RU2797785C1 - Semiconductor structure - Google Patents

Abstract

FIELD: semiconductor devices.

SUBSTANCE: semiconductor structure is proposed, which includes several first patterns located in a photoresist layer with a thickness of more than 1.2 mcm and placed in the first direction, and several second patterns located in the second direction. The first direction and the second direction form an interior corner. The first patterns have a first arrangement length in the first direction. The second patterns have a second arrangement length in the second direction. The total area of the first patterns and the second patterns is less than 1/2 of the product of the first arrangement length and the second arrangement length.

EFFECT: increasing the accuracy when combining different layers in the production process.

10 cl, 7 dwg

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority from Chinese Patent Application No. 202010804638.6, filed on August 12, 2020 with the National Intellectual Property Office of China and named "Semiconductor Structure", which is incorporated herein by reference in its entirety.

FIELD OF TECHNOLOGY

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology and, in particular, semiconductor structure.

BACKGROUND OF THE INVENTION

[0003] With the rapid development of semiconductor technology, the size of a semiconductor device is becoming smaller and smaller, and higher demands are placed on measurement accuracy when aligning different layers in a manufacturing process.

[0004] However, the ion implantation of some layers in the manufacture of a semiconductor device is relatively deep. High energy exposure is required during exposure, which can easily cause the marker graphic to be deformed or misapplied, so that the marker graphic has poor visual performance. This seriously affects the measurement accuracy, which leads to a decrease in the yield of suitable semiconductor devices.

DISCLOSURE OF THE INVENTION

[0005] In some embodiments, the present disclosure provides a semiconductor structure including:

[0006] several first patterns located in the first direction and placed in a layer of photoresist with a thickness of more than 1.2 microns, and several second patterns located in the second direction. The first direction and the second direction form an interior corner.

[0007] The first drawings have a first arrangement length in the first direction. The second patterns have a second arrangement length in the second direction. The total area of the first patterns and the second patterns is less than 1/2 of the product of the first arrangement length and the second arrangement length.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly describe the technical solutions in embodiments of the present disclosure or in the prior art, the drawings necessary for use in embodiments or illustrations of conventional technology will be briefly presented below. It is understood that the drawings in the illustration below represent only some embodiments of the present disclosure. Typically, those skilled in the art can also obtain other drawings in accordance with the drawings without doing creative work.

[0009] FIG. 1 is a schematic plan view of a semiconductor structure provided in the first embodiment;

[0010] in FIG. 2 is a schematic plan view of a semiconductor structure provided in the second embodiment;

[0011] in FIG. 3 is a schematic plan view of a semiconductor structure provided in the third embodiment;

[0012] in FIG. 4 is a schematic plan view of a semiconductor structure provided in the fourth embodiment;

[0013] in FIG. 5 is a schematic plan view of a semiconductor structure provided in the fifth embodiment;

[0014] in FIG. 6 is a schematic plan view of a semiconductor structure provided in the sixth embodiment;

[0015] in FIG. 7A shows a Qmerit measurement result of a conventional marker graphic;

[0016] in FIG. 7B shows the measurement result Qmerit of the marker graphic element provided in the second embodiment; And

[0017] in FIG. 7C shows the measurement result Qmerit of the marker graphic element provided in the fourth embodiment.

IMPLEMENTATION OF THE INVENTION

[0018] For the convenience of understanding the present disclosure, embodiments of the present invention will be described in more detail below with reference to the corresponding accompanying drawings. Some embodiments of the present disclosure are shown in the drawings. However, the present disclosure may be carried out in a variety of different ways, which are not limited to the embodiments described herein. On the contrary, these embodiments are presented in such a way that the described contents of the present disclosure will be more complete and complete.

[0019] Unless otherwise indicated, all technical and scientific terms used herein have the same meaning as generally understood by those skilled in the art to which this disclosure pertains. The terms used in the detailed description of embodiments of the present disclosure are used for the purpose of describing particular embodiments only and are not intended to limit the embodiments of the present disclosure. In addition, certain terms used throughout the description and the appended claims refer to specific elements. Those skilled in the art will recognize that manufacturers may refer to components by different names. This document does not intend to highlight elements with different names but the same functionality. In the following description and embodiments, the terms "including" and "include" are used in an open sense and thus should be interpreted as "including, but not limited to..." In the same way, the term "combine " is intended to express an indirect or direct electrical connection. Accordingly, if one equipment is connected to another equipment, the connection can be made by a direct electrical connection or by an indirect electrical connection between the other equipment and the connecting part.

[0020] It should be understood that although the terms "first", "second", etc. may be used in this document to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0021] The term "multiple" in embodiments of the present disclosure means "one or more".

[0022] With reference to FIG. 1, a semiconductor structure provided according to one embodiment of the present disclosure includes several first patterns 10 located in the first Ox direction and placed in a photoresist layer 100 with a thickness greater than 1.2 μm, and several second patterns 20 located in the second direction. Oh. The first direction Ox and the second direction Oy form an interior angle a, with 0°<a<180°. The first patterns 10 have a first alignment length L1 in the first direction Ox, and the second patterns 20 have a second alignment length L2 in the second direction Oy. The total area of the first patterns 10 is S1 and the total area of the second patterns 20 is S2, with S1+S2<0.5L1*L2.

[0023] For example, with continued reference to FIG. 1, with several first patterns 10 in the first Ox direction on a photoresist layer 100 with a thickness greater than 1.2 μm and several second patterns 20 in the second Oy direction, the first Ox direction and the second Oy direction form an internal angle a, with 0° <a<180°. The first patterns 10 have a first alignment length L1 in the first direction Ox, and the second patterns 20 have a second alignment length L2 in the second direction Oy, so that it can facilitate accurate measurement of the various layers in the semiconductor structure through the first patterns 10 and the second patterns 20. The first patterns 10 and the second patterns 20 are formed on the photoresist layer 100 with a thickness of more than 1.2 µm, and the photoresist provides good support for the first patterns 10 and the second patterns 20, so that the phenomenon of reduction in measurement efficiency and accuracy caused by deformation or misalignment of partial marker graphics elements during high-energy exposure is prevented. The total area of the first patterns 10 and the second patterns 20 is less than 1/2 the product of the first arrangement length L1 and the second arrangement length L2, which simplifies the arrangement of the plurality of first patterns and the plurality of second patterns, further improving the measurement accuracy and increasing the yield of manufactured semiconductor devices.

[0024] With reference to FIG. 2, in one embodiment of the present disclosure, the first patterns and the second patterns are gap patterns. The first patterns are shown as first rectangular through holes 11. A plurality of first rectangular through holes 11 are spaced in the first direction Ox and have a first arrangement length L1 in the first direction Ox. The second patterns are shown as second rectangular through holes 21. A plurality of second rectangular through holes 21 are spaced in the second direction Oy and have a second arrangement length L2 in the second direction Oy. The total area of the orthogonal projections of the various first rectangular through holes 11 onto the surface of the photoresist layer 100 and the orthogonal projections of the various second rectangular through holes 21 onto the surface of the photoresist layer 100 is less than 1/2 of the product of the first arrangement length L1 and the second arrangement length L2. The plurality of first rectangular through holes 11 and the plurality of second rectangular through holes 21 are used as marker graphics to realize accurate measurement using marker graphics. The photoresist layer 100 provides good support for the marker graphics, so that the phenomenon of reduction in measurement efficiency and accuracy caused by deformation or superimposition of partial marker graphics during high-energy exposure is prevented. The total area of the first patterns 10 and the second patterns 20 is less than 1/2 the product of the first arrangement length L1 and the second arrangement length L2, which simplifies the arrangement of the plurality of first patterns and the plurality of second patterns, further improving the measurement accuracy and increasing the yield of manufactured semiconductor devices.

[0025] In one embodiment of the present disclosure, with reference to FIG. 3, the first patterns are shown as first rectangular through holes 11. A plurality of first rectangular through holes 11 are spaced in the first Ox direction, and each has a width w1 ranging from 0.5 µm to 1.5 µm, and/or a distance d1 between located next to the first rectangular through holes 11 is in the range from 0.5 μm to 1.5 μm. The size of the first rectangular through hole 11 is set to ensure that during high energy exposure, the photoresist at the position of the first rectangular through hole can be exposed and developed. Meanwhile, the distances between the first rectangular through holes 11 are set to ensure that during high-energy exposure, the photoresist between the first rectangular through holes 11 cannot be destroyed. The resulting marker graphic has an excellent appearance, thus facilitating accurate measurement of the marker graphic. As shown in FIG. 7A and 7B, compared with the conventional marker graphic, the measured Qmerit value obtained by using the marker graphic in the present embodiment is relatively small and more convergent, indicating that the quality of the marker graphic in the present embodiment is higher. , and the resulting measurement result is more reliable and has higher accuracy.

[0026] In other embodiments of the present disclosure, the gaps between the first samples may be one or more circles, ellipses, triangles, or polygons.

[0027] In one embodiment of the present disclosure, continuing to refer to FIG. 3, the second patterns are defined as the second rectangular photoresist graphics elements 22. The plurality of second rectangular graphic elements 22 of the photoresist are spaced in the second direction Oy and have a second arrangement length L2 in the second direction Oy. The first patterns are defined as first rectangular through holes 11. A plurality of first rectangular through holes 11 are spaced in the first direction Ox and have a first arrangement length L1 in the first direction Ox. The total area of the first rectangular through holes 11 and the second rectangular photoresist graphics elements 22 is less than 1/2 of the product of the first arrangement length L1 and the second arrangement length L2. The width w2 of each second rectangular photoresist graphic element 22 is in the range of 1.5 µm to 3.5 µm, and the distance d2 between adjacent second rectangular graphic elements 22 of the photoresist is in the range of 0.5 µm to 1.5 µm. When the second patterns are photoresist graphics, in particular, the width of each second rectangular photoresist graphics 22 is larger than the distance between adjacent second rectangular photoresist graphics 22, in order to prevent destruction of the second rectangular photoresist graphics 22 when the photoresist layer is too thick, which contributes to the implementation of accurate measurement of marker graphic elements. Meanwhile, when using the first patterns related to the gap patterns and the second patterns related to the photoresist graphics, different types of patterns can be found in the marker graphics in the same layer or in the same marker graphics in the same layer. the same layer.

[0028] In one embodiment of the present disclosure, the distance from the first drawings to the second drawings is greater than the sum of the distance between the first drawings and the distance between the second drawings. With continued reference to FIG. 3, the first pattern is the first rectangular through hole 11, and the distance d1 between adjacent first rectangular through holes 11 is in the range of 0.5 µm to 1.5 µm. The second pattern is the second rectangular graphic element 22 of the photoresist, and the distance d2 between adjacent second rectangular graphic elements 22 of the photoresist is in the range from 0.5 μm to 1.5 μm. The distance between the first rectangular through hole 11 and the second rectangular photoresist graphic element 22 is greater than the sum of the distance d1 between adjacent first rectangular through holes 11 and the distance d2 between adjacent second rectangular graphic elements 22 of the photoresist, in order to make the boundary between the first rectangular through hole 11 and the second rectangular graphic element 22 of the photoresist and prevent influence on the measurement result.

[0029] In one embodiment of the present disclosure, with reference to FIG. 4, the first patterns are defined as the first rectangular photoresist graphics elements 12, and the second patterns are defined as the second rectangular photoresist graphics elements 22. A plurality of first rectangular graphic elements 22 of the photoresist are spaced in the first Ox direction and have a width w12 in the range of 2 µm to 3 µm. The distance d12 between the first rectangular graphic elements 12 of the photoresist is in the range of 1 µm to 1.5 µm. A plurality of second rectangular photoresist graphics elements 22 are spaced in the second direction Oy and have a width w2 in the range of 2 µm to 3 µm. The distance d2 between the second rectangular graphic elements 22 of the photoresist is in the range of 1 µm to 1.5 µm. When the first patterns and the second patterns according to the present embodiment are photoresist graphics, in particular, the width of the first rectangular photoresist graphics element 12 is larger than the distance between adjacent first rectangular photoresist graphics elements 12, and the width of the second rectangular photoresist graphics element 22 is larger, than the distance between adjacent second rectangular photoresist graphics elements 22 in order to prevent destruction of the first rectangular photoresist graphics elements 12 or the second rectangular photoresist graphics elements 22 when the photoresist layer is too thick. Especially when the thickness of the photoresist is larger than 1.2 µm, the widths and distances of the above-mentioned photoresist graphics provide an advantage in guaranteeing the quality of the marker graphics and realizing accurate measurement of the marker graphics. As shown in FIG. 7A and 7C, compared with the conventional marker graphic, the measurement value of Qmerit obtained by using the marker graphic in the present embodiment is relatively small and more convergent, indicating that the quality of the marker graphic in the present embodiment higher, and the measurement result obtained is more reliable and has higher accuracy. In other embodiments of the present disclosure, the photoresist graphics in the first patterns 10 and the second patterns 20 may be one or more of a circle, ellipse, triangle, or polygon.

[0030] With continued reference to FIG. 4, the various first rectangular photoresist graphics 12 are equally spaced in the first Ox direction, and the various second rectangular photoresist graphics 22 are evenly spaced in the second Oy direction, so that the difficulty of preparing the marker graphics is reduced while ensuring measurement accuracy of the marker graphics. elements.

[0031] In one embodiment of the present disclosure, with reference to FIG. 5, the interior angle between the first Ox direction and the second Oy direction is 90°, so that detection results in the X direction and the Y direction in the rectangular coordinate system can be conveniently achieved.

[0032] In one embodiment of the present disclosure, with reference to FIG. 6, the first graphics elements 30 and the second graphics elements 40 are also formed in the photoresist layer 100. The arrangement direction of the first graphics elements 30 is parallel to the arrangement direction of the first patterns 10, and the arrangement direction of the second graphics elements 40 is parallel to the arrangement direction of the second patterns 20. The first graphics elements 30 and the second graphics elements 40 are used to set the position and shape of the device semiconductor structure in the chip area. . The arrangement direction of the first graphics elements 30 is parallel to the arrangement direction of the first patterns 10, and the arrangement direction of the second graphics elements 40 is parallel to the arrangement direction of the second patterns 20, which can reduce the effect of photolithography conditions on the measurement results. The measurement result of the marker graphic elements can better reflect the actual situation of the first graphic elements 30 and the second graphic elements 40 in this region of the chip.

[0033] With continued reference to FIG. 6, the first graphics elements 30 are gapped graphics elements. The second graphics elements 40 are photoresist graphics elements. The first graphics elements 30 are gapped graphics that are compatible with the type of the first patterns 10, i. e. the first drawings 10 are also gapped graphics. The second graphics elements 40 are photoresist graphics elements that are compatible with the type of the second patterns 20, i. e. the second patterns 20 are also graphic elements of the photoresist. For example, with continued reference to FIG. 6, the first graphic element 30 is provided in the form of third rectangular through holes. The arrangement direction of the plurality of third rectangular through holes is parallel to the arrangement direction of the first patterns 10. The second graphics elements 40 are provided as fourth rectangular photoresist graphics elements, and the arrangement direction of the plurality of fourth rectangular photoresist graphics elements is parallel to the arrangement direction of the second patterns. This ensures that the graphic elements in the chip area are compatible with the type of marker graphic elements, so that the measurement result of the marker graphic elements can better reflect the actual situation of the graphic elements in the chip area.

[0034] In one embodiment of the present disclosure, with continued reference to FIG. 6, the width w3 of each of the first graphics elements 30 is in the range of 0.5 µm to 1.5 µm. The width w4 of each of the second graphics elements 40 is in the range of 1.5 µm to 3.5 µm to ensure the quality of the first graphics elements 30 and the quality of the second graphics elements 40, so that the position and shape of the device semiconductor structure in a given area of the chip can be determined. exactly.

[0035] It should be noted that the embodiments mentioned above are for illustrative purposes only and are not intended to limit the disclosure.

[0036] All embodiments in the present description are described incrementally. The content essentially described in each embodiment differs from those described in other embodiments. The same or similar parts of all embodiments refer to each other.

[0037] Various technical features in the embodiments described above may be combined arbitrarily. For the convenience of a simple description, not all possible combinations of various technical features in the above embodiments are presented. However, as long as the combinations of these technical features do not contradict each other, they should be considered as falling within the scope of protection of the present description.

[0038] The above embodiments represent only a few embodiments of the present disclosure, and descriptions that are specific and detailed should not be construed as limiting the scope of patent protection of the present disclosure. It should be noted that changes and improvements may also be made by those skilled in the art without departing from the intent of the present disclosure, but all such changes and improvements are within the protection scope of this disclosure. Thus, the scope of patent protection of the present disclosure should be determined by the appended claims.

Claims (19)

1. Semiconductor structure containing: one or more first patterns located in the first direction and placed in a photoresist layer with a thickness of more than 1.2 μm, and one or more second patterns located in the second direction, while the first direction and the second direction form an internal corner; wherein the first drawings have a first arrangement length in the first direction; the second patterns have a second arrangement length in the second direction; and the total area of the first patterns and the second patterns is less than 1/2 of the product of the first arrangement length and the second arrangement length. 2. The semiconductor structure of claim 1, wherein the first patterns and the second patterns are gap patterns. 3. The semiconductor structure of claim 1, wherein the first patterns are gap patterns, and wherein at least one of the following is applied: each of the first patterns has a width in the range of 0.5 µm to 1.5 µm; or the distance between two adjacent first patterns is in the range of 0.5 µm to 1.5 µm. 4. The semiconductor structure of claim 3, wherein the second patterns are photoresist patterns, and wherein at least one of the following is applied: each has a width ranging from 1.5 µm to 3.5 µm; or the distance between two adjacent second patterns is in the range of 0.5 µm to 1.5 µm. 5. Semiconductor structure according to claim 1, in which the first patterns and the second patterns are photoresist patterns, each of which has a width in the range from 2 μm to 3 μm; the distance between two adjacent first patterns is in the range from 1 µm to 1.5 µm; and the distance between two adjacent second patterns is in the range of 1 µm to 1.5 µm. 6. The semiconductor structure of claim 1, wherein the first patterns are evenly spaced in the first direction and the second patterns are evenly spaced in the second direction. 7. The semiconductor structure according to claim 1, wherein the internal angle between the first direction and the second direction is 90°. 8. Semiconductor structure according to claim 4, in which: one or more first graphic elements and one or more second graphic elements are also formed in the photoresist layer; the arrangement direction of the first graphical elements is parallel to the first direction; and the arrangement of the second graphical elements is parallel to the second direction. 9. The semiconductor structure of claim 8, wherein the first graphics elements are gapped graphics elements and the second graphics elements are photoresist graphics elements, and in which the width of each of the first graphic elements is in the range from 0.5 μm to 1.5 μm, and the width of each of the second graphic elements is in the range from 1.5 μm to 3.5 μm. 10. The semiconductor structure of claim 4, wherein the distance from the first patterns to the second patterns is greater than the sum of the distance between the first patterns and the distance between the second patterns.

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