RU2523064C1 - Forming of multilevel copper interconnections of micro ic with application of tungsten rigid mask - Google Patents

Abstract

FIELD: metallurgy.

SUBSTANCE: method comprises the process of dual Damascene ICs formation through duplex rigid mask including application of insulation dielectric ply on the plate, conductors of IC multilevel metallisation being formed in dielectric body. Bottom and top layers of silicon dioxide rigid mask are applied over said insulation dielectric. Topological mask of resist is formed on top ply of duplex rigid mask to etch said top ply by said topological mask. Residual resist is removed from the surface of topological pattern formed in top layer of duplex rigid mask. Bottom layer of duplex silicon dioxide rigid mask is etched by topological patter of said top ply of duplex rigid mask. Trenches and transition contact plies are etched in every insulation dielectric ply by topological patter in duplex rigid mask. Formed trenches and transition contact openings are filled with metallisation ply and removal of residual volume of applied metal from the plate surface. Note here that tungsten ply is used as the material of rigid mask top ply.

EFFECT: higher reliability and yield.

2 cl, 10 dwg

Description

Technical field

The invention relates to the manufacturing technology of semiconductor devices and ultra-large integrated circuits (VLSI) in terms of the formation of multilevel metal compounds.

State of the art

The level of modern microelectronics is determined by the degree of integration of elements in a single device and / or on a separate semiconductor chip chip. The degree of integration directly depends on the minimum dimensions of the elements and the distances between them. The complexity of modern integrated circuits is such that the organization of the electrical connection of millions of elements requires many levels of metal connections with transverse dimensions of conductors comparable to the minimum size of elements of the order of ten nanometers. By decreasing the wiring step and adding consecutive conductive layers, multilevel metallization satisfies the needs of higher density circuits (V. Agarwal, M.S. Hrishikesh, SW Keckler and D. Burger, Clock rate versus IPC: the end of the road for conventional microarchitectures. Proceedings of the International Symposium on Computer Architecture, pp. 248-259, 2000.) The available number of metal layers has tripled in the past 10 years so that current technologies (90-180 nm) have 6-10 levels. At the same time, to reduce electrical losses, it is required to use materials with high conductivity as conductors, and for insulation - layers of dielectric materials with the lowest possible dielectric constant, the so-called low-k dielectrics.

Currently, in the production of VLSI, aluminum and copper are used as the main material for conductors of multilevel metal compounds. Copper, as a rule, is used in VLSI with design standards of 130 nm or less. This is due to the fact that with a decrease in the cross section of the conductors and the distance between the conductors, which directly depend on the linear dimensions of the elements, the resistance of the electrical wiring and the electrical capacitance of closely located conductors begin to increase significantly. This increases signal propagation delays in the VLSI and power loss. The transition from aluminum conductors in the structure of VLSI to copper is due to a lower resistivity of copper compared to aluminum. The transition to the use of copper required a change in the technological process of forming conductors. Since copper does not form volatile compounds with boiling or sublimation temperatures compatible with semiconductor technology, it is not possible to use traditional industrial technologies for dry etching through a photoresist mask. Therefore, the Damascene process was developed (the name (damascene) has already been established in Russian literature, in which the trench of the future conductor is etched in the dielectric layer, which is then filled with copper, thereby creating an electrical connection of the elements. This process generally includes the steps of:

- the formation of a dielectric layer with which the conductor will be surrounded on the sides;

- the formation of a mask for etching the trench in the dielectric layer;

- etching of the trench in the dielectric layer;

- applying a barrier layer to prevent the interaction of copper with surrounding materials and degradation of the latter;

- application of the germ layer for subsequent deposition of copper;

- electrochemical deposition of copper with the filling of the trench;

- chemical-mechanical polishing of copper, which removes the deposited copper layer from the surface of the deposited dielectric layer and leaves copper inside the etched trenches that form the electrical wiring conductors of the corresponding microcircuit level.

In addition, for the formation of not only conductors of the same level, but also contacts through transition windows to the underlying level of electrical wiring, the Damascene process was modified and received the name Double Damascene. Thus, trenches (position 95 of Figure 1) and transition contact windows (position 94 of Figure 1) are formed at one wiring level (United States Patent 5635423, Simplified dual damascene process for multi-level metallization and interconnection structure. 1997).

CMOS technology, the main parameters of which are set out in the International Semiconductor Roadmap (ITRS), for the level of 45 nm and below provides the use of low-k dielectric with a dielectric constant in the range from 2.3 to 2.9 for the first metal level (ITRS Edition Reports and Ordering. Interconnect 2010 tables. 2010) (Table 1)

Table 1 Low-k dielectric interconnect requirements DRAM 1/2 step (nm) 51.69 45.00 40.09 35.72 31.82 28.35 25.26 22.50 20.05 17.86 15.91 14.17 MPU / ASIC Metal 1/2 pitch (nm) 53.51 45.00 37.84 31.82 26.76 23.84 21.24 18.92 16.86 15.02 13.38 11.92 Inter-level dielectric - dielectric constant (k 2.9-3.3 2.6-2.9 2.6-2.9 2.6-2.9 2.4-2.8 2.4-2.8 2.4-2.8 2.1-2.5 2.1-2.5 2.1-2.5 2.0-2.3 2.0-2.3 Inter-level dielectric - dielectric constant (k) 2.5-2.8 2.3-2.6 2.3-2.6 2.3-2.6 2.1-2.4 2.1-2.4 2.1-2.4 1.9-2.2 1.9-2.2 1.9-2.2 1.7-2.0 1.7-2.0

Such a coefficient of dielectric constant in the current level of development of material science is achieved only in dielectrics made of porous materials.

In the closest analogue, a double Damascene route is used to form conductors and contacts in a porous low-k dielectric (United States Patent US 2010/0022091. Method for plasma etching porous low-k dielectric layer. 2010). However, some complex problems arise in the process of integrating dielectric materials with a porous structure into the double Damascene route. Plasma etching followed by removal of the photoresist and purification of porous materials from polymers in narrow structures alter the properties of the porous material, which affect the electrical and reliability properties (K. Maeh, MR Baklanov, D. Shamiryan, F. Iacopi, SH Brongersma, ZS Yanovitskaya. Low dielectric constant materials for microelectronics J. Appl. Phys. 93 (2003) 8793).

There are two types of masks for forming a topological pattern in low-k material: a soft mask (photoresist) and a hard mask (inorganic materials). The technology using a photoresist mask is quite simple, because it does not require deposition and removal of additional layers, except for the photoresist and organic antireflection coating (ARC), which separates the photoresist and the stack from the bottom. In the case of applying a rigid mask, it is deposited on top of the low-k, dielectric, and then ARC and a photoresist are applied. The plasma etching process is divided into 4 stages: (1) ARC opening, (2) hard mask etching, (3) photoresist / ARC cleaning, and (4) low-k dielectric etching through the hard mask.

Although the process using a resistive mask is preferable from the point of view of costs, however, it has several significant disadvantages. For organic low-k polymers, the resistive mask is excluded, since the material to be etched and the material of the resistive mask belong to the same class of materials: organic polymers. Thus, the selectivity of etching a low-k dielectric to a resistive mask is very small and upon subsequent purification from polymers, the plasma will etch the low-k dielectric as quickly as it removes the photoresist. Thus, a rigid mask is an absolute requirement for the formation of structures from organic polymers.

For silica hybrid materials, a resistive mask may not always be used. Due to the different nature of the resistive mask and the low-k dielectric, the main part of the composition of which are SiOCH groups (strictly speaking, it’s not completely different, since SiOCH also contains individual CH3 hydrocarbon groups in its composition), however, there are conditions in which the selectivity of SiOCH etching to the resistive mask allows the formation of a given topological contact structure.

The process of subsequent removal of the resistive mask should be optimized so as not to damage the low-k material, since the hydrophobicity of SiOCH materials depends precisely on the presence of -CH3 groups, while the plasma used to remove the resist also removes low-k from the surface material these hydrocarbon groups. Already in 65 nm technology, it is impossible to ignore damage to the surface and side wall of the trench caused by plasma to remove the resist. A further reduction in critical dimensions (CD) brings two new challenges: firstly, the thickness of the resist must be reduced to provide the required resolution, and secondly, narrow lines do not allow deep damage to the side walls.

Based on the foregoing, a rigid mask can be considered as the only viable option for the formation of SiOCH low-k dielectrics for technologies below 45 nm (Mikhail R. Baklanov, Jean-Francois de Marneffe, Denis Shamiryan, Adam M. Urbanowicz, Hualiang Shi, Tatyana V. Rakhimova Huai Huang and Paul S. Ho. Plasma processing of low-k dielectrics. J. Appl. Phys. 112, 000000 (2012)).

There are two main types of hard masks: dielectric and metal. The dielectric rigid masks can be based on silicon (SiO2, Si3N4 or SiC) or based on carbon (amorphous carbon). Hard metal masks usually consist of metal nitrides, such as TaN or TiN. Metal and silicon oxides are not very suitable for etching organosilicate glasses because their deposition involves the use of oxygen-containing oxidizing agents and they can lead to degradation of low-k material. Si masks are best suited for the low-k organic polymer because they have a high selectivity for etching to the low-k dielectric in a plasma based on H2 or O2, which allows the use of relatively thin masks.

For SiOCH materials, a rigid mask based on Si is not technologically advanced (Fig. 2a), since both materials of a low-k dielectric and a rigid mask contain Si, because of this it is difficult to achieve the required etching selectivity, which leads to faceting and rounding of the upper part of the opened contact (N. Posseme, T. David, M. Darnon, T. Chevolleau, O. Joubert. Impact of Hard Mask Composition and Etching Chemistry on Porous Ultra Low-k Material Modification. Int. Conf. Microelectron. Interfaces 2005). Low selectivity requires the deposition of a thick layer of a hard mask, which affects the resolution of the process, and also increases the effective value of the dielectric constant k in the contact structure, if you leave the hard mask on the low-k surface after the etching process. Again, removing a Si-based rigid mask is a problem because it has a composition similar to a low-k dielectric.

Recent development solutions for SiOCH formation include metal hard masks and amorphous carbon hard masks. In this case, after ARC removal, the hard mask metal is usually etched in HBr-Cl2 plasma, while amorphous carbon is usually etched using N2-O2 or N2-H2 plasma.

Since the material is protected by a hard mask during the opening of the ARC low-k, minor damage is possible at this stage. Nevertheless, care must be taken when opening the stiff mask, especially when using a stiff mask made of amorphous carbon, in which case a thin dense SiO2 or SiC film can act as an effective protection against diffusing radicals. In the case of a metal hard mask (e.g., TiN) during low-k etching, high selectivity of SiOCH / TiN is achieved because the main etching product - TiF4 - has a relatively low volatility (boiling point at atmospheric pressure 284 ° C) compared to SiF4 (boiling point at atmospheric pressure - 86 ° C). From this point of view, TaN is less preferred since its main etch product TaF5 is more volatile than TiF4. In addition, the metal of the stiff mask does not contribute to an increase in the effective value of the dielectric constant k, because the stiff mask is removed by SMR after filling the contact with metal (M. Darnon, T. Chevolleau, D. Eon, L. Vallier, J. Torres, O. Joubert. Etching characteristics of TiN used as hard mask in dielectric etch process. J. Vac. Sci. Technol. 24 (2006) 2262.).

The main disadvantages of using metal hard masks are metal-containing etching residues that are very difficult to remove (Figure 2b). The micromasking effect is caused by low-volatility TiN etching products that reprecipitate on the surface of the etched structure. The release of mechanical stresses when using TiN can lead to serious distortions (the so-called "waviness") in the bands of metal and low-k dielectric in narrow lines with a high aspect ratio during etching, which will be shown below.

To integrate porous SiOCH dielectrics into the double Damascene architecture, a method of using a two-layer rigid mask was developed to prevent direct exposure to porous dielectric material of oxygen plasma (O. Hinsinger, R. Fox, E. Sabouret, C. Goldberg, C. Verove, W. Besling , P. Brun, E. Josse, C. Monget, O. Belmont, J. Van Hassel, BG Sharma, JP Jacquemin, P. Vannier, A. Humbert, D. Brunei, R. Gonella, E. Mastromatteo, D. Rebert, A. Farcy, J. Muel. Demonstration of an extandable and industrial 300 mm BEOL integration for the 65-nm technology node. Int. Electron. Devices Meeting (2004).

Closest to the technical nature of the present invention is a method of forming multilevel copper interconnects VLSI using a layer of titanium nitride as a hard mask (M. Darnon and T. Chevolleau, T. David, J. Ducote, N. Posseme, R. Bouyssou, F Bailly, D. Perret, O. Joubert. Patterning of porous SiOCH using an organic mask: Comparison with a metallic masking strategy. J. Vac. Sci. Technol. In (28) No. 1, Jan / Feb 2010 149-156) . The formation of SiOCH trenches was performed using a rigid mask made of TiN metal on the SiO2 sublayer.

The stack consists of a 40 nm thick SiO2 (TEOS) layer, which is deposited on a porous low-k dielectric before the 45 nm TiN metal hard mask is deposited (Figure 3). However, when etching porous low-k dielectrics in a fluorocarbon plasma through a rigid TiN mask, the formation of non-volatile Ti etching deposits is induced based on the by-product that is produced during reprecipitation on the side walls of the trench and leads to serious distortion of the profile (Figure 4).

Reprecipitation of by-products on the side walls of porous low-k dielectrics depends on the presence of a photoresist layer on the surface of the TiN hard mask.

Consider the following examples:

1) TiN was opened, then the photoresist was removed from the entire plate except one section, after which the dielectric material was etched. Those. the main part of the plate is etched through the TiN hard mask and only one section through the TiN hard mask protected by a photoresist (Figure 5). On the main part of the plate, reprecipitation of the products after etching was observed, while the part of the plate covered by the photoresist was also with precipitated products. The cause of the global effect of product deposition is TiN atomization and gaseous reprecipitation.

2) TiN was opened, then the photoresist was removed from one section, after which the dielectric material was etched. Those. the main part of the plate is etched through a TiN hard mask protected by a photoresist, and only one section through a TiN hard mask without a photoresist (Fig.6). On the main part, no reprecipitation of products was found, except for the area not protected by photoresist. The cause of the local particle deposition effect is the spraying of TiN from the surface and reprecipitation from the gas phase.

Since the reprecipitation of by-products on the side walls of porous low-k dielectrics depends on the presence of a photoresist layer on the TiN surface of the rigid mask during contact formation, photoresist removal is necessary after opening the low-k dielectric. However, for porous material, as shown by the authors (M. Darnon, T. Chevolleau, T. David, N. Posseme, J. Ducote, C. Licitra, L. Vallier, O. Joubert, J. Torres. Modifications of dielectric films induced by plasma ashing processes: Hybrid versus porous SiOCH materials. J. Vac. Sci. Technol. 26, 1964 (2008)) degradation of low-k dielectrics exposed in the plasma to remove the photoresist. Removal in NH3 and O2 in the plasma causes carbon depletion and moisture absorption, the low-k dielectric material becomes hydrophilic and its dielectric constant increases greatly. Plasma CH4 leads to severe carbon depletion (depletion of CH3) without moisture absorption and the formation of a thin layer of carbon on the surface. The low-k dielectric material remains hydrophobic, the dielectric constant varies slightly. Subsequently, an increase in the dielectric constant is associated with water capture more than with the depletion of the methyl group. The low-k dielectric material should remain hydrophobic.

Using an optimized recipe for etching a porous low-k dielectric (CF4 / Ar), trenches up to 100 nm wide are possible (M. Darnon and T. Chevolleau, T. David, J. Ducote, N. Posseme, R. Bouyssou, F. Bailly, D. Perret, O. Joubert, Patterning of porous SiOCH using an organic mask: Comparison with a metallic masking strategy. J. Vac. Sci. Technol. In (28) No. 1, Jan / Feb 2010 149-156). With smaller sizes, there is a waviness of the dielectric lines (Fig.7). The phenomenon of line waviness is explained by the release of high residual stresses of titanium nitride, which deforms the less rigid line of the porous low-k dielectric. The presented results show that the process of forming a trench of a porous low-k dielectric depends on the material of the rigid mask.

The etching rate of silicon-based dielectric layers in a fluorine-containing plasma almost linearly depends on the bias applied to the sample. This means that the treated sample is specially subjected to sufficiently intense ion bombardment to achieve acceptable etching rates, which in turn leads not only to an increase in the etching rate of the mask, but also to the formation of a developing chamfer at the edge of the masking coating (the so-called facet mask). This effect can cause premature “drift” of the edge of the mask (with low selectivity or the wrong choice of thickness of the mask) and, as a result, the slope of the etching profile.

The presented results show that the profile shape of the formed trench in a porous low-k dielectric, the level of contamination of its walls and the level of depletion of the surface layers with useful carbon-hydrogen groups depends on the choice of mask material.

Disclosure of the invention

As shown above, when using a rigid TiN mask during the formation of multilevel copper VLSI interconnects, a number of problems arise that affect the output of suitable multilevel copper metallization, and therefore the output of suitable VLSI in general:

- A narrow technological window of etching processes due to the poor volatility of titanium fluorohalides;

- Barrel-shaped etching profile due to reprecipitation of products from the gas phase due to TiN sputtering;

- The waveform of narrow and high lines due to relaxation of residual stresses;

- Degradation of low-k dielectrics exposed to plasma to remove photoresist when forming a topological pattern using a TiN hard mask;

- The complexity of the route and its more expensive implementation when forming a low-k dielectric through a TiN hard mask, since the preliminary etching of the layer of the most rigid TiN mask and subsequent etching through it of the SiO2 sublayer and then the low-k dielectric must be carried out in different reactors. This is due to the fact that the etching of TiN is carried out, as a rule, in a plasma based on chlorine, and the etching of dielectrics in a plasma based on fluorine and carbon-containing compounds.

The aim of the present invention is to increase reliability and increase the percentage of yield of CMOS VLSI products during the formation of multilevel copper interconnects due to:

- simplification of the technological route for creating a rigid mask;

- elimination of distortions and defects when opening trenches and transition windows through a hard mask;

- eliminating the degradation of the low-k dielectric due to the avoidance of plasma contact to remove the photoresist from the porous surface of the low-k dielectric.

These goals are achieved if the layer of metallic tungsten (W) is used instead of a layer of titanium metal nitride (TiN) in the production route of CMOS VLSI during the formation of multilevel copper interconnects as a rigid mask.

Distinctive features in relation to the prototype, which characterize the invention, which are also essential features, is the development of a method for forming multilevel copper VLSI interconnects (Fig. 8) without changing the design topology parameters (i.e., reducing the linear dimensions). Instead of the material of the upper layer of the TiN rigid mask of the prototype, we use another material of the upper layer of the rigid mask W.

The technical result of the proposed solution is the formation of a given etching profile that meets the requirements for the formation of contacts and trenches.

This technical result is achieved due to the fact that during the formation of multilevel copper VLSI interconnects by the double Damascene process through a two-layer rigid mask, including the deposition of an insulating dielectric layer on a plate, in whose body conductors of multilevel metallization of an integrated circuit will be formed, deposition of a lower two-layer rigid layer on top of the insulating dielectric masks of silicon dioxide and the upper layer of a two-layer rigid mask, the formation on the upper layer of a two-layer rigid mask skiing of a topological mask from a resist, etching the upper layer of a two-layer rigid mask by a topological mask from a resist, removing the residual resist from the surface of a topological pattern formed in the upper layer of a two-layer rigid mask, etching the lower layer of a two-layer rigid mask of silicon dioxide according to the topological pattern of the upper layer of a two-layer rigid mask , etching of trenches and transition contact windows in an insulating dielectric layer according to the topological pattern in a two-layer rigid mask, filling spheres trenches and transition contact windows with a metallization layer and removal of an excess volume of deposited metal from the surface of the plates, a tungsten layer is used as the material of the upper layer of the rigid mask.

The thickness of the upper layer of tungsten of a two-layer rigid mask is from 25 nm to 100 nm.

Graphic images illustrating the invention

Figure 1 - Cross-section of a semiconductor device manufactured in accordance with the invention of the States Patent 5635423.

Figure 2 - Trenches of porous SiOCH etched through a rigid mask (a) SiO2, (b) TiN.

Figure 3 is a stack diagram of a porous low-k dielectric with a two-layer rigid SiO2 / TiN mask.

4 is a SEM cross-section of the structure of a porous dielectric etched through a TiN rigid mask.

Figure 5 - The nature of the precipitation of TiFx, the effect of local masking.

6 - The nature of the precipitation of TiFx, the effect of global masking.

7 - Curvature of the lines of porous SiOCH etched through a rigid TiN mask.

Fig. 8 is a diagram of the formation of a porous low-k dielectric using a two-layer rigid W / SiO2 mask in accordance with our invention.

Fig. 9 is a diagram of a stack of a porous low-k dielectric with a two-layer rigid W / SiO2 mask.

Figure 10 - Profile structure of W / SiO ₂ . The initial thickness of W is 55 nm. Process parameters: W _ICP = 600 W, W _cm = 80 W (-90 V), P = 6 mTorr, t = 60 sec.

The implementation of the invention

The invention is implemented as follows (Fig. 8). The interconnect stack includes substrate 1, dielectric layer 2 (thermal oxide, TEOS, doped oxide, etc.), metal layer 3 (copper) and stop layer 4 (non-conductive materials, films based on SiC and SiCN), porous low- k dielectric 5, a masking layer 6 (low temperature oxide, TEOS,), which is used as the lower layer of the two-layer rigid mask, a masking layer 7 (tungsten) which is used as the upper layer of the two-layer rigid mask, and an electron resist layer 8 (Fig. 8 A )

First, a transition contact window is formed by forming a topological pattern in the upper layer of a two-layer rigid mask 7 through an electron-resistive mask 8 by plasma-chemical etching. Then the remnants of the electron-resistive mask 8 are removed in the plasma (Fig.8 B) in the same reactor.

After removal of the electron-resistive mask 8, the process of plasma-chemical formation of the transition contact window in the porous low-k dielectric layer 5 to the stop layer 4 through the lower layer 6 of the two-layer rigid mask formed by the topology of the upper layer 7 of the two-layer rigid mask is carried out (Fig. 8B).

Since the formation of a topology in a rigid mask and the subsequent etching of a low-k dielectric are carried out in fluorine-containing plasmas, there is no need to separate these processes into different reactors.

After the formation of the transition contact window in the layer of porous low-k dielectric 5, the remains of the upper layer of tungsten 7 of the two-layer rigid mask are removed in the plasma and the surface of the plate is cleaned by dry and liquid cleaning methods (Fig. 8 G).

After the transition contact window is formed, an interconnect trench is formed along the traditional double Damascene route, for this a new stack is formed by deposition of the planarizing sacrificial layer 9 (ARC, SOG), which fills the previously formed transition contact windows. Next, the upper layer of the two-layer rigid mask 10 of tungsten is deposited again, on which an electron resist 11 is applied (Fig. 8 D).

The formation of a trench of interconnects occurs by forming a topological pattern in the upper layer of a two-layer rigid mask 10 through an electron-resistive mask 11 by plasma-chemical etching methods (Fig. 8 E).

After the formation of the upper layer 10 of the two-layer rigid mask according to the topology of the trench, the process of plasma-chemical etching of the sacrificial layer 9 by the topology of the trench to the lower layer 6 of the two-layer 4 rigid mask is carried out (Fig. 8 G).

Then, the process of plasma-chemical formation of the trench in the porous low-k dielectric 5 is carried out through the lower layer 6 of the two-layer rigid mask according to the topology of the trench formed earlier in the sacrificial layer 9 (Fig. 8 H).

After the formation of the trench in a porous low-k dielectric 5 by plasma-chemical methods, the remnants of the upper layer 10 of the two-layer rigid mask and the sacrificial layer 9 are removed (Fig. 8 I).

Further, according to the topology of the transition contact window, the stop layer 4 is etched and the contact is opened to the underlying metal layer. Then, liquid cleaning of the surface of the plate is carried out (Fig. 8 K).

Next, the process of conformal deposition of the barrier layer and the metal layer of the conductor 12 (Copper) (Fig. 8 L) takes place.

Then, by the method of chemical-mechanical polishing, the remnants of the metal layer of the conductor 12 are removed together with the lower layer 6 of the two-layer rigid mask (Fig. 8 M).

This forms one level of wiring. The next level of wiring is formed in a similar manner described above, while the previously formed level of wiring acts as a substrate (position 1 of Fig. 8). Thus, multilevel metal compounds are formed.

Plasma-chemical etching of the reduced multilayer structure was carried out using a high-density plasma process reactor using reactive-ion etching. The installation includes: a vacuum system (pumping system), which includes a turbomolecular pump, an oil-free mechanical pump, a foreline and bypass line, vacuum valves and fittings, vacuum 1 sensors to monitor the residual and working vacuum. Plasma-chemical reactor, includes:

- a plasma source with inductive excitation of the plasma and a magnetic system to increase the plasma density and radial uniformity of its parameters;

- gas distributor, providing a uniform distribution of gas flows and the possibility of their regulation in the deposition zone;

- a heated table-holder plates with the supply of gaseous helium under the plate to equalize the temperature distribution on the plate and improve thermal contact of the latter with the holder.

- gas inlet control system (5 channels, each of which includes a quick-response gas mass flow controller and 2 shut-off valves);

- An RF generator with a matching device with a plasma excitation inductor;

- RF generator with matching device for applying bias to the plate holder;

- a system for monitoring and maintaining the temperature of the plate;

- a lock chamber for individual loading of plates.

The etching rate was determined by the loss of material thickness during etching. Profiles of the formed structures were examined using scanning electron microscopy (SEM).

In the process of plasma chemical anisotropic etching of the tungsten layer, mixtures of SF6 (oxygen) with oxygen were used as working gases. All processes were carried out in the range of maintaining the temperature of the plate 4-25 ° C. As working samples, KDB-10 silicon wafers with an orientation of (100) were used, onto which SiO2 layers (stop layer 50–400 nm thick) and a tungsten layer 25–100 nm thick were deposited (Fig. 9). As a mask, an PMMA-950K-A2 electron resistor was used, as well as a TOK SAR 112A3 resist.

We carry out preliminary estimates of the optimal thickness of the masking layers of tungsten for the formation of a second layer of SiO2 double mask for etching porous low-k dielectrics. For slots with a width of 50 nm, the aspect ratio without taking into account the height of the first layer of the mask becomes 400 nm / 50 nm = 8, which will greatly slow down the etching process in narrow slits. Optimal thicknesses are tungsten layers, about 10 times thinner than the thickness of the low-k dielectric layer. The small thickness of the tungsten coating allows the use of small thickness electron resistors, which in turn leads to an increase in the resolution for electron lithography operations. Therefore, the layer thickness for W-based masks is selected in the range from 25 nm to 100 nm.

In turn, for etching a layer of a porous low-k dielectric with a thickness of 400 nm through masks of thickness, technological processes are required that provide high selectivity with respect to the hard mask of W (taking into account the faceting of the mask) of at least 15.

To achieve these selectivity values, we used mixtures commonly used for etching silica, where strong polymer-forming gases, such as C ₄ F _8, are used as the main gas supplier of fluorocarbon radicals. Correct selection of the composition of the gas mixture applied to the sample, the RF bias, and the working temperature of the sample make it possible to maintain the thickness of the fluoropolymer layer (about 3 nm) necessary for ensuring selectivity on the tungsten surface, which leads to a large difference in the etching rates of the dielectric and mask. The process of etching the dielectric was carried out in the same technological reactor as the etching of the first layer of the rigid mask.

Figure 10 shows the etching profile of the second silicon dioxide layer to an etching depth of 240 nm through the mask of the first layer W with an initial thickness of 32 nm of a double rigid mask to form porous low-k dielectrics with a minimum size of 50 nm. The process demonstrates low defectiveness and the absence of contamination at the bottom of the pickled trenches. In this process, etching selectivity with respect to the tungsten mask of at least 15 was achieved, while the vertical profile in the lower part of the mask indicates the possibility of masking while continuing the etching process.

Thus, the use of technology, the so-called double hard mask, allows the formation of porous low-k dielectrics for technology 45 nm and below. As materials for the double rigid mask, tungsten was selected as the first, upper layer from 25 nm to 100 nm thick and silicon oxide as the second lower layer covering the porous low-k dielectric from 30 to 300 nm thick.

Claims (2)

1. A method for forming multilevel VLSI copper interconnects according to the double Damascene process through a two-layer rigid mask, including applying an insulating dielectric layer to a plate, in whose body conductors of multilevel metallization of an integrated circuit will be formed, applying a lower layer of a two-layer rigid silicon dioxide mask and an upper layer over the insulating dielectric a two-layer rigid mask, the formation on the upper layer of a two-layer rigid mask of a topological mask from a resist, etching of the upper layer of a two-layer rigid mask according to the topological mask of the resist, removing the residual resist from the surface of the topological pattern formed in the upper layer of the two-layer rigid mask, etching the lower layer of the two-layer rigid mask of silicon dioxide according to the topological drawing of the upper layer of the two-layer rigid mask, etching trenches and transition contact windows in insulating dielectric layer according to the topological pattern in a two-layer rigid mask, filling the formed trenches and transition contact windows to the layer metallization and removing excess volume of the supported metal with surface plates, characterized in that the upper layer hard mask material layer using tungsten. 2. The method according to claim 1, characterized in that the thickness of the upper layer of tungsten of a two-layer rigid mask is from 25 nm to 100 nm.

Images