KR960009074A - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

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Publication number
KR960009074A
KR960009074A KR1019950025445A KR19950025445A KR960009074A KR 960009074 A KR960009074 A KR 960009074A KR 1019950025445 A KR1019950025445 A KR 1019950025445A KR 19950025445 A KR19950025445 A KR 19950025445A KR 960009074 A KR960009074 A KR 960009074A
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South Korea
Prior art keywords
semiconductor substrate
semiconductor
electrode
forming
insulating film
Prior art date
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KR1019950025445A
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English (en)
Inventor
다쯔오 스기야마
슈지 히라오
고사쿠 야노
노보루 노무라
Original Assignee
모리시다 요이치
마쯔시다 덴키 산교 가부시키가이샤
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Application filed by 모리시다 요이치, 마쯔시다 덴키 산교 가부시키가이샤 filed Critical 모리시다 요이치
Publication of KR960009074A publication Critical patent/KR960009074A/ko

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Abstract

제1반도체 기판 표면에 제1전극 및 제1전극용 절연막을 형성하는 동시에, 제2반도체 기판 표면에 제2전극 및 제2전극용 절연막을 형성한다. 제1반도체 기판 표면에는 일정한 주기를 갖고 단면이 톱니 모양의 요철 패턴이 스트라이프 모양으로 형성되어 있는 동시에, 제2반도체 기판 표면에는 제1반도체 기판 표면 요철 패턴에 대해 180도 위상이 어긋난 톱니모양의 요철 패턴이 스트라이프 모양으로 형성되어 있다. 제1반도체 기판과 제2반도체 기판은 표면의 요철 패턴이 서로 맞물리는 듯한 상태로 접합하여 있다.

Description

반도체 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 관한 반도체 장치의 단면도.

Claims (25)

  1. 반도체 장치는, 기판 위에 형성된 제1반도체 소자와, 기판 표면에 형성되고 상기 제1반도체 소자와 전기적으로 접속된 복수의 제1전극과, 기판 표면에 형성되고 상기 복수의 제1전극끼리 절연하는 제1절연층과, 상기 제1전극 및 제1절연층의 표면에 형성된 복수의 철부를 갖는 제l반도체 기판과, 기판위에 형성된 제2반도체소자와, 기판 표면의 상기 제1반도체 기판의 상기 복수의 제1전극과 대응하는 부위에 형성되고 상기 제2반도체 소자와 전기적으로 접속된 복수의 제2전극과, 기판 표면에 형성되고 상기 복수의 제2전극끼리 절연하는 제2절연층과, 상기 제2전극 및 제2절연층 표면의 상기 제1반도체 기판의 복수 철부 각각과 대응하는 부위에 형성된 복수의 요부를 갖는 제2반도체 기판을 구비하고, 상기 제1반도체 기판과 상기 제2반도체 기판은 상기 제1반도체 기판의 복수 철부와 상기 제2반도체 기판의 복수의 요부가 서로 요철 끼워 맞춤으로써 접합하고 있는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 제l반도체 기판의 복수 철부 및 상기 제2반도체 기판의 복수 요부는 각각 1차원적 또는 2차원적으로 같은 패턴을 갖고 형성되어 있는 것을 특징으로 하는 반도체 장치.
  3. 반도체 장치의 제조방법은, 제1반도체 소자가 형성된 제1반도체 기판의 표면에 상기 제1반도체 소자와 전기적으로 접속하는 복수의 제1전극을 형성하고 상기 제l반도체 기판의 표면에 상기 복수의 제1전극끼리 절연하도록 제1절연층을 형성하는 동시에, 제2반도체 소자가 형성된 제2반도체 기판 표면의 상기 제1반도체 기판의 상기 복수의 제1전극과 대응하는 부위에 상기 제2반도체 소자와 전기적으로 접속하는 복수의 제2전극을 형성하고 상기 제2반도체 기판의 표면에 상기 복수의 제2전극끼리 절연하는 제2절연층을 형성하는 제1공정과, 상기 제1전극 및 제1절연막 표면에 에칭으로 복수의 철부를 형성하는 동시에, 상기 제2전극 및 제2절연막 표면의 상기 복수의 철부와 각각 대응하는 부위에 에칭으로 복수의 요부를 형성하는 제2공정과, 상기 제1반도체 기판과 상기 제2반도체 기판을, 상기 제1반도체 기판의 복수 철부와 상기 제2반도체 기판의 복수의 요부가 서로 요철 끼워맞추도록 접합하는 제3공정을 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  4. 제3항에 있어서, 상기 제2공정은 상기 제1전극 및 제1절연막의 표면에 제l패턴형상을 갖는 제1레지스트 패턴을 형성한 후, 이 제1레지스트 패턴을 마스크로 상기 제1전극 및 제1절연막에 대해 에칭을 행함으로써 상기 복수의 철부를 형성하는 공정과, 상기 제2전극 및 제2절연막 표면에 상기 제1패턴 형상이 반전하여 이루어지는 제2패턴 형상을 갖는 제2레지스트 패턴을 형성한 후, 이 제2레지스트 패턴을 마스크로 상기 제2전극 및 제2절연막에 대해 에칭을 행함으로써 상기 복수의 요부를 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  5. 반도체 장치의 제조방법은, 제1반도체 소자가 형성된 제1반도체 기판 표면에 상기 제1반도체 소자와 전기적으로 접속하는 복수의 제1전극을 형성하고 상기 제1반도체 기판 표면에 상기 복수의 제1전극끼리 절연하는 제1절연층을 형성하는 동시에, 제2반도체 소자가 형성된 제2반도체 기판 표면의 상기 제1반도체 기판 복수의 제1전극과 대응하는 부위에 상기 제2반도체 소자의 전기적으로 접속하는 복수의 제2전극을 형성하고 상기 제2반도체 기판 표면에 상기 복수의 제2전극끼리 절연하는 제2절연층을 형성하는 제1공정과, 상기 제1전극 및 제1절연막의 표면을 평탄화하는 동시에, 상기 제2전극 및 제2절연막의 표면을 평탄화하는 제2공정과, 상기 제1반도체 기판과 상기 제2반도체 기판을 상기 제1반도체 기판 복수의 제1전극과 상기 제2반도체 기판 복수의 제2전극이 서로 대향하도록 위치 맞춤시키는 제3공정과, 위치 맞춤된 상기 제1반도체 기팜 및 제2반도체 기판을 서로 압착함으로써, 상기 제1반도체 기판과 상기 제2반도체 기판을 접합하는 제4공정을 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  6. 제5항에 있어서, 상기 제2공정과 상기 제3공정 사이에, 상기 제1전극 및 제1절연막 표면에 댕그링 본드를 갖는 분자층을 형성하는 공정을 구비하고, 상기 제4공정은 상기 제1전극 및 제1절연막의 표면에 형성된 분자층의 댕그링 본드와, 상기 제2전극 및 제2절연막의 표면층을 화학 흡착시킴으로써, 상기 제1반도체 기판과 상기 제2반도체 기판을 접합하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  7. 제5항에 있어서, 상기 제3공정은 상기 제1반도체 기판과 제2반도체 기판을 액체중에서 위치 맞춤시키는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  8. 제5항에 있어서, 상기 제3공정은 상기 제1반도체 기판 표면에 제1패턴형상을 갖는 제1레지스트 패턴을 형성한 후, 상기 제1반도체 기판에 대해 상기 제1레지스트패턴을 마스크로 에칭을 행함으로써 상기 제1반도체 기판 표면에 위치 맞춤용 요부를 형성하는 공정과, 상기 제2반도체 기판의 표면에 상기 제1패턴 형상이 반전하여 이루어지는 제2패턴 헝상을 갖는 제2레지스트 패턴을 형성하는 공정과, 상기 제1반도체 기판과 상기 제2반도체 기판을 상기 위치 맞춤용 요부와 상기 제2레지스트 패턴이 요철 끼워맞추도록 위치맞춤하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  9. 제5항에 있어서, 상기 제4공정은 위치 맞춤된 상기 제1반도체 기판 및 제2반도체 기판을 진공상태로 유지한 후, 상기 제1반도체 기판의 이면 및 상기 제2반도체 기판의 이면 중 적어도 한쪽을 가스로 압압함으로써, 상기 제1반도체 기판과 상기 제2반도체 기판을 서로 압착하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.
  10. 제5항에 있어서, 상기 제4공정은 위치 맞춤된 상기 제1반도체 기판 및 제2반도체 기판을 가열하면서 서로 압착하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  11. 제5항에 있어서, 상기 제1공정의 상기 제1반도체 기판은 투명성을 갖고 있는 동시에 얼라이먼트 마크가 형성되어 있고, 상기 제4공정에서 상기 제2반도체 기판과 접합된 상기 제1반도체 기판의 이면에 대해 상기 얼라이먼트 마크를 이용하여 에칭을 행함으로써, 상기 제1반도체 기판에 이 제1반도체 기판 안에 상기 제1전극과 전기적으로 접속하도륵 형성되어 있는 도전층에 이르는 개구부를 형성한 후, 상기 개구부에 금속을 매립함으로써, 상기 제1반도체 기판에 외부 전극과 전기적으로 접속되는 인출 전극을 형성하는 제5공정을 더 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  12. 제5항에 있어서, 상기 제1공정은 상기 제1절연층 중에 매립된 제1금속막을 형성하는 동시에, 상기 제2절연층 중의 상기 제1금속막과 대응하는 부위에 매립된 제2금속막을 형성하는 공정을 포함하고, 상기 제2공정은 상기 제1금속막이 형성된 제1절연막 및 상기 제2금속막이 형성된 제2절연막을 평탄화하는 공정을 포함하고, 상기 제4공정은 상기 제1금속막과 상기 제2금속막을 접합하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.
  13. 반도체 장치의 제조방법은, 제1반도체 소자가 형성된 제1반도체 기판 표면에 상기 제1반도체 소자와 전기적으로 접속하는 제1배선을 형성하는 동시에, 제2반도체 소자가 형성된 제2반도체 기판 표면에 상기 제2반도체 소자의 전기적으로 접속하는 제2배선을 형성하는 제1공정과, 상기 제1배선이 형성된 상기 제1반도체 기판 표면에 상기 제1배선과 대응하는 부위에 제1개구부를 갖는 제1층간 절연막을 형성하는 동시에, 상기 제2배선이 형성된 상기 제2반도체 기판 표면에 상기 제2배선과 대응하고 상기 제1개구부와 대웅하는 부위에 제2개구부를 갖는 제2층간절연막을 형성하는 제2공정과, 상기 제1개구부 및 제2개구부 내부에 무전해 도금법으로 금속을 매립함으로써, 상기 제1배선과 상기 제2배선을 접속하는 접속용 전극을 형성하는 제3공정과, 상기 제1반도체 기판과 상기 제2반도체 기판 사이에 절연성 수지를 충전함으로써, 상기 제1반도체 기판과 상기 제2반도체 기판을 서로 접속하는 제4공정을 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  14. 제13항에 있어서, 상기 제1공정은 상기 제1배선이 형성된 상기 제1반도체 기판 표면에 상기 제1배선끼리 절연하는 제1절연막을 상기 제1배선과 같은 면에 형성하는 동시에, 상기 제2배선이 형성된 상기 제2반도체 기판 표면에 상기 제2배선끼리 절연하는 제2절연막을 상기 제2배선과 같은 면에 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  15. 제13항에 있어서, 상기 제2공정의 상기 제1층간 절연막 및 제2층간절연막은 각각 레지스트, 패턴인 것을 특징으로 하는 반도체 장치의 제조방법.
  16. 제13항에 있어서, 상기 제2공정의 상기 제1층간 절연막 및 제2층간 절연막은 각각 실리콘 산화막인 것을 특징으로 하는 반도체 장치의 제조방법.
  17. 제13항에 있어서, 상기 제1공정의 상기 제1반도체 기판은 투명성을 갖고 있는 동시에 얼라이먼트 마크가 형성되어 있고, 상기 제4공정에서 상기 제2반도체 기판과 접합된 상기 제1반도체 기판의 이면에 대해 상기 얼라이먼트 마크를 이용하여 에칭을 행함으로써, 상기 제1반도체 기판에 이 제1반도체 기판 안에 상기 제1배선과 전기적으로 접속하도록 형성되어 있는 도전층에 이르는 개구부를 형성한 후, 상기 개구부에 금속을 매립함으로써, 상기 제1반도체 기판에 외부전극과 전기적으로 접속되는 인출 전극을 형성하는 제5공정을 더 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  18. 반도체 장치의 제조방법은, 제1반도체 소자가 형성된 제1반도체 기판 표면에 상기 제1반도체 소자와 전기적으로 접속되도록 제1배선을 형성하는 동시에, 제2반도체 소자가 형성된 제2반도체 기판 표면에 상기 제2반도체 소자와 전기적으로 접속하는 제2배선을 형성하는 제1공정과, 상기 제1배선이 형성된 상기 제1반도체 기판 표면에, 상기 제1배선과 대응하는 부위에 개구부를 갖는 레지스트 패턴을 형성하는 제2공정과, 상기 레지스트 패턴의 개구부에 금속을 매립하여 접속용 전극을 형성하는 제3공정과, 상기 제1반도체 기판과 상기 제2반도체 기판을 상기 접속용 전극과 상기 제2배선이 접속하도록 위치를 맞춘 후, 상기 제1반도체 기판과 상기 제2반도체 기판을 가열하면서 압축하여 서로 접합하는 제4공정을 구비하고 있는 것을 특징으로 하는 반도체창치의 제조방법.
  19. 제18항에 있어서, 상기 제1공정은 상기 제1배선이 형성된 상기 제1반도체 기판 표면에 상기 제1배선끼리 절연하는 제1절연막을 상기 제1배선과 같은 면에 형성하는 동시에, 상기 제2배선이 형성된 상기 제2반도체기판 표면에 상기 제2배선끼리 절연하는 제2절연막을 상기 제2배선과 같은 면에 형성하는 공정으로 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  20. 제18항에 있어서, 상기 제2공정은 상기 레지스트 패턴을 가열로 열경화시키는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  21. 제18항에 있어서, 상기 제3공정은 무전해 도금법으로 상기 접속용 전극을 선택적으로 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  22. 제18항에 있어서, 상기 제4공정으로 서로 접합된 상기 제1반도체 기판과 상기 제2반도체 기판 사이에 개재하는 상기 레지스트 패턴을 제거한 후, 상기 제1반도체 기판과 상기 제2반도체 기판사이에 스핀온글라스 또는 열경화성 수지를 충전하고, 그후 상기 스핀온글라스 모는 열경화성 수지를 경화시켜 층간 절연막을 형성하는 제5공정을 더 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  23. 제18항에 있어서, 상기 제1공정의 상기 제1반도체 기판은 투명성을 갖고 있는 동시에 얼라이먼트 마크가형성되어 있고, 상기 제4공정에서 상기 제2반도체 기판과 접합된 상기 제1반도체 기판이면에 대해 상기 얼라이먼트 마크를 이용하여 에칭을 행함으로써, 상기 제1반도체 기판에, 이 제1반도체 기판내에 상기 제1배선과 전기적으로 접속하도록 형성되어 있는 도전층에 이르는 개구부를 형성한 후, 상기 개구부에 금속을 매립함으로써, 상기 제1반도체 기판에 외부 전극과 전기적으로 접속되는 인출 전극을 형성하는 제5공정을 더 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  24. 반도체 장치의 제조방법은, 제1반도체 소자가 형성된 제1반도체 기판 표면에 상기 제1반도체 소자와 전기적으로 접속하는 제1전극을 형성하는 동시에, 제2반도체 소자가 형성된 제2반도체 기판 표면에 상기 제2반도체 소자와 전기적으로 접속하는 제2전극을 형성하는 제1공정과, 상기 제1전극이 형성된 상기 제1반도체 기판이면에 상기 제1반도체 기판을 표면쪽에 요모양으로 휘어지게 하는 제1절연막을 형성하는 동시에, 상기 제2전극이 형성된 상기 제2반도체 기판 이면에, 상기 제2반도체 기판을 표면쪽에 요모양으로 휘어지게 하는 제2절연막을 형성하는 제2공정과, 상기 제1반도체 기판과 상기 제2반도체 기판을 상기 제1전극과 상기 제2전극이 대향하도록 위치를 맞춘후, 상기 제1반도체 기판과 상기 제2반도체 기판을 가열하면서 압착하여 서로 접합하는 제3공정을 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  25. 제24항에 있어서, 상기 제2공정의 제1절연막 및 제2절연막은 각각 실리콘 질화막인 것을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950025445A 1994-08-29 1995-08-18 반도체 장치 및 그 제조방법 KR960009074A (ko)

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CN1119345A (zh) 1996-03-27
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DE69519967T2 (de) 2001-05-23
EP0813246A3 (en) 1998-02-04
EP0700088A2 (en) 1996-03-06
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