KR960007678B1 - Parallel distributed sample scramble system - Google Patents

Abstract

A parallel distributed sample scrambling system comprises: a parallel shift register generator having a plurality of shift registers and a plurality of modulo-2 adders, and generating a parallel matrix for a parallel scrambling of an input data matrix; a sampling means for generating a sample from the parallel shift register generator according to a transferring channel slot; a parallel scrambling means for performing a parallel scrambling function by performing a modulo-2 operation with the parallel matrix; and a multiplexing means for multiplexing the scrambled data matrix from the parallel scrambling means.

Description

Parallel Distributed Sample Scrambling System

1 is a diagram showing a format of a serial input data sequence.

2A is a functional block diagram of a scrambler of a DSS system.

2B is a functional block diagram of a descrambler of a DSS system.

3 is a diagram showing an example of conversion from direct scrambling to parallel scrambling, in which FIG. 3A is a diagram showing a serial scrambling portion, and FIG. 3B is a diagram showing a parallel scrambling portion.

4 is a format diagram of a parallel input data sequence.

5 is a timing diagram for sampling time and settling time in a parallel DSS system.

6A is a functional block diagram of a parallel scrambler of a parallel DSS system.

6B is a functional block diagram of a parallel descrambler in a parallel DSS system.

7 illustrates a data structure for ATM 쎌 transmission.

8A is a configuration diagram of a serial shift register generator used for CCITT-DSS.

8B is a configuration diagram of a parallel shift register generator used for CCITT-DSS.

9 illustrates one embodiment of a parallel inverse scrambler for ATM pin scrambling.

* Explanation of symbols for main parts of the drawings

61: parallel shift register generator 62: sample circuit

63: parallel scrambling circuit 64: N: 1 multiplexer (MUX)

65: correction circuit

66: Parallel Shift Register Generator

67: sample circuit 68: comparison circuit

69: parallel descrambling circuit 70: 1: N demultiplexer (DEMUX)

71: shift register generator engine unit 72: parallel sequence generator circuit

73: SRG engine unit 74: parallel heat generation circuit

The present invention relates to a parallel distributed sample scrambling system (PDSS).

Distributed sample scrambling (DSS), which is suitable for scrambling binary data consisting of fixed-size packet streams, scrambles and descrambles binary data in the same way as frame synchronous scrambling (FSS). (descrambling) However, in order to maximize the effect of scrambling, a different scrambler and inverse scrambler synchronization method is used. In other words, the DSS takes a sample of scrambler status and transmits it to the descrambler through a predetermined time slot of every packet, and the descrambler compares the transmitted sample value with the sample value generated by itself. If they differ after comparating, they are motivated by correcting the state of the descrambler, ultimately making the state of the descrambler the same as the state of the scrambler.

Such a DSS system is used for scrambling of an ATM (Asychronous Transfer Mode) cell stream in a cell-based physical layer of a Broadband Integrated Services Digital Network (BISDN). CCITT has recommended it for use. In this case, the transmission rates of ATM cell strings are 155.520 Mbps and 622.080 Mbps.

Since scrambling of the DSS is performed on the transmission signal, the speeds of scrambling and descrambling are equal to the transmission rate. That is, the scrambling and descrambling rates of the ATM cell rows are 155.520 Mbps, 622.080 Mbps, or 2488.320 Mbps. However, the scrambling at such a high speed requires a high speed device, resulting in an increase in manufacturing cost and consumption of power. In addition, since the recent trend is moving toward high-speed transmission of Gbps, scrambling at the transmission speed may be impossible in this case. Therefore, the present invention solves the DSS rate problem by providing PDSS (parallel DSS) at the lower speed than the transmission rate, while having the same effect as the DSS (hereinafter referred to as serial DSS) at the transmission rate. It is in a ship.

Accordingly, it is an object of the present invention to provide a parallel distributed sample scrambling system for fixed-size packet transmission that can scramble binary data at rates lower than the transmission rate.

Another object of the present invention is to provide a parallel distributed sample descrambling system for fixed-size packet transmission capable of descrambling binary data at a rate lower than the transmission rate.

In order to realize the above object, the parallel distributed sample scrambling system according to the present invention includes a plurality of shift registers and a plurality of modulo-2 adders, for generating a parallel sequence for parallel scrambling of an input data sequence. A parallel shift register generator; Sampling means for generating a sample from the parallel shift register generator in accordance with a transport channel slot available for sample transfer; Parallel scrambling means for performing a parallel scrambling function by modulo-2 calculating a parallel sequence from the parallel shift register generator to a parallel input data sequence; And multiplexing means for multiplexing the scrambled data sequences from the parallel scrambling means.

In addition, the parallel distributed sample descrambling system according to the present invention includes demultiplexing means for demultiplexing the multiplexed scrambled data sequence; A parallel shift register generator, comprising a plurality of shift registers and a plurality of modulo-2 adders, for generating parallel sequences for parallel descrambling of scrambled data sequences; Sampling means for generating a sample from the parallel shift register generator in accordance with a transport channel slot available for sample transfer; Comparison means for comparing a sample generated by the sample means with a sample transmitted from the scrambling system; Correction means connected to said comparing means for correcting a sample according to a comparison result from said comparing means; And parallel descrambling means for performing parallel descrambling of the scrambled data sequence by modulo-2 operation of the parallel sequence from the parallel shift register generator to the scrambled data sequence from the demultiplexing means. .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 1, which shows the format of a serial input data sequence, the scrambled serial input data sequence {b _k } is composed of a stream of packets of length F bits. For each packet, the state sample of the scrambler is transmitted through J time slots in a certain position, and the sampling time slot α _{0 for the} time slot for delivering the sample _. , α ₁ ,.. It is called α _J-1 .

The serial DSS at the baud rate can be plotted as shown in Figure 2. Figure 2A is a schematic diagram of a scrambling system or scrambler, showing a serial shift register generator (SRG) 21, a sample. A series SRG, which in turn is a series SRG engine 31 and a serial sequence generating circuit 32, which are composed of a smpling circuit 22 and a scrambling circuit 23. It consists of. FIG. 2B is a schematic diagram of the reverse scrambling system, which includes a series SRG 25 and a sample circuit 26 having the same structure as the scrambling system of FIG. Comparing circuit 28 for comparing the values, and correction circuit 24 and reverse scrambling circuit for correcting the SR state of the series SRG in the reverse scrambling system from the results of the comparison circuit 28. (descrambling circuit) 27 is included.

For the serial SRG engine sections 31 and 33, the number of shift registers in the SRG is denoted by the SRG length L, and an L-vector representing the state of the shift registers in the SRG at time k is represented by the state vector d. _k (in reverse scrambling systems And two state vectors d _k and d _k-1 (or in an inverse scrambling system) Wow The L × L matrix representing the relation of N 2) is expressed as a state transition matrix T. In other words,

Then, the SRG engine units 31 and 33 are uniquely determined by the state transition matrix T.

SRG sequence scrambled {s _k } or SRG sequence scrambled For the series sequence generators 32 and 34 that generate s, the SRG sequence s _k {or } And state vector d _k (or The L-vector representing the relationship with) is expressed as a generating vector h. In other words,

The series sequence generators 32, 34 are then uniquely determined by the generation vector h.

For the sample circuits 22 and 26 which take the state sample values of the SRs in the SRG engine units 31 and 33, the i th sample time slot α ₁ i = 0,1,... , The sample value passed to J-1 in z (reverse scrambling system z), and the sample value (or ) Of the state vector at sample time nF + α ₁ i which the sample value taken d _{nF + α1 (α1 + nF} or d) the sample L- vector showing the relationship between a vector v _1, i = 0,1, ... It is written as J-1. In other words,

The sample circuits 22 and 26 then have a sample time slot α ₁ i = 0,1,... , J-1 and sample vector v ₁ , i = 0,1,.. Is determined solely by J-1.

The scrambling circuit 23 in the scrambling system adds the input data sequence {b _k } to the SRG sequence {s _k } generated by the serial SRG 21 (all additions are modulo-2 operations below). sikimyeo scrambling the data sequence {b _k}, SRG station scrambling sequence circuit 27 in a reverse scrambling system is generated in the serial SRG (25) for the scrambled data sequence {b _k + s _k} { } To restore the original input data sequence {b _k }.

In this case, the inverse scrambled data sequence {b _k + s _k + } Is equal to the input data sequence {b _k }, the SRG sequence of the inverse scrambler { } Must be equal to the SRG sequence of the scrambler {s _k }, which in turn must be in the same state of the SR in the inverse scrambler and the SRG engine section 31,33 of the scrambler. When scrambling and descrambling, the time slot α ₁ i = 0,1,... J-1 and FAW (frame alignment word) or HEC (header error control) indicating the starting point of the packet are excluded from scrambling and descrambling.

The comparison circuit 28 in the inverse scrambling system takes a sample value taken in the scrambling system. And taken in the same way in a reverse scrambling system Compare At this time, if the two values are the same, 0 is sent to the correction circuit, and if they are different, 1 is sent to the correction circuit.

The correction circuit 24 in the inverse scrambling system has two sample values. Wow If they are different, the SR state of the serial SRG 25 in the descrambling system is corrected to make it the same as the SR state of the serial SRG 25 in the scrambling system. For the correction circuit 24, the i th sample value Wow If the times are different from each other, the position of the time slot for correcting the SR state is corrected by a correction time slot β ₁ , i = 0,1,... Denotes the position of the SR to be corrected, and denotes the correction vector c ₁ , i = 0, 1,... It is written as J-1. The correction circuit 24 then performs correction time slots β ₁ , i = 0, 1,... , J-1 and the correction vector c ₁ , i = 0,1,... Is determined solely by J-1. Sample value Wow Are different from each other, considering that the SR state of the serial SRG engine unit 33 of the inverse scrambling system is corrected by the correction vector c ₁ at the correction time nF + β ₁ , equation (1) is modified as follows.

In order to implement a parallel DSS (PDSS) system, an input data sequence {b _k } is first divided into N low-speed parallel sequences. , j = 0,1,… It should be changed to multiplexed signal of N-1. The scrambling portion of FIG. 2A may then be redrawn to FIG. 3A. If serial scrambling performed on the multiplexed numbers is transferred to multiplexing before, a parallel scrambling portion can be obtained as shown in FIG. 3B. Similarly, parallel descrambling can be drawn. The parallel scrambling and parallel descrambling rates are then 1 / N of the rate at which the original serial scrambling is performed (this is the same as the transmission rate), where N is taken from the argument of packet length F. Then, the input data sequence {b _k } of FIG. 1 is a parallel input data sequence as shown in FIG. , j = 0,1,… , N-1 can be obtained. In Figure 4 The time slots, denoted as F / N, are the sample time slots α ₁ , i = 0,1,..., Which send the state sample values of the scrambler in the serial input data sequence {b _k }. Is a parallel sampling time slot corresponding to J-1. That is, the serial sample time slot α ₁ , i = 0,1,... If the quotient of J-1 divided by N and the remainder are q ₁ and r ₁ , this time slot is the r ₁ parallel data sequence. And in that a second parallel q ₁ time slot. Therefore, the parallel sample time slot of FIG. About N If + l is found, this value is the serial sample time slot α ₁ , i = 0, 1,... It corresponds to one of, J-1.

Next, for a serial SRG in a serial scrambling system, N parallel sequences that make the multiplexed parallel scrambled signal equal to the serial scrambled and descrambled signal. (In case of reverse scrambling , J = 0,1,... It should be replaced with a parallel SRG (hereafter PSRG) that generates N-1. This occurs in parallel with the formula (1) in series SRG engine parts of the state transition matrix T and (2) the serial number sequence generation state transition matrix of PSRG satisfying the generation following expression vectors h each circuit in the T _p linking the vector h ₁ , j = 0,1,… To N-1.

Another consideration is the change in the sample circuit. The sampling process is the parallel data input sequence of FIG. , j = 0,1,… In parallel sample time slot at N-1 Depends on However, note that in parallel sampling, multiple samples may be taken at the same time. The parallel sampling time slot shown in FIG. 4 is generally defined in FIG. 5 according to the sampling time taken and the number of samples taken at that time. The same sample timing can be expressed. In Figure 5, , i = 0,1,… , K-1 is the parallel sample time slot, parallel time slot shown in FIG. Are listed in order of magnitude, except for duplicates, and m ₁ is a parallel sample time slot. , i = 0,1,… Is the number of samples taken for K-1. Also, parallel sample time slot of the nth packet. The m ₁ sample values taken at (In reverse scrambler ), l = 0, 1,... , m ₁ -1. here, And m ₁ are not taken arbitrarily but are obtained uniquely from FIG. (or Note that) should be equal to the sample value taken in the sample time slot corresponding to the serial data sequence. Sample value Take a sample vector taking v _1,1 , i = 0,1,. , K-1, L = 0,1,... When expressed as, m ₁ -1, equation (3) is modified as follows.

The sample circuits 22 and 26 directly affect the comparison circuit 28 in the inverse scrambling system. That is, the comparison circuit 28 must be modified so that m ₁ sample values taken in parallel sampling can be compared at the same time. Finally, the correction process in the inverse scrambling system must also change with the sampling process. Parallel sample time slots in parallel sampling ₁ sample at m (or ), 1 = 0,1,... Since m ₁ -1 has been taken, the correction process must simultaneously perform m ₁ corrections in the correction time slot β ₁ (see FIG. 5). Sample value Wow Are different from each other, a correction vector representing a correction position of the SR in the inverse scrambler PSRG is obtained by c _1,1 , i = 0,1,. , K-1, 1 = 0,1,... When expressed as, m ₁ -1, equation (4) is modified as follows.

Reflecting all of the requirements mentioned so far, the serial DSS system of FIG. 2 can be drawn as a variant of the PDSS system as shown in FIG. FIG. 6A shows a parallel scrambler of a parallel DSS system, and FIG. 6B shows a parallel descrambler. In these figures, the 1: N demultiplexer that is in the scrambler portion and the N: 1 multiplexer that is in the descrambler portion are omitted. As shown in FIG. 6A, the parallel scrambler includes a parallel shift register generator (PSRG) 61 including a plurality of shift registers (SRGs) and a plurality of modulo-2 adders, a sample circuit 62, and a parallel circuit. The scrambling circuit 63 and the N: 1 multiplexer 64 are included. The PSRG 61 includes a shift register generator engine section 71 for generating a state transition matrix for the shift register and a parallel sequence generating circuit 72 for generating parallel sequences for scrambled parallel input data sequences. have. The sample circuit 62 generates sample values from the PSRG 61 according to the transmission channel slots available for sample delivery. The parallel scrambling circuit 63 performs a parallel scrambling function by adding a parallel sequence from the PSRG 61 to an input data sequence. The N: 1 multiplexer (MUX) 64 multiplexes the scrambled data sequence from the parallel scrambling circuit 63. 6B, the parallel descrambler includes a 1: N demultiplexer (DEMUX) 70, a parallel shift register generator 66, a sample circuit 67, a comparison circuit 68, The correction circuit 65 and the parallel descrambling circuit 69 are included. The parallel shift register generator (PSRG) 66 is composed of a plurality of shift registers and a plurality of modulo-2 adders, and the scrambled data with the SRG engine unit 73 for generating a state transition matrix for the shift register. A parallel sequence generating circuit 74 for generating parallel sequence for reverse scrambling of the sequence is included. The DUMUX 70 performs a function of demultiplexing the multiplexed scrambled data sequence, and the sample circuit 67 generates sample values from the PSRG 661 according to a transmission channel slot that can be used for sample transfer. The comparison circuit 68 is connected to the sample circuit 67 and performs a function of comparing the sample value generated by the sample circuit 67 with the sample value transmitted from the scrambler side. The correction circuit 65 is connected to the comparison circuit 68, and performs a function of correcting a sample value according to a comparison result from the comparison circuit 68. The output of the correction circuit 65 is configured to be applied to the PSRG 66. The parallel descrambling circuit 69 performs descrambling of the scrambled data sequence by adding the parallel sequence from the PSRG 66 to the scrambled data sequence from the DEMUX 70.

In order to implement the PDSS system of FIG. 6, the state transition matrix T _p of the PSRG and the parallel sequence generating vectors h ₁ , j = 0, 1,... , N-1: sample time slot of sample circuit , i = 0,1,… , K-1 and sample vector v _1,1 , i = 0,1,... , K-1, 1 = 0,1,... , m ₁ -1: and the correction time slot of the correction circuit , i = 0,1,… , K-1 and the correction vector c _1,1 , i = 0,1,... , K-1, 1 = 0,1,... , m ₁ -1

The state transition matrix T _p of the PSRG and the parallel sequence generating vectors h ₁ , j = 0,1,... N-1 can be obtained from existing papers (see DWChoi's Parallel scrambling teniques for digital multiplexer, AT & T tech. J., September / October 1986, pages 123-136). , i = 0,1,… , K-1 and v _1,1 , i = 0,1,... , K-1, 1 = 0,1,... , m ₁ -1 is uniquely determined from the relationship between the serial data sequence of FIG. 1 and the parallel data sequence of FIG. Therefore, the correction time slot of the correction circuit for the implementation of the PDSS system , i = 0,1,… , K-1 and the correction vector c _1,1 , i = 0,1,... , K-1, 1 = 0,1,... Finding m ₁ -1 is a key problem.

Correction circuit And c _1,1 to define a vector representing the difference between the state vector d _k of the scrambler and the state vector δ _k of the inverse scrambler as a state distance vector δ _k . In other words,

Then, when δ _k = 0, the scrambler and the inverse scrambler are synchronized. For the state vector d _k of the scrambler from equation (5)

For the state vector d _k of the inverse scrambler, equation (5) is corrected only when the correction occurs, that is, the correction time nF + Note that only changes to Eq. (8)

Get The above two expressions are represented by equation (7) and When combined using, the following equation can be obtained.

In other words,

Where A _* is

Becomes Therefore, the state difference vector at the end of correction in the nth packet And the relationship between the initial state difference vector δ ₀

Becomes To synchronize the scrambler SRG with the inverse scrambler SRG, we need to make the corrected state difference vector to zero regardless of the initial state difference vector δ _0. Only possible when is 0 matrix.

When the SRG length of the PSRG is L, at least L sample values may be transmitted from the scrambler to estimate the state of the L SRs. However, since J sample values are transmitted per packet, nJ sample values are transmitted after n packets. Therefore, if W is the smallest integer whose WJ is greater than L, then the descrambler can be synchronized at least after W packets. We will see how to synchronize after W packet for efficient synchronization. This is given as mentioned above And v _1,1 Makes 0 And c _1,1 .

Standard time slots associated with the sample process And sample vector v _1,1 can be synchronized after W packets only if the conditions shown by the following theorem are met (actually, if only a W packet can be synchronized for a serial DSS system, And v _1,1 can be shown to automatically satisfy the condition of Theorem 1).

Theorem 1 (Sample Condition): Define the discriminant matrix Δ as follows.

Then, only if the rank of the discrimination matrix Δ (which is the WJ × L matrix) is equal to the length L of the SRG. Makes 0 And c _1,1 are present.

Next, the sample time slot If c _1,1 and sample vector v _1,1 satisfy 1, then theorem 2 is the correction time slot associated with the correction process. And how to catch the correction vector c _1,1 can be synchronized after W packet.

Theorem 2 (correction condition): L × L nonsingular matrix excluding some rows from the first J matrices from the discrimination matrix Δ of equation (16) (This is always possible if the rank of Δ is L). The correction time slot Can be arbitrarily selected and the selected correction time slot If we take the correction vector c _1,1 as Becomes zero.

Where e ₁ , i = 0,1,... , L-1 is a unit vector of only the i th element, and the remainder 0, and I _1,1 this Is the line number that appears in, and u _{1l, 1} is any value of 0 or 1.

As a special example, let's implement a PDSS system for a DSS system used in CCITT. CCITT adopts DSS (hereinafter referred to as CCITT-DSS) as the scrambling method of ATM chips, which is serial input data consisting of 53 bytes (424 bits; F = 424) of ATM rows, as shown in FIG. For scrambling a sequence, an SRG as shown in FIG. 8A is used. As shown in FIG. 7, two (J = 2) scrambler sample values s _t-211 and s _t for each ATM 로 are passed to the inverse scrambler through two adjacent sample time slots α ₀ = 32 and α ₁ = 33, respectively. Is sent. The transmission rate of ATM 쎌 is 155.520 Mpbs, 622.080 Mpbs or 2488.320 Mpbs.

To implement CCITT-DSS in parallel (hereafter CCITT-PDSS), N must be selected first. Choose N for 8 for byte-by-byte parallelism. then, Is 53 (= F / N), and the scrambling rates drop to 19.44 Mpbs (= 155.520 / 8), 77.76 Mpbs (= 622.080 / 8) and 311.04 Mpbs (= 2488.320 / 8), respectively. First eight parallel sequences , j = 0,1,… By obtaining a PSRG that generates, 7, a PSRG as shown in FIG. 8B can be obtained. The length L of the PSRG is 31, and the state transition matrix T _p and the generation vector h ₁ , j = 0,1,... , 7 is as follows.

Next, the sample time slot determines the sample circuit. _{Find the} sample vector v _1,1 . Eight parallel sequences , j = 0,1,… Note that the multiplexed sequence of, 7 must be equal to the serial SRG sequence {s _k }. The sample values s _t-211 and s _t of the serial CCITT-DSS are the sample values of the PSRG, respectively. Wow It can be seen that they are transmitted through the same time slot of the 0 th and 1 th parallel input data sequences (K = 1, m ₁ = 2). That is, the parallel sample time slot in this case. = 4, and the sample vectors v _0,0 and v _0,1 are as follows.

Finally, the correction time slot to determine the correction circuit _Find and the correction vector c _1,1 . In this case, since the length L of SRG is 31 and J is 2, W is 16. Substituting these and equations (20a) and (20b) into equation (16) confirms that the rank of the discriminant matrix Δ (32 x 31 matrix) is 31, except for the 0th row from the discriminant matrix Δ, × 31 Reversible Matrix Can be obtained. This reversible matrix With correction time slot By substituting = 5 (which means that correction takes place immediately after the standard is taken) into equation (17), the following correction vector is obtained.

Sample vector in equation (20), correction vector in equation (21), and sample time slot = 4 and the correct time slot By using = 5, an inverse scrambler of the CCITT-DSS system as shown in FIG. 9 can be obtained. In FIG. 9, the boxes shown as dotted lines represent the sample values of the PSRG. Is a circuit for implementing the sample vector v _0,0 that generates The display shows a modulo-2 adder, and reference numerals 91 and 92 denote AND gates which form part of the correction circuit 65. Except for the correction circuit and the comparison circuit in FIG. 9, the inverse scrambler is scrambled in the CCITT-PDSS system.

Claims (8)

A parallel distributed sample scrambling system for transmitting fixed size packets, comprising a plurality of shift registers and a plurality of modulo-2 adders, and a parallel shift for generating parallel sequences for parallel scrambling of the input data sequence. A register generator; Sampling means for generating a sample from the parallel shift register generator in accordance with a transport channel slot available for sample transfer; Parallel scrambling means for performing a parallel scrambling function by modulo-2 calculating a parallel sequence from the parallel shift register generator to a parallel input data sequence; And multiplexing means for multiplexing the scrambled data sequence from said parallel scrambling means. 2. The apparatus of claim 1, wherein the parallel shift register generator comprises: a shift register generator engine section for generating state transition matrices for the plurality of shift registers; A parallel distributed sample scrambling system comprising parallel sequence generating means for scrambling an input data sequence. 3. The parallel distributed sample scrambling system of claim 2, wherein the parallel scrambling means comprises a plurality of modulo-2 adders. CLAIMS 1. A parallel distributed sample descrambling system for transmitting fixed size packets, comprising: demultiplexing means for demultiplexing multiplexed scrambled data sequences; A parallel shift register generator, comprising a plurality of shift registers and a plurality of modulo-2 adders, for generating parallel sequences for parallel descrambling of scrambled data sequences; Sampling means for generating a sample from the parallel shift register generator according to a transport channel slot that may be used for sample transfer; Comparison means connected to said sample means for comparing a sample generated by said sample means with a sample transmitted from a scrambling system; Correction means connected to said comparison means for correcting a sample according to a comparison result from said comparison means; And parallel descrambling means for performing parallel descrambling of the scrambled data sequence by modulo-2 operation of the parallel sequence from the parallel shift register generator to the scrambled data sequence from the demultiplexing means. Parallel distributed specimen scrambling system. 5. The apparatus of claim 4, wherein the parallel shift register generator comprises: a shift register generator engine section for generating state transition matrices for the plurality of shift registers; A parallel distributed sample scrambling system comprising parallel sequence generating means for descrambling a scrambled data sequence. 6. The parallel distributed sample scrambling system of claim 5, wherein the comparing means comprises a plurality of modulo-2 adders. 7. The apparatus according to claim 6, wherein the correction means comprises a plurality of AND products each having an input as long as a sample pulse is applied and an input connected to the output of one of the plurality of modulo-2 adders in the comparison means. Parallel distributed sample scrambling system, characterized in that. 8. The parallel distributed sample scrambling system of claim 7, wherein the parallel descrambling means comprises a plurality of modulo-2 adders.