KR950022355A - Phase Change Detection Circuit of Input Signal Using Digital Signal Processing Method - Google Patents

Phase Change Detection Circuit of Input Signal Using Digital Signal Processing Method Download PDF

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Publication number
KR950022355A
KR950022355A KR1019930028941A KR930028941A KR950022355A KR 950022355 A KR950022355 A KR 950022355A KR 1019930028941 A KR1019930028941 A KR 1019930028941A KR 930028941 A KR930028941 A KR 930028941A KR 950022355 A KR950022355 A KR 950022355A
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KR
South Korea
Prior art keywords
output
prom
address
phase change
data
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KR1019930028941A
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Korean (ko)
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KR960009537B1 (en
Inventor
조진호
표철식
최재익
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양승택
재단법인 한국전자통신연구소
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Priority to KR93028941A priority Critical patent/KR960009537B1/en
Publication of KR950022355A publication Critical patent/KR950022355A/en
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Publication of KR960009537B1 publication Critical patent/KR960009537B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

본 발명은 위성통신 지구국 시스템의 수신부에서 위성의 운동으로 인하여 발생되는 도플러 주파수오차를 보상하기 위하여 복조된 신호의 위상변화를 디지탈 신호처리 방법으로 검출하는 디지탈 신호처리 방식을 이용한 입력신호의 위상변화 검출회로에 관한 것으로, 입력신호의 위상변화를 7.2도의 오차로 검출이 가능하며 특히 입력신호의 비트 중간에 존재하는 지터잡음과 랜덤한 잡음을 제거하고 순수히 도플러 효과로 인한 위상의 변화 검출이 가능하며, 또한 프로세서로 부터 계수 PROM의 시작 어드레스를 지정받아 코릴레이션을 취함으로써 전체 25샘플데이타에 대해서 코릴레이션 취하지 않고도 3개의 샘플 데이타만이 코릴레이션으로 같은 기능을 유지함으로써 코릴레이션 시간을 크게 감소 시킬수 있는 효과가 있다.The present invention detects a phase change of an input signal using a digital signal processing method for detecting a phase change of a demodulated signal by a digital signal processing method in order to compensate for a Doppler frequency error caused by the motion of a satellite at a receiver of a satellite communication earth station system. The circuit can detect the phase change of the input signal with an error of 7.2 degrees. In particular, the jitter noise and random noise existing in the middle of the bit of the input signal can be removed, and the phase change due to the pure Doppler effect can be detected. Also, by correlating with the start address of the coefficient PROM from the processor, only three sample data can be correlated and the correlation time can be greatly reduced without having to correlate the entire 25 sample data. There is.

Description

디지털 신호처리 방식을 이용한 입력신호의 위상변화 검출회로Phase change detection circuit of input signal using digital signal processing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 회로구성 블록도.1 is a circuit block diagram of the present invention.

Claims (1)

입력되는 신호 데이터(복원신호)를 샘플링하고 샘플된 펄스를 디지털 코드로 변환시키는 아날로그/디지털 변환수단(ADC)(1); 상기 아날로그/디지털 변환수단(ADC)(1)을 통해 입력되는 신호를 받아서 순차적으로 8비트 데이터를 저장함과 동시에 다른 저장되어 있던 바로전 신호의 데이터 전송을 동시에 수행하는 고속 RAM으로 2중 구조로 되어 있는 RAM(2)과; 상기 RAM(2)출력 데이터와 디지털 코드화된 데이터를 입력받아 코릴레이션하여 누적시키는 MAC(M ultiple Accumulator)(4); 위상오차가 전혀없는 133 1/3Kb/s의 아날로그신호를 25샘플하고 8비트 디지털 코드화한 데이터를 상기 MAC(4)으로 전송하는 계수 PROM(3); 상기 ROM(4)으로부터 카운터 설정횟수만큼 출력이 증가할때 한번씩 출력하는 제1출력래치(5); 상기 계수 PROM(3)의 시작점 어드레스를 프로세서에서부터 받아서 상기 계수 PROM(3)의 어드레스 시작 번지를 지정하는 입력래치(6)와; 어드레스를 설정값까지 증가시켜 계수하는 카운터(7); 상기 계수 PROM(3)의 시작번지와 상기 카운터(7)의 출력을 더하여 계수 PROM(3)의 시작번지부터 어드레스를 증가시키는 제1가산기(8); 상기 제1출력래치(5)의 출력을 Incosh 함수값으로 변환하는 PROM으로 제1출력래치(5)의 출력을 어드레스로 입력하고 그 어드레스버너지에 해당하는 Incosh 값을 출력하는 Incosh PROM(9); 상기 Incosh PROM(9)의 출력 데이터와 누적 데이터를 가산하는 제2가산기(10)와 상기 제2가산기(10)로부터의 가산 출력을 저장했다가 다시 상기 제2가산기(10)로 출력하는 누적 RAM(11)을 구비하는 프레임 누적기(12); 및 상기 프레임 누적기(12)로부터의 출력을 일시저장하였다가 출력하는 제2출력래치(13); 를 구비하는 것을 특징으로 하는 디지털 신호처리 방식을 이용한 입력신호의 위상변화 검출회로.An analog / digital converting means (ADC) 1 for sampling the input signal data (restoration signal) and converting the sampled pulses into digital codes; Receives the signal input through the analog-to-digital conversion means (ADC) (1) is a high-speed RAM that stores 8-bit data sequentially and at the same time performs data transmission of the other immediately stored signal at the same time has a double structure RAM 2; A MAC (Multiple Accumulator) 4 which receives the RAM 2 output data and the digitally coded data and correlates and accumulates them; A coefficient PROM (3) which samples 25 analog signals of 133 1/3 Kb / s with no phase error and transmits 8-bit digitally coded data to the MAC (4); A first output latch (5) outputting the output once from the ROM (4) as the output increases by the counter setting frequency; An input latch (6) which receives a start point address of the coefficient PROM (3) from a processor and designates an address start address of the coefficient PROM (3); A counter 7 for counting by incrementing the address to a set value; A first adder (8) for adding the start address of the counting PROM (3) and the output of the counter (7) to increase the address from the start address of the counting PROM (3); An Incosh PROM (9) for inputting an output of the first output latch (5) as an address and outputting an Incosh value corresponding to the address burner to a PROM for converting the output of the first output latch (5) to an Incosh function value; A cumulative RAM for storing the second adder 10 for adding the output data and the cumulative data of the Incosh PROM 9 and the add output from the second adder 10, and for outputting the accumulated output to the second adder 10 again. A frame accumulator 12 having a frame 11; And a second output latch 13 for temporarily storing and outputting the output from the frame accumulator 12. Phase change detection circuit of the input signal using a digital signal processing method characterized in that it comprises a. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93028941A 1993-12-21 1993-12-21 Circuit for detecting phase transformation KR960009537B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93028941A KR960009537B1 (en) 1993-12-21 1993-12-21 Circuit for detecting phase transformation

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Application Number Priority Date Filing Date Title
KR93028941A KR960009537B1 (en) 1993-12-21 1993-12-21 Circuit for detecting phase transformation

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KR950022355A true KR950022355A (en) 1995-07-28
KR960009537B1 KR960009537B1 (en) 1996-07-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100640432B1 (en) * 2002-10-09 2006-10-30 삼성전자주식회사 Method of phase demodulation for phase error suppressing of communication signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100640432B1 (en) * 2002-10-09 2006-10-30 삼성전자주식회사 Method of phase demodulation for phase error suppressing of communication signal

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KR960009537B1 (en) 1996-07-20

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