KR940012170A - Finite field inverse calculation method and apparatus - Google Patents

Finite field inverse calculation method and apparatus Download PDF

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KR940012170A
KR940012170A KR1019920022937A KR920022937A KR940012170A KR 940012170 A KR940012170 A KR 940012170A KR 1019920022937 A KR1019920022937 A KR 1019920022937A KR 920022937 A KR920022937 A KR 920022937A KR 940012170 A KR940012170 A KR 940012170A
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value
multiplier
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finite field
inverse
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KR1019920022937A
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KR950010452B1 (en
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이종환
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윤종용
삼성전자 주식회사
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Priority to US08/125,269 priority patent/US5448510A/en
Priority to GB9320086A priority patent/GB2272983B/en
Priority to DE4333382A priority patent/DE4333382A1/en
Priority to FR9311657A priority patent/FR2698703B1/en
Priority to JP5253294A priority patent/JPH06230991A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G06F7/726—Inversion; Reciprocal calculation; Division of elements of a finite field
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations

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  • Error Detection And Correction (AREA)
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Abstract

본 발명은 유한체상에서 역수를 굿하는 방법 및 장치에 관한 것으로, 방법은 유한체GF(2n)내에서 비트로 표현된 임의의 수 (ak)를 이용하여 비트로 표현된 그의 역수(a-k)를 구하는 방법에 있어서, 상기 유한체GF(2n)의 원시원을 a라할 때, 상기 ak가 a0인 경우에 a0를 a-k로서 구하는 과정과;ak≠a0인 경우에는 A 및 A-1에 a0를 대입한 후 상기 A 값이 상기 ak갑과 동일한 값을 가질때까지 상기 A 및 A-1에 상기 유한체의 원시원 a및 a-1을 각각 승산하는 과정과; 상기 A-1의 값을 a-1로서 구하는 과정을 포함하여 구성되며 이를 구현하기 위한 장치는 a곱셈기와 a-1곱셈기와 비교기 및 랫치수단을 포함하여 구성되는 것으로, 특업테이블방식이 아닌 하드웨어로 구현할 수 있는 유한체상의 역수를 구하는 알고리즘을 새로이 제시함과 동시에 이를 수행할 수 있는 장치를 제공하며 종래의 유한체상의 역수를 구하는 장치보다 그 크기가 줄어드는 효과가 있다.The present invention relates to a method and apparatus for a good inverse on the finite field, the method finite field GF (2 n) can be any of the bits in the representation of its reciprocal expression bits using a (a k) (a -k In the method for obtaining), when the source of the finite field GF (2 n ) is a, obtaining a 0 as a -k when a k is a 0 ; and a k ≠ a 0 . It is then substituted for a 0 on the a and a -1 a process of the value is multiplied by the a k handcuffs up when you have a value equal to the primitive root of a finite field for the a and a -1 and a -1 a, respectively and ; And comprising: a process of obtaining the value of the A -1 -1 as a device for implementing this, as a multiplier and a -1 multiplier and being configured to include a comparator, and latch means, the hardware than the method table teukeop While presenting a new algorithm for calculating the inverse of the finite field that can be implemented, the present invention provides a device capable of performing the same, and its size is reduced compared to the device for obtaining the inverse of the conventional finite field.

Description

유한체상의 역수 산출방법 및 장치Finite field inverse calculation method and apparatus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 일실시예에 따른 유한체상의 역수 산출방법의 순서도이고,2 is a flow chart of a method for calculating the inverse of the finite body according to an embodiment of the present invention,

제3도는 본 발명의 일실시예에 따른 유한체상의 역수 산출장치의 블럭도이고,3 is a block diagram of a finite body inverse calculating apparatus according to an embodiment of the present invention,

제4도는 a곱셈기 및 a-1곱셈기의 일실시예에 따른 블럭도이다.4 is a block diagram according to one embodiment of a multiplier and a- 1 multiplier.

Claims (5)

유한체GF(2n)내에서 비트로 표현된 임의의 수 (ak)를 이용하여 비트로 표현된 그의 역수 (a-k)를 구하는 방법에 있어서, 상기 유한체GF(2n) 의 원시원을 a라 할 때, 상기 ak가 a0인 경우에 a0를 a-k로서 구하는 과정과; ak≠a0인 경우에는 A 및 A-1에 a0를 대입한 후 상기 A값이 상기 ak값과 동일한 값을 가질때까지 상기 A 및 A-1에 상기 유한체의 원시원 a 및 a-1을 각각 승산하는 과정과; 상기 A-1의 값을 ak로서 구하는 과정을 구비하는 것을 특징으로 하는 유한체상의 역수 산출방법.Finite Field GF (2nAny number expressed in bits within)kIts inverse expressed as a bit using-kIn the method for obtaining), the finite body GF (2nWhen the source of a) is a, the akHave a0If is a0A-kObtaining as; ak≠ a0If A and A-OneOn a0After A is substituted, the A value is the akA and A until the same value as the value-OneSources of the finite bodies a and a-OneMultiplying each; A above-OneValue of akA process for calculating the reciprocal of the finite body, characterized in that it comprises a process of obtaining as. 제1항에 있어서, 상기 A 및 A-1에 상기 유한체의 원시원 a 및 a-1을 각각 승산하는 과정은 상기 A값이 상기 ak값과 동일한 값을 가지거나 또는 상기 A-1의 값이 상기 ak값과 동일한 값을 가질때까지 수행되며; A값이 ak값과 동일한 경우에는 A-1의 값을 a-k로서 구하고, A-1의 값이 ak값과 동일한경우에는 A의 값을 a-k로서 구하게 되는것을 특징으로 하는 유한테상의 역수 산출방법.2. The method of claim 1, wherein A and A -1 primitive root a, and the process of multiplying each of the A a -1 value of the finite field has the same value and the k value for a, or of the A -1 Is performed until the value has the same value as the a k value; If the A value equal to a k value of finding a value of A -1 as a -k, if the value of A -1 is the same as a k value, characterized in that the oil seek the value of A as a -k How to calculate the inverse of an award. 유한체GF(2n)내에서 비트로 표현된 임의의 수 (ak)를 이용하여 비트로 표현된 그의 역수 (a-k)를 구하는 장치에 있어서, 상기 유한체GF(2n) 의 원시원을 a라 할 때, 초기값으로 a0를 로딩하고 클럭이 인가될 때마다 그 자신이 가지고 있는 값에 a를 곱셈하는 a곱셈기와; 초기값으로 a0를 로딩하고 클럭이 인가될 때마다 그 자신이 가지고 있는 값에 a-1를 곱셈하는 a-1곱셈기와; 상기 ak와 상기 a 곱셈기의 출력을 비교하여 동일한 경우에 인에이블되는 신호를 출력하는 비교기; 및 상기 비교기의 출력이 인에이블되는 경우에 상기 a-1곱셈기의 출력을 랫치하는 랫치수단을 구비하여 랫치수단의 울력이 a-k가 되는것을 특징으로 하는 유한체상의 역수 산출장치.In the finite field GF (2 n) to obtain the number of random bits in the representation (a k) its inverse (a -k) bits can be described using a device, a primitive root of a finite field GF (2 n) a multiplier that loads a 0 as an initial value and multiplies a by its own value each time a clock is applied; Each time the initial value loaded to a 0 and applies this clock a -1 multiplier for multiplying a -1 to the value that he has with; A comparator for comparing the a k and the output of the a multiplier and outputting a signal that is enabled in the same case; And latching means for latching the output of the a -1 multiplier when the output of the comparator is enabled, so that the force of the latching means becomes a -k . 유한체GF(2n)내에서 비트로 표현된 임의의 수 (ak)를 이용하여 비트로 표현된 그의 역수 (a-k)를 구하는 장치에 있어서, 상기 유한체 GF(2n)의 원시원을 a라 할 때, 초기값으로 a0를 로딩하고 클럭이 인가될 때마다 그 자신이 가지고 있는 값에 a를 곱셈하는 a곱셈기와; 초기값으로 a0를 로딩하고 클럭이 인가될 때마다 그 자신이 가지고 있는 값에 a-1를 곱셈하는 a-1곱셈기와; 상기 ak와 상기 a 곱셈기의 출력을 비교하여 동일한 경우에 인에이블되는 신호를 출력하는 제1비교기와; 상기 ak와 상기 a-1곱셈기의 출력을 비교여 동일한 경우에 인에이블되는 신호를 출력하는 제2비교기; 및 상기 제2비교기의 출력이 인에이블인 경우에는 상기 a 곱셈기의 출력을 선택하고 상기 제1비교기의 출력이 인에이블인 경우에는 상기 a-1곱셈기의 출력을 선택하게 되는 선택기를 구비하여 선택기의 출력이 임의의 수 (ak)의 역수 (a-k)가 되는 것을 특징으로 하는 유한체상의 역수 산출장치.In the finite field GF (2 n) to obtain the number of random bits in the representation (a k) its inverse (a -k) bits can be described using a device, a primitive root of a finite field GF (2 n) a multiplier that loads a 0 as an initial value and multiplies a by its own value each time a clock is applied; Each time the initial value loaded to a 0 and applies this clock a -1 multiplier for multiplying a -1 to the value that he has with; A first comparator for comparing the a k and the outputs of the a multiplier and outputting a signal that is enabled in the same case; A second comparator comparing the outputs of the a k and the a- 1 multiplier and outputting a signal that is enabled when the same is the same; And a selector for selecting the output of the a multiplier when the output of the second comparator is enabled and selecting an output of the a- 1 multiplier when the output of the first comparator is enabled. output any number of (a k) the inverse (a -k) is the inverse calculation unit on the finite field characterized in that a. 오류정정부호의 복호시, 유한체GF(2n)내에서 연산이 수행되며, 오류위치다항식의 계수를 구하기 위하여 n비트로 구성되는 오증들(S)을 이용하여 그의 역수(S-1)를 산출하기 위한 장치에 있어서, 상기 유한테 GF(2n)의 원시원을 a라 할 때, 초기값으로 a0(100…0)를 로딩하고 클럭이 인가될 때마다 그 자신이 가지고 있는 값에 a를 곱셈하는 a 곱셈기와; 초기값으로 a0(100…0)를 로딩하고 클럭이 인가될 때마다 그 자신이 가지고 있는 값에 a-1곱셈하는 a-1곱셈기와; 상기 오중 S와 상기 a곱셈기의 출력을 비교하여 동일한 경우에 인에이블되는 신호를 출력하는 비교기; 및 상기 비교기의 출력이 인에이블되는 경우에 상기 a-1곱셈기의 출력을 랫치하는 랫치수단을 구비하여 랫치수단의 출력이 오중의 역수 S-1이 되는 것을 특징으로 하는 유한체상의 오증역수 산출장치.When decoding an error correcting code, an operation is performed in the finite field GF (2 n ), and its inverse (S -1 ) is calculated using the negatives S composed of n bits to obtain the coefficient of the error position polynomial. In the apparatus for doing this, when the source of the finite element GF (2 n ) is a, it loads a 0 (100... 0) as an initial value and the value a has to its own value whenever a clock is applied. A multiplier for multiplying; An a- 1 multiplier that loads a 0 (100... 0) as an initial value and multiplies its own value by a -1 each time a clock is applied; A comparator for comparing the output of the error S and the output of the a multiplier and outputting a signal that is enabled in the same case; And a latch means for latching the output of the a -1 multiplier when the output of the comparator is enabled, so that the output of the latch means is the reciprocal of the reciprocal S -1. Device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920022937A 1992-11-30 1992-11-30 Method and apparatus for generating inverse data on a finite field KR950010452B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019920022937A KR950010452B1 (en) 1992-11-30 1992-11-30 Method and apparatus for generating inverse data on a finite field
US08/125,269 US5448510A (en) 1992-11-30 1993-09-23 Method and apparatus for producing the reciprocal of an arbitrary element in a finite field
GB9320086A GB2272983B (en) 1992-11-30 1993-09-29 Method and apparatus for producing the reciprocal of an arbitrary element in a finite field
DE4333382A DE4333382A1 (en) 1992-11-30 1993-09-30 Method and apparatus for forming the reciprocal of any element in a finite field
FR9311657A FR2698703B1 (en) 1992-11-30 1993-09-30 Method and device for producing the inverse of an arbitrary element in a finite field.
JP5253294A JPH06230991A (en) 1992-11-30 1993-10-08 Method and apparatus for computation of inverse number of arbitrary element in finite field

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KR1019920022937A KR950010452B1 (en) 1992-11-30 1992-11-30 Method and apparatus for generating inverse data on a finite field

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KR940012170A true KR940012170A (en) 1994-06-22
KR950010452B1 KR950010452B1 (en) 1995-09-18

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GB (1) GB2272983B (en)

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KR100653675B1 (en) * 2005-12-06 2006-12-05 엠텍비젼 주식회사 Apparatus and method for calculating reciprocal number

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US5974582A (en) * 1997-10-14 1999-10-26 Lsi Logic Corporation High-speed chien search logic
US6052704A (en) * 1998-01-12 2000-04-18 National Science Council Exponentiation circuit and inverter based on power-sum circuit for finite field GF(2m)
JP3659320B2 (en) * 2000-06-21 2005-06-15 インターナショナル・ビジネス・マシーンズ・コーポレーション Multiplication module, multiplication inverse element operation circuit, multiplication inverse element operation control system, device using the multiplication inverse element operation, encryption device, error correction decoder
JP4935367B2 (en) * 2007-01-19 2012-05-23 富士通株式会社 RAID device and Galois field product operation processing method
US10020932B2 (en) * 2015-11-13 2018-07-10 Nxp B.V. Split-and-merge approach to protect against DFA attacks

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EP0096163B1 (en) * 1982-06-15 1988-06-01 Kabushiki Kaisha Toshiba Apparatus for dividing the elements of a galois field
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KR950010452B1 (en) 1995-09-18
JPH06230991A (en) 1994-08-19
DE4333382A1 (en) 1994-06-01
FR2698703A1 (en) 1994-06-03
US5448510A (en) 1995-09-05
GB2272983A (en) 1994-06-01
FR2698703B1 (en) 1995-03-31
GB9320086D0 (en) 1993-11-17

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