KR20230045505A - Semiconductor integrated circuit, method for testing semiconductor integrated circuit, and semiconductor system - Google Patents

Abstract

A semiconductor integrated circuit, a method for testing a semiconductor integrated circuit, and a semiconductor system are disclosed. The semiconductor integrated circuit according to the technical idea of the present disclosure includes: a security key injection unit which generates a plurality of delay input signals differently delayed from a test scan input signal based on the test scan input signal, and generates an input key signal by capturing the plurality of delay input signals in response to a test clock signal; a key comparator which verifies the input key using a reference key; a chip which outputs a scan output signal; a scan output remapper which obfuscates the scan output signal according to the verification results; and a security scan controller.

Description

Semiconductor integrated circuit, method for testing semiconductor integrated circuit, and semiconductor system

The technical idea of the present disclosure relates to an electronic device, and more particularly, to a semiconductor integrated circuit, a method for testing a semiconductor integrated circuit, and a semiconductor system.

Design-for-Test (DFT) techniques provide fundamental support for the testing of complex integrated circuits (ICs) and systems-on-chips (SoCs), as they allow a simple and effective means of accessing, as well as reading and altering, device internal components. am. This access is provided through scan chains. Undesirably, however, such access beneficial during testing can lead to a number of security problems after the product is sold/deployed. That is, this same access can be used for malicious reasons to change the product, manipulate the product, disassemble and imitate the product, or perform other malicious activities.

A typical solution for preventing the utilization of the scan chain of the system after the test is to check whether an input key received as a test scan input signal from the outside corresponds to a preset authentication key. In general, in order to capture a test scan input signal from the outside in response to a clock signal, series-connected flip-flops are introduced. However, when an authentication key input is received using flip-flops connected in series, flip-flops must be additionally connected in series in order to increase security, such as complicating a preset authentication key. This method not only increases the size of the chip, but also has a problem in that it does not significantly increase security.

The technical spirit of the present disclosure provides a semiconductor integrated circuit, a method for testing the semiconductor integrated circuit, and a semiconductor system that further enhance security without adding an element such as a flip-flop.

A semiconductor integrated circuit according to technical features of the present disclosure generates a plurality of delay input signals that are delayed differently from a test scan input signal based on a test scan input signal, and captures a plurality of delay input signals in response to a test clock signal. A security key injecting unit configured to generate an input key signal by doing so, a key comparator configured to generate a verification result signal indicating whether an input key according to the input key signal matches a preset reference key, and a scan output based on the test scan input signal. A chip configured to generate a signal, a scan output remapper configured to obfuscate the scan output signal according to a verification result by the verification result signal, and output the obfuscated scan output signal as a security scan output signal, and a security key injection unit; It includes a secure scan controller configured to control the key comparator, chip and scan output remapper.

In addition, a semiconductor integrated circuit according to the technical idea of the present disclosure includes N delay circuits that receive a test scan input signal and output N (N is an integer greater than 1) delay input signals differently delayed from the test scan input signal. and N flip-flops that latch the logic values of the N delay input signals in response to the test clock signal and output an input key signal composed of the latched logic values. A key comparator that outputs a verification result signal indicating whether the key matches a preset reference key, a chip that generates a scan output signal based on the test scan input signal, and obfuscation of the scan output signal according to the verification result of the verification result signal. and a scan output remapper outputting the obfuscated scan output signal as a security scan output signal, and a security scan controller configured to control the security key injection unit, the key comparator, the chip, and the scan output remapper.

In addition, a method for testing a semiconductor integrated circuit according to the technical idea of the present disclosure includes changing a test scan input signal into a plurality of delay input signals having different delay values, and a plurality of delay inputs in response to a test clock signal. Generating an input key signal by capturing signals, verifying whether an input key according to the input key signal matches a preset reference key, and scanning an output signal output from a chip to be tested according to the verification result. It includes obfuscation.

In addition, a semiconductor system according to the technical concept of the present disclosure may include a test device outputting a test scan input signal, a test clock signal, and a test mode signal, and receiving the test scan input signal, the test clock signal, and the test mode signal, A semiconductor integrated circuit that outputs a security scan output signal, wherein the semiconductor integrated circuit receives a test scan input signal and outputs N (N is an integer of 1 or more) delay input signals differently delayed from the test scan input signal. N delay circuits, and N flip-flops that latch logic values of the N delay input signals in response to a test clock signal.

According to the technical concept of the present disclosure, the system is safely protected from malicious users by not using a method of receiving an authentication key using serially connected flip-flops, and the effect of further strengthening security without adding elements such as flip-flops. there is

1 is a diagram for explaining a semiconductor system according to an exemplary embodiment of the present disclosure.
2 is a diagram for explaining a semiconductor integrated circuit according to an exemplary embodiment of the present disclosure.
3 is a diagram for explaining a security key injection unit according to an embodiment of the present disclosure.
4 is a diagram illustrating an example for implementing a security key injection unit according to an embodiment of the present disclosure.
5 is a timing diagram for explaining a method of generating an input key signal according to an embodiment of the present disclosure.
6 is a diagram illustrating an implementation example of a secure scan controller for controlling a key comparator according to an embodiment of the present disclosure.
FIG. 7 is a diagram illustrating an implementation example of the key selector shown in FIG. 6 .
8 is a diagram for explaining a scan output remapper according to an embodiment of the present disclosure.
9 is a diagram illustrating an example for implementing a scan output remapper according to an embodiment of the present disclosure.
10 is a diagram illustrating an implementation example of a remap controller according to an embodiment of the present disclosure.
11 is a diagram for explaining a security scan output signal output in a test mode.
12 is a diagram for explaining a security scan output signal output in a scan dump mode.
13 is a diagram for describing a semiconductor integrated circuit according to another exemplary embodiment of the present disclosure.
14 is a diagram for describing a semiconductor integrated circuit according to another exemplary embodiment of the present disclosure.
15 is a flowchart illustrating a method of testing a semiconductor integrated circuit according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a diagram for explaining a semiconductor system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a semiconductor system 10 may include a tester 100 and a semiconductor integrated circuit 200 .

The tester 100 may be any device suitable for testing the semiconductor integrated circuit 200 . The tester 100 may have a plurality of pins. Referring to FIG. 1 , for example, the tester 100 may include a first pin P1', a second pin P2', and a third pin P3'. However, it is not limited thereto. The tester 100 may transmit a specific signal to the semiconductor integrated circuit 200 through each pin. For example, the tester 100 outputs a test scan input signal through a first pin P1', outputs a test clock signal through a second pin P2', and outputs a third pin P3'. Through this, the test mode signal can be output. The test scan input signal may be a signal arbitrarily input by a user to perform the test. Alternatively, the test scan input signal may be a signal including a key for authenticating whether a user to be tested is qualified to test the semiconductor integrated circuit 200 . The test clock signal may be a clock signal used in a test mode. The test clock signal may be constantly toggled at a specific period. In this case, when the specific period includes preset cycles, the test clock signal may be repeatedly toggled every cycle within the specific period. Alternatively, the test clock signal may be toggled only in at least one specific cycle among a plurality of cycles included in one cycle. For example, if one cycle of the test clock signal includes 100 cycles, the test clock signal may be toggled at 70th cycle, 81st to 83rd cycle, and 99th cycle among the 100 cycles. However, it is not limited thereto. The test mode signal may be a signal for performing the test mode. If the logic value of the test mode signal is a first value (or first bit value, logic high level), this may indicate to perform the test mode. Conversely, if the logic value of the test mode signal is the second value (or second bit value, logic low level), this may indicate to perform the normal mode. However, it is not limited thereto. The tester 100 in this specification may be referred to as a test device, a tester, and the like.

In one embodiment, the tester 100 is a computer system, eg, a personal computer, etc., and may include a debugging program for testing.

The semiconductor integrated circuit 200 may include a plurality of pins to receive signals output from the tester 100 . For example, the semiconductor integrated circuit 200 includes a first pin P1, a second pin P2, and a third pin P3, and through each pin, a test scan input signal, a test clock signal, and A test mode signal can be received. However, it is not limited thereto. The semiconductor integrated circuit 200 may further include a pin for outputting a scan output signal generated as a result of performing a test. For example, the semiconductor integrated circuit 200 may include a fourth pin P4.

In one embodiment, the semiconductor integrated circuit 200 includes a secure scan controller 210, a secure key injector 220, a key comparator 230, a scan output remapper 240, a circuit under test 250, and a source A one time programmable memory (hereinafter referred to as OTP) 260 may be included.

2 is a diagram for explaining a semiconductor integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , the semiconductor integrated circuit 200 may receive a test scan input signal TSI, a test clock signal TCK, and a test mode signal TMS and output a security scan output signal SSO. there is. To this end, the semiconductor integrated circuit 200 includes a security scan controller 210, a security key injection unit 220, a key comparator 230, a scan output remapper 240, a circuit under test 250, and an OTP 260. can include

The security scan controller 210 may control each of the security key injection unit 220 , the key comparator 230 , the scan output remapper 240 , and the circuit under test 250 . The secure scan controller 210 may receive a test scan input signal TSI, a test clock signal TCK, and a test mode signal TMS through the first to third pins P1 , P2 , and P3 . In one embodiment, when the test mode signal has a first value, the security scan controller 210 transmits the test scan input signal TSI as a test key signal TSI_KEY to the security key injection unit 220, The test clock signal TCK_SKI for the security key injection unit 220 may be transmitted to the security key injection unit 220 . In one embodiment, the secure scan controller 210 transmits the test clock signal TCK_KC for the key comparator 230 to the key comparator 230 and transmits a prestored reference key signal KEY_REF to the key comparator 230. can be conveyed In one embodiment, the secure scan controller 210 may transfer the test clock signal TCK_SR for the scan output remapper 240 to the scan output remapper 240 . In one embodiment, the secure scan controller 210 passes the scan control signal SC, the test data TSI_TD, and the test clock signal TCK_CHIP for the circuit under test 250 to the circuit under test 250. can

In another embodiment, the security scan controller 210 receives the key selection signal KEY_SEL from the OTP 260 and selects any one key selected by the key selection signal KEY_SEL from among a plurality of pre-stored keys as a reference key signal ( KEY_REF).

In another embodiment, the secure scan controller 210 receives the scan dump enable signal SDE and the configuration signal CFG from the circuit under test 250, and to switch from the normal mode to the scan dump mode, dump The mode signal DUMP_MODE may be transmitted to the scan output remapper 240 . The scan dump enable signal SDE may be a signal instructing to enter the scan dump mode. The configuration signal CFG may be a signal indicating internal information of the circuit under test 250 in the scan dump mode.

In another embodiment, the secure scan controller 210 may transmit a map selection signal MAP_SEL for an authorized user to decrypt the secure scan output signal SSO to the scan output remapper 240 .

The security key injection unit 220 may generate a plurality of delay input signals based on the test scan input signal TSI. The plurality of delay input signals may be signals delayed differently from each other from the test scan input signal TSI. The security key injection unit 220 may generate the input key signal KEY_CAP by capturing a plurality of delay input signals in response to the test clock signal TCK. The security key injection unit 220 may provide the input key signal KEY_CAP to the key comparator 230 .

The key comparator 230 may verify whether the input key according to the input key signal KEY_CAP matches the reference key according to the reference key signal KEY_REF. Also, the key comparator 230 may generate a verification result signal P/F indicating such a verification result. Specifically, the key comparator 230 compares the value of the input key signal KEY_CAP and the value of the reference key signal KEY_REF in response to the test clock signal TCK_KC for the key comparator 230 and passes Alternatively, a verification result signal P/F indicating a failure may be output.

In one embodiment, the key comparator 230 may additionally provide the comparison key signal KEY_COMP to the scan output remapper 240 . The comparison key signal KEY_COMP may be, for example, a signal indicating an input key compared with a reference key in a cycle in which the test clock signal TCK_KC was last toggled.

The scan output remapper 240 obfuscates the scan output signal PSO according to the verification result by the verification result signal P/F, and converts the obfuscated scan output signal into a security scan output signal. (SSO).

In one embodiment, if the verification result is PASS, the scan output remapper 240 may output the scan output signal PSO as it is through the fourth pin P4. That is, if the verification result is pass, the scan output remapper 240 de-obfuscates the scan output signal PSO, and converts the de-obfuscated scan output signal PSO to the secure scan output signal SSO on the fourth pin P4. ) can be output as is.

In one embodiment, if the verification result is fail, the scan output remapper 240 may generate obfuscation information for obfuscating the scan output signal PSO based on the comparison key signal KEY_COMP. Also, the scan output remapper 240 may obfuscate the scan output signal PSO according to the obfuscation information.

In another embodiment, the scan output remapper 240 may generate obfuscation information for obfuscating the scan output signal PSO based on the dump mode signal DUMP_MODE and the map select signal MAP_SEL.

The circuit under test 250 may be a circuit or chip to be tested or debugged. The circuit under test 250 may include a plurality of synchronization circuits connected in one scan-chain. The circuit under test 250 performs a scan operation based on the scan control signal SC, the test data TSI_TD, and the circuit under test 250 received from the security scan controller 210, and scans the output signal PSO. ), and transmits the scan output signal PSO to the scan output remapper 240. The circuit under test 250 in this specification may be referred to as a chip, circuit, core logic, on-chip logic, and the like.

OTP 260 may store authentication key data. The authentication key data may be data indicating an authentication key number generated by a manufacturer or the like. The OTP 260 may output authentication key data to the security scan controller 210 as a key selection signal KEY_SEL. The security scan controller 210 may output, as a reference key signal KEY_REF, one key selected by a key selection signal KEY_SEL among a plurality of pre-stored keys. The OTP 260 of the present specification may be implemented as a fuse, anti-fuse, or e-fuse.

3 is a diagram for explaining a security key injection unit according to an embodiment of the present disclosure.

Referring to FIG. 3 , the security key injection unit 220 may include N delay circuits and N flip-flops. N may be an integer greater than or equal to 1. Referring to FIG. 3 , for example, the security key injection unit 220 includes first to sixth delay circuits 221_1, 221_2, 221_3, 221_4, 221_5, and 221_6 and first to sixth flip-flops 222_1, 222_2, 222_3, 222_4, 222_5, 222_6). However, it is not limited thereto. Hereinafter, for convenience of description, it is assumed that the number of delay circuits and flip-flops included in the security key injection unit 220 is six.

The security scan controller 210 may transfer the test scan input signal TSI to the first to sixth delay circuits 221_1 , 221_2 , 221_3 , 221_4 , 221_5 , and 221_6 as the test key signal TSI_KEY. In this case, the first to sixth delay circuits 221_1, 221_2, 221_3, 221_4, 221_5, and 221_6 delay the test key signal TSI_KEY to generate the first to sixth delay input signals D0, D1, D2, D3, D4, D5) can be output. Delay values of the first to sixth delay input signals D0 , D1 , D2 , D3 , D4 , and D5 may be different from each other. Each of the first to sixth delay input signals D0, D1, D2, D3, D4, and D5 may be transmitted to the first to sixth flip-flops 222_1, 222_2, 222_3, 222_4, 222_5, and 222_6. .

The security scan controller 210 may transmit the test clock signal TCK_SKI for the security key injection unit 220 to the first to sixth flip-flops 222_1, 222_2, 222_3, 222_4, 222_5, and 222_6. In this case, the first to sixth flip-flops 222_1, 222_2, 222_3, 222_4, 222_5, and 222_6 respond to the test clock signal TCK_SKI to the first to sixth delay input signals D0, D1, Logic values of D2, D3, D4, and D5 may be latched, and the latched values may be transferred to the key comparator 230. Referring to FIG. 3 , for example, in response to the test clock signal TCK_SKI, the first flip-flop 222_1 latches the logic value of the first delay input signal D0, and the second flip-flop 222_2 The logic value of the second delay input signal D1 may be latched, and the third flip-flop 222_3 may latch the logic value of the third delay input signal D2. Similarly, the fourth to sixth flip-flops 222_4, 222_5, and 222_6 may also latch logic values of the fourth to sixth delay input signals D3, D4, and D5, respectively.

4 is a diagram illustrating an example for implementing a security key injection unit according to an embodiment of the present disclosure.

Referring to FIG. 4 , at least one of the first to sixth delay circuits 221_1, 221_2, 221_3, 221_4, 221_5, and 221_6 may include one or more buffers. In this case, the buffer included in the delay circuit i (i is an integer less than or equal to N, for example, 1 to 6) among the six first to sixth delay circuits 221_1, 221_2, 221_3, 221_4, 221_5, and 221_6. The number of is the number of buffers included in the jth (j is an integer different from i and less than or equal to N) delay circuits among the six first to sixth delay circuits 221_1, 221_2, 221_3, 221_4, 221_5, and 221_6, and can be different.

Referring to FIG. 4 , for example, the second delay circuit 221_2 includes four buffers 223, the third delay circuit 221_3 includes two buffers 223, and the fourth delay circuit ( 221_4 may include one buffer 223, the fifth delay circuit 221_5 may include three buffers 223, and the sixth delay circuit 221_6 may include five buffers 223. . However, it is not limited thereto, and any combination may be applied to the present embodiment as long as the number of buffers included in each delay circuit is different from each other. As the number of buffers 223 increases, the delay value may increase. That is, as the number of buffers 223 increases, the test key signal TSI_KEY may be delayed more.

In one embodiment, any one of the six first to sixth delay circuits 221_1, 221_2, 221_3, 221_4, 221_5, and 221_6 may not include a buffer. In this case, any one of the first to sixth delay circuits 221_1, 221_2, 221_3, 221_4, 221_5, and 221_6 may transfer the test key signal TSI_KEY to the corresponding flip-flop. Referring to FIG. 4 , for example, the first delay circuit 221_1 may not include a buffer, and the first delay circuit 221_1 may transmit the test key signal TSI_KEY to the first delay circuit 221_1. It can be input to the flip-flop 222_1. However, it is not limited thereto.

5 is a timing diagram for explaining a method of generating an input key signal according to an embodiment of the present disclosure.

Referring to FIGS. 4 and 5 , the test clock signal TCK_SKI and the test key signal TSI_KEY may be transmitted to the security key injection unit 220 . The test clock signal TCK_SKI may be toggled only in a specific cycle within one cycle. The test key signal TSI_KEY may have a first logic value (eg, a logic high level) from a specific point in time to another specific point in time. Each of the test clock signal TCK_SKI and the test key signal TSI_KEY may have a first logic value or a second logic value. Hereinafter, for convenience, it is assumed that the first logic value is a logic high level or 1 bit and the second logic value is a logic low level or 0 bit.

The first to sixth delay input signals D0 , D1 , D2 , D3 , D4 , and D5 may be signals obtained by delaying the test key signal TSI_KEY. The first to sixth delay input signals D0 , D1 , D2 , D3 , D4 , and D5 may each have a first logic value or a second logic value. Assuming that the number of buffers 223 included in each delay circuit is as shown in FIG. 4 , the first delay input signal D0, the fourth delay input signal D3, and the third delay input signal D2 ), the fifth delay input signal D4, the second delay input signal D1, and the sixth delay input signal D5, the delayed value may increase.

In an embodiment, the first to sixth flip-flops 222_1, 222_2, 222_3, 222_4, 222_5, and 222_6 respond to the rising edge of the test clock signal TCK_SKI at the rising edge of the test clock signal TCK_SKI. Logic values of the first to sixth delay input signals D0, D1, D2, D3, D4, and D5 may be latched. Referring to FIG. 5 , for example, in the first stage STG1, a rising edge of the test clock signal TCK_SKI may occur. At this time, the logic value of the first delay input signal D0 is a first logic value (or logic high level, or 1 bit), and the logic value of the second delay input signal D1 is a second logic value (or logic low level, or 0 bit), the logic value of the third delay input signal D2 to the fifth delay input signal D4 is a first logic value, and the logic value of the sixth delay input signal D5 is a second logic value. It can be a logical value. The first to sixth flip-flops 222_1, 222_2, 222_3, 222_4, 222_5, and 222_6 may capture an input key (KEY_CAP [D0:D5]) composed of latched logic values. [D0:D5]) may be "101110". Referring to FIG. 5 , for another example, in the second stage STG2 , a rising edge of the test clock signal TCK_SKI may occur. At this time, the logic value of the first delay input signal D0 is the second logic value, and the logic values of the second and third delay input signals D1 and D2 are the first logic value and the fourth delay input signal D3 The logic value of may be a second logic value, and the logic values of the fifth and sixth delay input signals D4 and D5 may be a first logic value. In this case, an input key (KEY_CAP [D0:D5]) composed of latched logic values may be "011011". Referring to FIG. 5 , for another example, in the third stage STG3 , a rising edge of the test clock signal TCK_SKI may occur. In this case, the logic values of the first to fifth delay input signals D0, D1, D2, D3, and D4 may be a first logic value, and the logic value of the sixth delay input signal D5 may be a second logic value. In this case, the input key (KEY_CAP [D0:D5]) may be "111110".

The security key injection unit 220 converts logic values of the first to sixth delay input signals D0, D1, D2, D3, D4, and D5 at the rising edge of the test clock signal TCK_SKI into the input key signal KEY_CAP. ), the input key signal KEY_CAP can be provided to the key comparator 230.

When the test clock signal TCK_SKI is toggled with respect to the first to sixth flip-flops 222_1, 222_2, 222_3, 222_4, 222_5, and 222_6, the first to sixth flip-flops 222_1, 222_2, 222_3, and 222_4 , 222_5, 222_6), the number of cases of the input key (KEY_CAP [D0:D5]) that can be captured is 2^6. In order for the user or the like to obtain the same input key as the reference key input to the key comparator 230, the transition of the test key signal TSI_KEY is performed by the first to sixth flip-flops 222_1, 222_2, and 222_3. , 222_4, 222_5, 222_6) must be known, and the skew between the transition of the test key signal (TSI_KEY) and the test clock signal (TCK_SKI) to capture the desired key value must be accurately input. . Therefore, according to the embodiment according to the present disclosure, since it is difficult for a malicious user to accurately input a skew between the transition of the test key signal TSI_KEY and the test clock signal TCK_SKI, security is enhanced.

As described above, since the degree of encryption can be increased without adding a flip-flop, there is an effect of promoting higher security and reliability.

6 is a diagram illustrating an implementation example of a secure scan controller for controlling a key comparator according to an embodiment of the present disclosure.

Referring to FIG. 6 , the security scan controller 210 may provide a reference key signal KEY_REF and a test clock signal TCK_KC to the key comparator 230 . The security scan controller 210 may count a stage corresponding to the number of times the plurality of delay input signals are captured whenever a plurality of delay input signals are captured. 4 and 6, for example, the security scan controller 210, the first to sixth delay input signals (D0, D1, D2, D3, D4, D5) in the first stage (STG1) When captured, the first stage STG1 may be counted. Also, when the first to sixth delay input signals D0, D1, D2, D3, D4, and D5 are captured in the second stage STG2, the security scan controller 210 performs a second stage STG2. can be counted. Also, when the first to sixth delay input signals D0, D1, D2, D3, D4, and D5 are captured in the third stage STG3, the security scan controller 210 performs a third stage STG3. can be counted. The security scan controller 210 may provide a key corresponding to the counted stage among a plurality of pre-stored keys to the key comparator 230 as a reference key.

In one embodiment, the secure scan controller 210 includes a key selector 211, a stage counter 212, a first OR gate 213, a first OR gate 214, a second OR gate 215, a second OR gate 215, A 2 AND gate 216 may be included.

In response to the stage signal STG, the key selector 211 selects one key as a reference key according to a counted stage among a plurality of pre-stored keys, and transmits the reference key signal KEY_REF to the key comparator 230. can In one embodiment, the key selector 211 may transfer the reference key signal KEY_REF to the key comparator 230 in response to the key selection signal KEY_SEL received from the OTP 260 .

The stage counter 212 may count a stage corresponding to the number of times the logic values of the N delay input signals are latched and output a stage signal STG indicating the counted stage. Referring to FIGS. 5 and 6 , for example, the stage counter 212 outputs stage signals STG sequentially indicating the first stage STG1 , the second stage STG2 , and the third stage STG3 . can The stage counter 212 may output a comparison signal COMP instructing a comparison operation whenever a stage is counted. The comparison signal COMP may have a first logic value or a second logic value, and while the stage is being counted, the comparison signal COMP may have the first logic value. When the comparison operation of the key comparator 230 is completed or when the preset number of stage counts is satisfied, the stage counter 212 may output a comparison completion signal COMP_DONE to the first OR gate 214 . The comparison completion signal COMP_DONE may have a first logic value or a second logic value. When the comparison operation of the key comparator 230 is completed, the comparison signal COMP may have a second logic value and the comparison completion signal COMP_DONE may have a first logic value.

The first AND gate 213 performs an AND operation of the comparison signal COMP and the test clock signal TCK, and the result is used as the test clock signal TCK_KC for the key comparator 230. The key comparator 230 can be provided to The first AND gate 213 may be referred to as an AND gate.

The first OR gate 214 may perform the OR operation of the comparison completion signal COMP_DONE and the dump mode signal DUMP_MODE and provide the result as the system reset signal SYS_nRESET to the circuit under test 250 . The dump mode signal DUMP_MODE may have a first logic value or a second logic value. When the dump mode signal DUMP_MODE has a first logic value, it may mean that the scan dump mode is entered. The system reset signal SYS_nRESET may be a signal indicating that the circuit under test 250 is reset.

The second OR gate 215 may perform a OR operation on the comparison completion signal COMP_DONE and the dump mode signal DUMP_MODE and provide the result to the second AND gate 216 .

The second AND gate 216 performs the AND operation of the output of the second OR gate 215 and the test clock signal TCK provided from the outside, and the result is the test clock signal (for the circuit under test 250) TCK_CHIP).

The key comparator 230 may output a signal indicating a pass as a verification result signal P/F when the input key by the input key signal KEY_CAP coincides with the reference key by the reference key signal KEY_REF. . In this case, the signal indicating the pass may be, for example, a signal having a first logic value. Meanwhile, if the input key is different from the reference key, the key comparator 230 may output a signal indicating a fail as a verification result signal P/F. In this case, the signal indicating a fail is, for example, a second logic It can be a signal with a value. However, it is not limited thereto.

FIG. 7 is a diagram illustrating an implementation example of the key selector shown in FIG. 6 .

Referring to FIGS. 5, 6, and 7 , the key selector 211 may store in advance stage keys 211_1 corresponding to stages and authentication key sets 211_2 corresponding to authentication key numbers. This key selector 211 may include a first multiplexer 211_3 and a second multiplexer 211_4. The number of stage keys 211_1 may be m, but is not limited thereto. Here, m may be an integer greater than or equal to 2.

The first multiplexer 211_3 may output a stage key selected from among the stage keys 211_1 according to the stage signal STG. Referring to FIGS. 5 and 7 , for example, when the stage signal STG indicates the first stage STG1, the first multiplexer 211_3 may output a first stage key KEY_0.

The second multiplexer 211_4 selects a key from the stage key selected by the first multiplexer 211_3 and the authentication key set 211_2 according to the key selection signal KEY_SEL (or authentication key data), and selects a key according to the reference key signal KEY_REF. ) can be output.

8 is a diagram for explaining a scan output remapper according to an embodiment of the present disclosure.

Referring to FIG. 8 , the scan output remapper 240 includes a remap controller 241, a first register set 242, a second register set 243, a first selector 244, and a second selector 245. can include

The remap controller 241 includes a test clock signal (TCK_SR), a scan output signal (PSO), a verification result signal (P/F), a dump mode signal (DUMP_MODE), and a comparison key signal for the scan output remapper 240. (KEY_COMP) can be received. Depending on embodiments, the remap controller 241 may further receive a map selection signal MAP_SEL. The remap controller 241 may transmit the scan output signal PSO to the first and second register sets 242 and 243 . The remap controller 241 outputs the first clock signal TCK_1 to the first register set 242 and generates the second clock signal TCK_2 based on the test clock signal TCK_SR and the comparison key signal KEY_COMP. It can be output to the second register set 243. The remap controller 241 may output the first scan enable signal SE_1 to the first register set 242 and provide the second scan enable signal SE_2 to the second register set 243 for output. . According to an embodiment, the second scan enable signal SE_2 may be an inverted signal of the first scan enable signal SE_1.

The first register set 242 latches the scan output signal PSO in response to the first scan enable signal SE_1 and the first clock signal TCK_1 and outputs the latched first scan output signal OSO1. can do. The first register set 242 may be connected to ground (GND).

The second register set 243 latches the scan output signal PSO in response to the second scan enable signal SE_2 and the second clock signal TCK_2, and outputs the latched second scan output signal OSO2. can do. The second register set 243 may be connected to ground (GND).

The first selector 244 may select one of the first scan output signal OSO1 and the second scan output signal OSO2 according to the second scan enable signal SE_2.

The second selector 245 converts one of the scan output signal OSO_SEL and the scan output signal PSO selected from the first selector 244 to the security scan output signal SSO according to the verification result signal P/F. can be printed out.

9 is a diagram illustrating an example for implementing a scan output remapper according to an embodiment of the present disclosure.

Referring to FIG. 9 , the first register set 242 may include r first flip-flops (r is an integer greater than or equal to 1) cascaded in series. Cascade in series may be a form in which the output terminal of the current flip-flop is connected to the input terminal of the next flip-flop. Referring to FIG. 9 , for example, the first register set 242 may include four first flip-flops 242_1, 242_2, 242_3, and 242_4 to which the output of the current flip-flop and the input of the next flip-flop are connected. there is. However, it is not limited thereto. Hereinafter, it is assumed that the number of first flip-flops is four. Each of the first flip-flops 242_1, 242_2, 242_3, and 242_4 may latch the scan output signal PSO in response to rising edges of the four first clock signals TCK_11, TCK_12, TCK_13, and TCK_14. In the first flip-flops 242_1, 242_2, 242_3, and 242_4, the first flip-flop 242_1 receives the ground (GND) through the scan input terminal (SI), and the three first flip-flops 242_2, 242_3, 242_4), the scan output terminal (SO) of the previous flip-flop may be connected to the scan input terminal (SI) of the next flip-flop. The first flip-flops 242_4 may correspond to the most significant bit (MSB), and the first flip-flop 242_1 may correspond to the least significant bit (LSB).

The second register set 243 may include r second flip-flops cascaded in series. Referring to FIG. 9 , for example, the second register set 243 may include four second flip-flops 243_1, 243_2, 243_3, and 243_4 to which the output of the current flip-flop and the input of the next flip-flop are connected. there is. However, it is not limited thereto. Hereinafter, it is assumed that the number of second flip-flops is four. Each of the second flip-flops 243_1, 243_2, 243_3, and 243_4 may latch the scan output signal PSO in response to rising edges of the four second clock signals TCK_21, TCK_22, TCK_23, and TCK_24. In the second flip-flops 243_1, 243_2, 243_3, and 243_4, the second flip-flop 243_1 receives the ground (GND) through the scan input terminal (SI), and the three second flip-flops 243_2, 243_3, 243_4), the scan output terminal (SO) of the previous flip-flop may be connected to the scan input terminal (SI) of the next flip-flop. The second flip-flops 243_4 may correspond to the most significant bit (MSB), and the second flip-flop 243_1 may correspond to the least significant bit (LSB).

The remap controller 241 may output four first clock signals TCK_11 , TCK_12 , TCK_13 , and TCK_14 to the first register set 242 . The remap controller 241 may output four second clock signals TCK_21 , TCK_22 , TCK_23 , and TCK_24 to the second register set 243 . The remap controller 241 may output the first scan enable signal SE_1 to the first register set 242 .

The scan output remapper 240 may further include an inverter 246 . The inverter 246 may invert the first scan enable signal SE_1 and output the second scan enable signal SE_2 to the second register set 243 .

In one embodiment, the first selector 244 may be implemented as a first multiplexer 244_1. However, it is not limited thereto. The first multiplexer 244_1 may select and output the first scan output signal OSO1 or the second scan output signal OSO2 according to the logic value of the second scan enable signal SE_2. For example, when the logic value of the second scan enable signal SE_2 is a first logic value (eg, a logic high level), the first multiplexer 244_1 outputs the second scan output signal OSO2. can do. For another example, when the logic value of the second scan enable signal SE_2 is a second logic value (eg, a logic low level), the first multiplexer 244_1 outputs the first scan output signal OSO1. can be printed out.

In one embodiment, the second selector 245 may be implemented as a second multiplexer 245_1. However, it is not limited thereto. The second multiplexer 245_1 may select and output the selected scan output signal OSO_SEL or scan output signal PSO according to the logic value of the verification result signal P/F. For example, when the logic value of the verification result signal P/F is a first logic value (eg, pass or logic high level), the second multiplexer 245_1 converts the scan output signal PSO to a security scan. It can be output as an output signal (SSO). For another example, when the logic value of the verification result signal P/F is a second logic value (eg, fail or logic low level), the second multiplexer 245_1 outputs the selected scan output signal OSO_SEL. It can be output as a security scan output signal (SSO).

10 is a diagram illustrating an implementation example of a remap controller according to an embodiment of the present disclosure.

Referring to FIG. 10 , the remap controller 241 generates obfuscation information for obfuscating the scan output signal PSO based on the comparison key signal KEY_COMP, and generates the scan output signal PSO according to the obfuscation information. can obfuscate. Such obfuscation information may be represented by the timing of the rising edge of r first clock signals TCK_1 [r-1:0] or r second clock signals TCK_2 [r-1:0].

The remap controller 241 includes a linear-feedback shift register 241_1, a one-hot encoder 241_2, a first multiplexer 241_3, a second multiplexer 241_4, a third multiplexer 241_5, and r first logical products. Gates 241_6 and r second AND gates 241_7 may be included.

The linear-feedback shift register 241_1 may output r linear signals LO based on the comparison key signal KEY_COMP. Here, the number of linear signals LO may be equal to the number of flip-flops included in the first and second register sets 242 and 243 .

The one-hot encoder 241_2 may output r number of encoding signals EO based on the map selection signal MAP_SEL. Here, the number of encoding signals EO may be equal to the number of flip-flops included in the first and second register sets 242 and 243 .

The r linear signals LO and the r encoding signals EO may correspond to the aforementioned obfuscation information.

The first multiplexer 241_3 may output r linear signals LO or r encoding signals EO according to the logic value of the dump mode signal DUMP_MODE. For example, when the logic value of the dump mode signal DUMP_MODE is a first logic value, the first multiplexer 241_3 may output r number of encoding signals EO. For another example, when the logic value of the dump mode signal DUMP_MODE is the second logic value, the first multiplexer 241_3 may output r linear signals LO.

The second multiplexer 241_4 outputs the first data 241_8 having a pre-stored first logic value or the output signal of the first multiplexer 241_3 according to the logic value of the first scan enable signal SE_1. can For example, when the logic value of the first scan enable signal SE_1 is the first logic value, the second multiplexer 241_4 may output first data 241_8. For another example, when the logic value of the first scan enable signal SE_1 is the second logic value, the second multiplexer 241_4 may output the output signal of the first multiplexer 241_3.

The third multiplexer 241_5 may output the second data 241_9 having a pre-stored first logic value or the output signal of the first multiplexer 241_3 according to the logic value of the first scan enable signal SE_1. there is. For example, when the logic value of the first scan enable signal SE_1 is the first logic value, the third multiplexer 241_5 may output the output signal of the first multiplexer 241_3. For another example, when the logic value of the first scan enable signal SE_1 is the second logic value, the third multiplexer 241_5 may output second data 241_9.

Depending on the embodiment, the first data 241_8 and the second data 241_9 may be stored as one data in the same storage space or stored in different storage spaces.

The r number of first AND gates 241_6 may perform an AND operation of the test clock signal TCK_SR and the output signal of the second multiplexer 241_4, respectively.

The r number of second AND gates 241_7 may perform an AND operation of the test clock signal TCK_SR and the output signal of the third multiplexer 241_5, respectively.

11 is a diagram for explaining a security scan output signal output in a test mode.

9, 10, and 11, for convenience, the number of cycles of the test clock signal TCK_SR is 12, r is 4, and the logic value (or bit value) of the linear signals LO is each cycle. Each sequentially, "0011", "0001", "1000", "0100", "0010", "1001", "1100", "0110", "1011", "0101", "1010", "1101" ", and "-" assumes that the first clock signals (TCK_11, TCK_12, TCK_13, TCK_14) and the second clock signals (TCK_21, TCK_22, TCK_23, TCK_24) are gated. "En" is The first clock signals TCK_11, TCK_12, TCK_13, and TCK_14 and the second clock signals TCK_21, TCK_22, TCK_23, and TCK_24 are enabled, have a rising edge, or are input to each flip-flop, It is assumed that “SR_A [3:0]” is the first scan output signal OSO1 and “SR_B [3:0]” is the second scan output signal OSO2.

It is assumed that the logic values of the first scan enable signal SE_1 and the logic values of the second scan enable signal SE_2 alternate every four cycles. For example, from the first cycle to the fourth cycle (ie, from cycle count 0 to cycle count 3), the logic value of the first scan enable signal SE_1 is a logic low level, and the second scan enable signal The logic value of (SE_1) may be a logic high level. In this case, the security scan output signal SSO may be a signal output from the four second flip-flops 243_1, 243_2, 243_3, and 243_4. Further, from the fifth cycle to the eighth cycle (ie, from the 4th cycle count to the 7th cycle count), the logic value of the first scan enable signal SE_1 is a logic high level, and the second scan enable signal SE_1 ) may be a logic low level. In this case, in this case, the security scan output signal SSO may be a signal output from the four first flip-flops 242_1, 242_2, 242_3, and 242_4.

In the first cycle, that is, when the cycle count is 0, the value of the scan output signal PSO is “p0” and only the first clock signals TCK_11 and TCK_12 are enabled. The first flip-flops 242_1 and 242_2 may latch “p0” in response to the rising edge of the first clock signals TCK_13 and TCK_14. In the second cycle, that is, when the cycle count is 1, the value of the scan output signal PSO is “p1” and only the first clock signal TCK_11 is enabled. The first flip-flop 242_1 may latch “p1” in response to the rising edge of the first clock signal TCK_11. In the third cycle, that is, when the cycle count is 2, only the first clock signal TCK_14 is enabled, and the first flip-flop 242_4 latches “p2” in response to the rising edge of the first clock signal TCK_14. can do. When the cycle count is 3, only the first clock signal TCK_13 is enabled, and the first flip-flop 242_3 may latch “p3” in response to the rising edge of the first clock signal TCK_13.

When the cycle count is 4 to 7, the security scan output signal SSO outputs the output values of each flip-flop from the first flip-flop 242_4 corresponding to the MSB to the first flip-flop 242_1 corresponding to the LSB. You can print sequentially. When the cycle count is 4, the security scan output signal (SSO) is "p2", when the cycle count is 5, the security scan output signal (SSO) is "p3", and when the cycle count is 6, the security scan output signal (SSO) is "p0", and when the cycle count is 7, the security scan output signal (SSO) may be "p1".

When the cycle count is 4, only the second clock signal TCK_22 is enabled. The second flip-flop 243_2 may latch “p4” in response to the rising edge of the second clock signal TCK_22. When the cycle count is 5, the second flip-flops 243_1 and 243_4 may latch “p5” in response to the rising edge of the second clock signals TCK_21 and TCK_24. Similarly, when the cycle count is 6, the second flip-flops 243_3 and 243_4 may latch “p6”. When the cycle count is 7, the second flip-flops 243_2 and 243_3 may latch “p7”.

When the cycle count is 8 to 11, from the second flip-flop 243_4 corresponding to the MSB to the second flip-flop 243_1 corresponding to the LSB, "p6", "p7", "p7", or A security scan output signal SSO having “p5” may be output.

12 is a diagram for explaining a security scan output signal output in a scan dump mode.

Referring to FIGS. 9, 10, 11, and 12, similar to FIG. 11, for convenience, the number of cycles of the test clock signal TCK_SR is 8, r is 4, and the value of the map selection signal MAP_SEL is Assume {2'b00, 2'b10, 2'b11, 2'b01} (or "00101101"). At this time, {A, B, C, D} indicating values of the map selection signal MAP_SEL indicate priorities from the flip-flops corresponding to the MSB to the flip-flops corresponding to the LSB. For example, in {A, B, C, D}, the first bit position (ie, "A") corresponds to the flip-flop (eg, the first flip-flop 242_4 and the second flip-flop ( 243_4)), and the second bit position (ie, “B”) corresponds to (MSB-1) flip-flops (eg, the first flip-flop 242_3 and the second flip-flop 243_3). )), and the third bit position (ie, "C") corresponds to (MSB-2) the flip-flop (eg, the first flip-flop 242_2 and the second flip-flop 243_2) ), and the fourth bit position (ie, "D") indicates the priority of the flip-flops (eg, the first flip-flop 242_1 and the second flip-flop 243_1) corresponding to the LSB. can indicate Also, the lower the value in parentheses ("{}"), the faster the latching sequence. For example, in the case of {2'b00, 2'b10, 2'b11, 2'b01}, the latching order is the flip-flop corresponding to the MSB, the flip-flop corresponding to the LSB, and the flip-flop corresponding to (MSB-1) A flip-flop, and a flip-flop corresponding to (MSB-2). In this case, the logic values of the encoding signals EO may be repeated every four cycles as "1000", "0001", "0100", and "0010".

Meanwhile, as shown in FIG. 11 , it is assumed that the logic values of the first scan enable signal SE_1 and the logic values of the second scan enable signal SE_2 alternate with each other every four cycles.

When the cycle count is 0, the first flip-flop 242_4 may latch “p0”. When the cycle count is 1, the first flip-flop 242_1 may latch “p1”. When the cycle count is 2, the first flip-flop 242_3 may latch “p2”. When the cycle count is 3, the first flip-flop 242_2 may latch “p3”. A value of the security scan output signal SSO may be “0”.

When the cycle count is 4, the second flip-flop 243_4 may latch “p4”. When the cycle count is 5, the second flip-flop 243_1 may latch “p5”. When the cycle count is 6, the second flip-flop 243_3 may latch “p6”. When the cycle count is 7, the second flip-flop 243_2 may latch “p7”. Values of the security scan output signal SSO may be sequentially “p0”, “p2”, “p3”, and “p1”.

13 is a diagram for describing a semiconductor integrated circuit according to another exemplary embodiment of the present disclosure.

Referring to FIG. 13 , the semiconductor integrated circuit 400 may include first to fourth pins P1 , P2 , P3 , and P4 as described above with reference to FIG. 1 . The semiconductor integrated circuit 400 may include a single lock key circuit 410 and a plurality of chips 420_1, 420_2, ..., 420_n. n may be an integer of 2 or greater.

The single lock key circuit 410 includes the security scan controller 210 shown in FIG. 1, the security key injection unit 220, the key comparator 230, the scan output remapper 240, the circuit under test 250, and OTP 260 may be included.

The single lock key circuit 410 may include the security scan controller 210, the security key injection unit 220, the key comparator 230, the scan output remapper 240, and the OTP 260 shown in FIG. can

Each of the plurality of chips 420_1, 420_2, ..., 420_n may correspond to the circuit under test 250 shown in FIG. 1 . The plurality of chips 420_1, 420_2, ..., 420_n may include a plurality of test interfaces 421_1, 421_2, ..., 421_n. The plurality of test interfaces 421_1, 421_2, ..., 421_n may be interfaces for communicating with the single lock key circuit 410 in a test mode or a scan dump mode. According to embodiments, the plurality of chips 420_1, 420_2, ..., 420_n may be implemented as a plurality of circuits.

14 is a diagram for describing a semiconductor integrated circuit according to another exemplary embodiment of the present disclosure.

Referring to FIG. 14 , the semiconductor integrated circuit 500 may include first and second pins P1' and P2'. The semiconductor integrated circuit 500 may receive the test scan input signal TSI or the test clock signal TCK through the first pin P1'. The semiconductor integrated circuit 500 may output the security scan output signal SSO through the second pin P2'.

The semiconductor integrated circuit 500 may include a single lock key circuit group 510 , a plurality of chips 520_1 , 520_2 , ..., 520_n , and a demultiplexer 530 .

The single lock key circuit group 510 may include a plurality of single lock key circuits 510_1, 510_2, ..., 510_n. Each of the plurality of single lock key circuits 510_1, 510_2, ..., 510_n may correspond to the single lock key circuit 410 described above with reference to FIG. 13 .

The plurality of chips 520_1, 520_2, ..., 520_n may correspond to the plurality of chips 420_1, 420_2, ..., 420_n described above with reference to FIG. 13 .

In one embodiment, the first single lock key circuit 510_1 may communicate with the first test interface 521_1 included in the first chip 520_1. The second single lock key circuit 510_2 may communicate with the second test interface 521_2 included in the second chip 520_2. The nth single lock key circuit 510_n may communicate with the nth test interface 521_n included in the nth chip 520_n.

The demultiplexer 530 may transmit a signal received from the outside to the plurality of single lock key circuits 510_1, 510_2, ..., 510_n through the first pin P1'.

15 is a flowchart illustrating a method of testing a semiconductor integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 15 , a method of testing a semiconductor integrated circuit includes changing a test scan input signal into a plurality of delay input signals having different delay values (S310), and a plurality of delay inputs in response to a test clock signal. Generating an input key signal by capturing signals (S320), verifying whether an input key according to the input key signal matches a preset reference key (S330), obtaining a scan output signal from a chip (S340) ), and obfuscating the scan output signal output from the chip to be tested according to the verification result (S350, S360, S370, S380).

In the case of the step of obfuscating the scan output signal output from the chip to be tested (S350, S360, S370, S380) according to the verification result, the step of checking whether the verification pass (S350), if the verification result is pass (S350, YES), outputting the scan output signal to the outside through an output pin (S360), if the verification result is fail (S350, NO), obfuscating the scan output signal (S370) and obfuscated scan Outputting the output signal to the outside through the output pin (S380) may be performed.

In one embodiment, each of the plurality of delay input signals may have a first logic value or a second logic value different from the first logic value. In this case, in the step of generating the input key signal (S320), logic values of a plurality of delay input signals at the rising edge of the test clock signal may be generated as the input key signal.

In one embodiment, in the step of verifying whether the input key according to the input key signal matches a preset reference key (S330), if the input key matches the reference key, a signal indicating a pass may be output. Meanwhile, if the input key is different from the reference key, a signal indicating a fail may be output.

In one embodiment, in step S360 of outputting the scan output signal to the outside through an output pin, the decrypted scan output signal may be output as a secure scan output signal.

In one embodiment, in step S380 of outputting the obfuscated scan output signal to the outside through an output pin, the obfuscated scan output signal may be output as a secure scan output signal.

As described above, reliability and security are improved by preventing malicious use of a circuit for performing a test.

In addition, as described above, by inputting the test scan input to the flip-flop in a parallelized input method, the number of security key input cases can be exponentially increased, thereby further increasing security. has the effect of

In addition, as described above, instead of adding a flip-flop implemented in a serialized input method to enhance security, a test scan input input to the flip-flop in a parallelized input method By inputting once again, there is an effect of reducing manufacturing cost and integrating products.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

A semiconductor integrated circuit that receives a test scan input signal, a test clock signal, and a test mode signal from the outside and outputs a security scan output signal,
generate a plurality of delay input signals differently delayed from the test scan input signal based on the test scan input signal, and generate an input key signal by capturing the plurality of delay input signals in response to the test clock signal; a security key injection unit;
a key comparator configured to generate a verification result signal indicating whether an input key according to the input key signal matches a preset reference key;
a chip configured to generate a scan output signal based on the test scan input signal;
a scan output remapper configured to obfuscate the scan output signal according to a verification result of the verification result signal and output the obfuscated scan output signal as the secure scan output signal; and
and a secure scan controller configured to control the secure key injection unit, the key comparator, the chip, and the scan output remapper. According to claim 1,
The security scan controller,
Providing the test scan input signal and the test clock signal to the security key injection unit;
The plurality of delay input signals, respectively
has a first logic value or a second logic value different from the first logic value;
The security key injection unit,
and generating logic values of the plurality of delay input signals at a rising edge of the test clock signal as the input key signal, and providing the input key signal to the key comparator. According to claim 1,
The security scan controller,
Providing a reference key signal representing the reference key and the test clock signal to the key comparator;
The key comparator,
If the input key coincides with the reference key, providing a signal indicating a pass to the scan output remapper as the verification result signal;
and providing a signal indicating a fail to the scan output remapper as the verification result signal when the input key is different from the reference key. According to claim 3,
The security scan controller,
Each time the plurality of delay input signals are captured, a stage corresponding to the number of times the plurality of delay input signals are captured is counted;
A semiconductor integrated circuit characterized in that a key corresponding to a counted stage among a plurality of keys stored in advance is provided to the key comparator as the reference key. According to claim 3,
The key comparator,
If the input key is different from the reference key, additionally providing a comparison key signal to the scan output remapper;
The scan output remapper,
and generating obfuscation information for obfuscating the scan output signal based on the comparison key signal, and obfuscating the scan output signal according to the obfuscation information. According to claim 1,
The scan output remapper,
characterized in that, if the verification result by the verification result signal is pass, outputting the decrypted scan output signal as the security scan output signal. A semiconductor integrated circuit that receives a test scan input signal, a test clock signal, and a test mode signal from the outside and outputs a security scan output signal,
N delay circuits receiving the test scan input signal and outputting N (N is an integer greater than 1) delay input signals differently delayed from the test scan input signal, and the N delay circuits in response to the test clock signal a security key injection unit including N flip-flops that latch logic values of input signals and output an input key signal composed of the latched logic values;
a key comparator outputting a verification result signal indicating whether the input key by the input key signal matches a preset reference key;
a chip generating a scan output signal based on the test scan input signal;
a scan output remapper that obfuscates the scan output signal according to a verification result of the verification result signal and outputs the obfuscated scan output signal as the security scan output signal; and
and a secure scan controller configured to control the secure key injection unit, the key comparator, the chip, and the scan output remapper. According to claim 7,
The security scan controller,
providing the test scan input signal to the N delay circuits and providing the test clock signal to the N flip-flops;
The N flip-flops are, respectively
and latching logic values of the N delay input signals at the rising edge of the test clock signal in response to the rising edge of the test clock signal. According to claim 8,
At least one of the N delay circuits includes one or more buffers,
The number of buffers included in the ith (i is an integer less than or equal to N) delay circuit among the N delay circuits is the jth (j is an integer less than or equal to i and is different from i) delay circuit among the N delay circuits. A semiconductor integrated circuit, characterized in that different from the number of included buffers. According to claim 9,
Any one of the N delay circuits does not include a buffer and inputs the test scan input signal to a flip-flop corresponding to any one of the N flip-flops. , a semiconductor integrated circuit. According to claim 7,
The security scan controller,
A stage counter that counts stages corresponding to the number of times logic values of the N delay input signals are latched and outputs a stage signal indicating a counted stage and outputs a comparison signal indicating a comparison operation whenever the stage is counted ;
a key selector configured to provide a key selected according to the counted stage among a plurality of previously stored keys in response to the stage signal to the key comparator as the reference key; and
and a first AND gate for performing an AND operation of the comparison signal and the test clock signal and providing a result of the AND operation to the key comparator. According to claim 11,
Further comprising a one-time programmable memory for providing a key selection signal indicating a pre-stored authentication key number to the key selector;
A plurality of pre-stored keys,
Includes stage keys corresponding to stages and an authentication key set corresponding to the authentication key number;
The key selector,
a first multiplexer outputting a stage key selected from among the stage keys according to a stage signal;
and a second multiplexer outputting a key selected according to the key selection signal among the selected stage key and the authentication key set as the reference key. According to claim 7,
The security scan controller,
providing the test clock signal to the scan output remapper;
The key comparator,
additionally providing a comparison key signal to the scan output remapper;
The scan output remapper,
a remap controller that transmits the scan output signal, outputs a first clock signal and a second clock signal based on the test clock signal and the comparison key signal, and outputs a first scan enable signal;
an inverter inverting the first scan enable signal to output a second scan enable signal;
a first register set that latches the scan output signal in response to the first scan enable signal and the first clock signal and outputs the latched first scan output signal;
a second register set that latches the scan output signal in response to the second scan enable signal and the second clock signal and outputs the latched second scan output signal;
a first selector selecting one of the first scan output signal and the second scan output signal according to the second scan enable signal; and
and a second selector outputting one of the scan output signal selected from the first selector and the scan output signal as the security scan output signal according to the verification result signal. According to claim 13,
The first register set,
It includes r first flip-flops (r is an integer greater than or equal to 1) cascaded in series;
The second register set,
A semiconductor integrated circuit comprising r second flip-flops cascaded in series. According to claim 13,
The first selector is a first multiplexer,
The semiconductor integrated circuit characterized in that the second selector is a second multiplexer. changing the test scan input signal into a plurality of delay input signals having different delay values;
generating an input key signal by capturing the plurality of delay input signals in response to a test clock signal;
verifying whether an input key according to the input key signal coincides with a preset reference key; and
A method for testing a semiconductor integrated circuit, comprising obfuscating a scan output signal output from a chip to be tested according to a verification result. According to claim 16,
The plurality of delay input signals, respectively
has a first logic value or a second logic value different from the first logic value;
Generating the input key signal,
The method of testing a semiconductor integrated circuit, characterized in that for generating the logic values of the plurality of delay input signals at the rising edge of the test clock signal as the input key signal. According to claim 16,
The verification step is
If the input key coincides with the reference key, outputting a signal indicating a pass;
and outputting a signal indicating a fail when the input key is different from the reference key. According to claim 18,
If the verification result is pass, outputting the decrypted scan output signal as a secure scan output signal. According to claim 18,
and outputting the obfuscated scan output signal as a security scan output signal if the verification result is a fail.

Images