KR20140106663A - Light emitter devices and methods with reduced dimensions and improved light output - Google Patents

Light emitter devices and methods with reduced dimensions and improved light output Download PDF

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Publication number
KR20140106663A
KR20140106663A KR1020147018718A KR20147018718A KR20140106663A KR 20140106663 A KR20140106663 A KR 20140106663A KR 1020147018718 A KR1020147018718 A KR 1020147018718A KR 20147018718 A KR20147018718 A KR 20147018718A KR 20140106663 A KR20140106663 A KR 20140106663A
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South Korea
Prior art keywords
submount
light emitting
lens
emitting device
less
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KR1020147018718A
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Korean (ko)
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데이빗 티. 에멀슨
저스틴 라이돈
레이 로사도
제프리 칼 브릿
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크리,인코포레이티드
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Publication of KR20140106663A publication Critical patent/KR20140106663A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

There is provided a light emitting device and a method having a reduced numerical value and an improved light output. In one embodiment, the light emitting device comprises a submount having an area of about 6 mm 2 or less; A light emitting chip on the submount; A lens disposed on the light emitting chip and disposed on the submount, and capable of emitting light of about 100 lumens or more.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting device and a light emitting device having reduced dimensions and an improved light output,

This application claims priority to U.S. Patent Application No. 13 / 312,518, filed December 6, 2011, which is incorporated herein by reference in its entirety.

A subject of the present invention relates to a light emitting device and a method. More particularly, the subject matter of the present invention relates to light emitting devices and methods having reduced dimensions and improved light output.

Light emitting diodes (LEDs) are used, for example, to provide blue, red and green light, combinations of light having different color points, and other color points of white light (e.g., white or near- A light emitting device or a package. Light emitting devices or packages are being developed as replacements for incandescent, fluorescent and metal halide high intensity discharge (HID) lighting products. Conventional devices can use optical elements such as lenses to improve the amount of light extracted from such devices. The problem with existing lenses is that various dimensions or lens and submount ratios, edge exclusion, and other dimensions are not fully reduced and / or improved for light output. This is because, on one side, the existing lens failed to expand close to the edge of the submount. Currently, the designers and manufacturers of light emitting devices and light emitting products tend to use and apply products that use numerically smaller light emitting devices. Thus, improving light output from a light emitting device is becoming more and more important in maintaining or exceeding optical properties, such as expected brightness levels, that are expected from a given device.

Despite the availability of a variety of light emitting devices in the market, there is still a need for devices and methods with improved efficiency and light output.

It is an object of the present invention to provide a light emitting device and a method having reduced dimensions and improved light output.

To achieve the above object, there is provided a light emitting device according to an aspect of the present invention, comprising: a submount having an area of about 6 mm 2 or less; A light emitting chip on the submount; A lens disposed on the light emitting chip and disposed on the submount, and a light emitting device emitting light of about 100 lumens or more can be provided.

According to another aspect of the present invention there is provided a lithographic apparatus comprising : a submount having an area less than or equal to about 6 mm 2 ; A light emitting chip on the submount; And a lens disposed on the light emitting chip, the lens being disposed on the submount; And emitting light from a light emitting device having an optical output of at least about 100 lumens.

According to the embodiment of the present invention, light output and efficiency can be improved from a numerically reduced light emitting device.

BRIEF DESCRIPTION OF THE DRAWINGS The complete and enabling disclosure of the present invention, including the best mode for carrying out the invention to those of ordinary skill in the art, is described in more detail with reference to the accompanying drawings in the remainder of the specification;
1 is a top perspective view of an embodiment of a light emitting device according to the present invention.
2 is another upper perspective view of the light emitting device of FIG.
3A and 3B are top plan views of the light emitting device of Fig.
4 is a side view of the light emitting device of FIG.
Fig. 5 is a bottom view of the light emitting device of Fig. 1;
6A to 6C are a plan view, a cross-sectional view, and a bottom view, respectively, of a light emitting chip according to the present invention.
Figures 7 and 8 show various shapes associated with the light emitting chip according to the subject matter of the present invention.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Each example is provided to illustrate the invention and does not limit the scope of the invention. Indeed, features shown and described as part of one embodiment may be used in other embodiments to create another embodiment. The subject matter of the invention disclosed and disclosed herein includes such modifications and variations.

As shown in the various figures, the dimensions of structures or portions are exaggerated relative to other structures and portions for purposes of explanation and are provided to illustrate the general structure of the present invention. Moreover, various aspects of the present invention are described with reference to structures or portions formed on other structures, portions, or both. As will be appreciated by one of ordinary skill in the art, when referring to another structure or portion being "on" or "on" a structure is added, the additional structure, portion, or both may be interposed therebetween Will be considered. Quot; or " on " another structure or portion without the intervening structure or portion is described herein as being formed "directly on " Similarly, when an element is referred to as being "connected," "attached," or "coupled" to another element, the element is directly connected, attached, May be understood to exist. In contrast, when a component is referred to as being "directly connected", "directly attached", or "directly coupled", there is no intervening component.

Further, the terms "on", "above", "upper", "upper", "lower", or "bottom" may refer to other structures of a structure or part It is used to describe the relationship with the part. It is to be understood that other terms such as "on "," on ", "above "," upper ", "lower ", or" bottom "are intended to encompass different orientations of the device, . For example, when inverting a device shown in the figures, structures or portions described as "above" another structure or portion are now "under" another structure or portion. Likewise, if the devices shown in the figures rotate about an axis, what is described as "above" the structure or portion is "next to" or "to the left" of another structure or portion. The same numbers represent the same components.

It will be further understood that terms such as " comprising, "" including," "having, " Is used.

A light emitting device according to embodiments disclosed herein may include a light emitting diode (LED) or laser that may be fabricated on a Group III-V nitride (e.g., gallium nitride (GaN)) based growth substrate. By way of example, the growth substrate may be manufactured by Cree, Inc. (SiC) substrate, such as a device manufactured and sold by Durham, North Carolina. As an example, other growth substrates such as sapphire, silicon (Si) and GaN can also be considered in the present invention. In one aspect, the SiC substrate / layer may be a 4H polytype silicon carbide substrate / layer. However, other SiC candidate polytypes may be 3C, 6H and 15R polytypes. Suitable SiC substrates are available from Cree, Inc., of Durham, N.C., the inventors of the present invention, and the method of making such substrates is not limited to the scientific literature, Patent No. Re. 34,861; U.S.A. Patent No. 4,946,547; and U.S. Patent No. 5,200,022, which is incorporated herein by reference in its entirety. Any other suitable growth substrate is contemplated by the present invention.

The term "group III nitride" as used herein refers to a semiconductor compound formed between nitrogen and at least one element belonging to group III of the periodic table, generally aluminum (Al) gallium (Ga), and indium (In). The term also refers to compounds of two elements, three elements and four elements, such as GaN, AlGaN and AlInGaN. Group III elements may be combined with nitrogen in the form of a binary element (e.g., GaN), a ternary element (e.g., AlGaN), or a quaternary element (e.g., AlInGaN) compound. Such a compound may have empirical formulas in which one mole of nitrogen is combined with one mole of the entire group III element. Therefore, empirical equations such as Al X Ga- 1-X N (0 < x < 1) are used to illustrate these compounds. Techniques for epitaxial growth of Group III nitrides have been well developed and reported in the appropriate scientific literature.

Although the various embodiments of the LED disclosed herein include a growth substrate, it will be understood by those of ordinary skill in the art as crystalline epitaxial growth substrates. The crystalline epitaxial growth substrate on which the epitaxial layer comprising the LED is grown can be removed and the separate epitaxial layer can have different thermal, electrical, structural and / or optical properties than the alternative carrier substrate or conventional substrate. Lt; / RTI &gt; substrate. The subject matter disclosed in the present invention is not limited to a structure having a crystalline epitaxial growth substrate, and an epitaxially grown substrate may be removed from an existing growth substrate and used in association with a structure bonded to an alternative carrier substrate.

For example, Group III nitride-based LEDs according to any embodiment of the subject matter of the present invention may be mounted on horizontal devices (having at least two electrical contacts on the same side of the LED) or vertical devices (E. G., A Si, SiC or sapphire substrate) to provide a substrate (e. G., Having electrical contacts). Further, the growth substrate can be retained or removed (e.g., by etching, grinding, polishing) on the LEDs produced. For example, the growth substrate may be removed to reduce the thickness of the resulting LED and / or to reduce the forward voltage through the vertical LED. For example, a horizontal device (with or without growth substrate) may be connected to a carrier substrate or printed circuit board (PCB) with a flip chip (e.g., using solder) or wire. The vertical device (with or without growth substrate) may have a first terrminal solder connected to a carrier substrate, a mounting area or a PCB and may be connected to a second terminal wire (not shown) connected to the carrier substrate, second terminal wire). Examples of vertical and horizontal LED chip structures are described in U.S. Publication No. 2008/0258130 to Bergmann et al. And U.S. Publication No. 2006/0186418 to Edmond et al. The disclosure of which is incorporated herein by reference in its entirety.

 More specifically, the one or more LED chips may be at least partially coated with one or more phosphors. The phosphorescent material can absorb a portion of the LED light and emit at other wavelengths of light. That is, the light emitting device or package emits a combination of light from each LED and phosphor. In one embodiment, the emitter device or package emits what is perceived as white light resulting from the combination of the LED chip and the light emission from the phosphor. One or more LEDs can be coated and fabricated by many different methods, one suitable method is disclosed in U.S. Patent Application Nos. 11 / 656,759, entitled " Wafer Level Phosphor Coating Method & 11 / 900,790, the entirety of which is incorporated herein by reference. Another suitable method of coating one or more LEDs is described in U.S. Patent Application No. 12 / 014,404, entitled " Phosphor Coating System, Packaged Light Emitting Diode Including Phosphor Coatings and Methods for Light Emitting Structures " ), United States Patent Application No. 12 / 717,048, entitled " System and Method for Application of Optical Materials to Optical Elements, " the disclosure of which is incorporated herein by reference in its entirety. The LED may also be coated using other methods such as electrophoretic deposition (EPD). A suitable EPD method is disclosed in U. S. Patent Application Serial No. 11 / 473,089 entitled " Near-Loop Electrophoretic Deposition of Semiconductor Devices ", the disclosure of which is incorporated herein by reference in its entirety. It is understood that the light emitting device and method according to the present invention can have a plurality of LEDs of one or more different colors which can be white light emission.

Referring to the various figures of the drawings showing embodiments of the light emitting device and method, Figures 1 to 5 illustrate one configuration or embodiment of an LED, package or device, generally designated as 10, according to the present invention . 6A-8 illustrate various embodiments of an LED chip that may be included in the novel light emitting package and apparatus disclosed herein. In particular, the devices and chips disclosed in the present invention can be numerically reduced and improved in various numerical aspects to provide improved light output with regard to the numerical aspects of the device and to obtain the best possible performance. Such an improvement is not predicted in the light of an existing apparatus, which is merely arbitrarily smaller in size and chosen and / or reduced in size of the radiator, without considering the improved ratio and / or size characteristics. Indeed, rather than realizing that the reduction and variation of the numerical aspects of existing larger packages or devices, such as the inventive subject matter disclosed herein, is in agreement with or surpasses the light output performance of a surprisingly larger package or device, The reduced light emitting package or device inevitably has reduced brightness or light output. By way of example, the light-emitting device described herein may be operated to emit light of about 100 lumens or more, 100-150 lumens, 150-200 lumens, or 200 lumens or more in its sub-range. In one aspect, a light emitting device according to the present invention is capable of emitting light having an output of greater than 110 lumens per watt when a current of 350 mA is driven. In one aspect, the devices disclosed herein can be operated at currents up to 1A. By way of example, this luminous efficacy can be under the condition of 25 캜 (77 ℉).

Referring to FIG. 1, a light emitting device designated generally at 10 is shown. The light emitting device 10 includes various features disposed under the lens 30. [ In Fig. 1, the lens 30 appears as a dotted line. The lens 30 may be optically opaque as shown in Fig. The dotted line in Figure 1 is for illustrative purposes only and represents the arrangement of the lens 30 in relation to features that may be placed under the lens 30. [ These features may not be visible below the opaque lens 30 (e.g., see FIG. 2). 1 to 4, the light emitting device 10 may include at least one solid state emitter or a light emitting device such as an LED chip 12. The light emitting device may be disposed or arranged on the chip in the present invention or may be die attached to the area 14 referred to as a mounting area. The mounting region 14 may include patterned conductive features to provide current to the LED chip as well as to provide lateral heat spreading. Since the LED chip may be any suitable shape or configuration, such as, for example, FIGS. 6A-8 showing the features and / or embodiments of the LED chip 12, the LED chip 12 shown in FIG. It is for illustrative purposes only.

In one aspect, the LED chip 12 may include any of the embodiments depicted by Figures 6A-8 of the present invention. The mounting region 14 may comprise any suitable conductive material known in the art. For example, a metal or metal alloy, copper (Cu), aluminum (Al), tin (Sn), silver (Ag), a conductive polymer material, and / or combinations thereof. The mounting region 14 may be electrically and / or thermally separated from or formed integrally with the electrical components of the light emitting device 10. By way of example, the electrical components may each include a first electrical contact area or element 16 and a second electrical contact area or element 18. By way of example and not limitation, the first electrical component 16 and the second electrical component 18 may comprise any suitable electrically conductive material known in the art. For example, a metal or metal alloy, copper (Cu), aluminum (Al), tin (Sn), silver (Ag), a conductive polymer material, and / or combinations thereof.

In one aspect, the mounting area 14, the first electrical component 16, and the second electrical component 18 may comprise copper (Cu) deposited using well known techniques such as plating. In one aspect, a titanium (Ti) adhesive layer and a copper seed layer can be sequentially sputtered onto the submount 22. Thereafter, approximately 75 mu m of copper (Cu) may be plated on the copper seed layer. The resulting deposited copper layer may then be patterned using a standard lithographic process. In another embodiment, the copper layer may be sputtered using a mask to form the desired pattern of devices 16 and 18. [ The mask can be used to form the gap G by preventing the deposition of copper in that area. In some aspects, the mounting area 14, elements 16 and 18 may be used to create a more suitable mounting area 14 for mounting the LED chip 12 and / or to improve optical properties such as the amount of light emitted May be plated or coated with additional metals or materials. As an example, the mounting region 14, elements 16 and 18 may be plated with an adhesive material, a bonding material, a reflective material, and / or a barrier material or layer. In one aspect, the mounting region 14 and elements 16 and 18 are formed by a reflective (Ag) layer disposed over the nickel (Ni) barrier layer and the nickel (Ni) barrier layer to increase reflection from the device 10. [ And can be plated to any suitable thickness.

1 to 4, the mounting area 14, the first electrical component 16 and the second electrical component 18 are disposed on the top surface 20 of the substrate or submount 22 and / Or attached. In one aspect, the mounting region 14 may be formed integrally with and / or with the first and / or second electrical component 16 or 18. The first electrical element 16 and the second electrical element 18 can be physically separated and can be electrically and / or thermally isolated from each other by a gap G. [ Although only one LED chip 12 is shown for illustrative purposes, a number of LED chips 12 with similar or different light wavelengths are also contemplated. The gap G can extend down to the top surface 20 of the submount 22 to electrically and thermally isolate the first and second electrical components 16 and 18 from each other. In one aspect, the gap G may provide electrical insulation between the first and second electrical components 16 and 18 to prevent shorting of the electrical signal applied to the LED chip 12.

The mounting region 14 and the electric elements 16 and 18 are arranged such that the heat from the LED chip 12 goes beyond the area immediately below the LED chip 12 to the submount 22 to be diffused into other regions of the thermal conductive path. By way of example, the mounting area 14 may cover more surface area of the top surface 20 of the submount 22 than the area covered by the LED chip 12. Mounting region 14 may extend to or near the edge of submount 22. In the illustrated embodiment, the mounting region 14 is generally circular and extends radially from the LED chip 12. [ It is understood that the mounting region 14 may include any suitable shape and / or size and may extend in contact with the edge of the submount 22 in any embodiment.

In general, the LED chip 12 disclosed in the present invention may be used alone or in combination with one or more phosphors or lumiphor to emit light in various colors, color points, or wavelength ranges. Emitters can be included. (1) a predominantly blue wavelength (preferably about 430 to 480 nm; alternatively any suitable subrange of 430 to 475 nm, 440 to 475 nm, 450 to 475 nm, or 430 to 480 nm); (2) mainly a cyan wavelength (preferably about 481 nm to 499 nm); (3) a green wavelength (preferably any suitable sub-range of about 500 nm to 570 nm, alternatively 505 nm to 515 nm, 515 nm to 527 nm, 527 nm to 535 nm, or 535 nm to 570 nm, or 500 nm to 570 nm); (4) mainly yellow wavelength (preferably about 571590 nm); (5) a wavelength range of from 621 nm to 700 nm, from 600 nm to 700 nm, preferably from 621 nm to 750 nm, preferably including from about 591 nm to about 750 nm, an optional orange subrange (preferably from about 591 nm to about 620 nm) , 610 nm to 700 nm, 610 nm to 680 nm, 620 nm to 680 nm, 620 nm to 670 nm, and / or 591 nm to 750 nm.

In one aspect, the light emitting device 10 is mainly blue, or a yellow phosphor disposed on the LED chip 12 when emitting light (e.g., the phosphor is a lens 30 disposed on the LED chip 12) (LED chips 12, such as BSY (blue shifted yellow)) that can activate LED chips 12 (which may, for example, be located at least partially above LED chip 12 and / or device 10). In another embodiment, a red LED chip 12 may be disposed and included below the phosphor, encapsulant, and / or lens 30, in order to mix and produce a warm white output. The light emitting device 10 may also include an LED chip 12 and / or an LED chip 12 configured to activate a red phosphor disposed on a portion of the device 10. By way of example, the red phosphors may be disposed on or within a portion of the lens 30 to produce a warm white output. In yet another embodiment, the device 10 may include one or more LED chips 12, such as a plurality of LED chips. The plurality of LED chips 12 may include substantially the same wavelength (e.g., a wavelength selected from the same target wavelength bin), or at least a first LED chip among the plurality of LED chips 12 may include at least a plurality of LED chips 12 2 LED chips and other wavelengths. That is, at least the first LED chip can be selected from the second LED chip and a different wavelength target bin. As described above, one or more LED chips 12 may be provided within the device 10 and may include one or more color points or combinations of wavelengths. For example, one or more LED chips 12 may emit primarily blue, green, red, yellow, cyan, yellow wavelengths, and combinations thereof.

In one embodiment, the LED chip 12 may include, for example and without limitation, conventional solder materials, which may or may not include conventional flow materials, and may be made of thermally- It is also possible to use polymeric materials, preform attachments, flow or no-flux eutectic attachments, silicone epoxy attachments, metal epoxy attachments, thermal compression attachments ), And / or any combination thereof, as will be apparent to those skilled in the art. The LED chip 12 may include other semiconductor layers arranged in different ways. LED structures and their fabrication and operation are generally well known in the art and are discussed briefly herein.

The LED chip 12 may include electrical contacts (e.g., an anode and a cathode) on one or more surfaces of the chip 12. In one aspect, the LED chip 12 may be vertically structured. That is, the first electrical contact is on the first surface and the second electrical contact is on the second surface of the LED chip 12 opposite the first surface. In this case, a wire bond (not shown) may be used to electrically connect the LED chip 12 to each of the first and / or second electric elements 16, 18. In another aspect, the LED chip 12 may include a horizontally structured device having two electrical contacts (e.g., an anode and a cathode) on the same surface, such as a floor surface. In this regard, a wire bond (not shown) may not be needed since the contacts are electrically connected to the first and second electrical elements 16,18 through the die attach method / material. The LED chip 12 of FIG. 1 may include a horizontally structured device having both electrical contacts on the bottom side. The bottom surface can be connected to the first and second elements 16, 18 using a die attach material. In one embodiment, the material may be a solder, epoxy or flux material. In this regard, the LED chip 12 may be disposed at least over an interval G where the cathode and anode are electrically isolated.

1 to 4, the emitter device 10 may further optionally include a surface electrical contact 15. In one aspect, the surface electrical contact 15 may be arranged to be electrically connected to the first and second electrical elements 16,18. 2, the surface electrical contact 15 may be attached to the contact 15 via soldering or any other attachment method to electrically connect the external component (not shown) to the emitter device 10 The protective layer 31 may be formed of a metal. The surface electrical contact 15 may optionally comprise any suitable electrically conductive material well known in the art. For example, the material may be a metal, a metal alloy, copper, silver, tin, electrically conductive ceramics, and / or a polymeric material. The surface electrical contact 15 receives the external electrical component (not shown, e. G., An electrical wire), crimps, clamps, or otherwise holds the body holding the electrical component .

Referring to Figures 1-5, the submount 22 may comprise any suitable material and may be electrically and / or thermally conductive or nonconductive. In one aspect, the sub-mount 22 is LTCC (low temperature co-fired ceramic), HTCC (high temperature co-fired ceramic), aluminum nitride (AlN), aluminum oxide (Al 2 O 3), glass, and / or And may include a ceramic material such as an aluminum panel material. In another aspect, the submount 22 may comprise a plastic material such as polyimide (PI), polyamide (PA), polyphthalamide (PPA), liquid crystal polymer (LCP), or silicone. In another embodiment, the submount 22 may be a printed circuit board (PCB) and its variants, sapphire, silicon, or any other suitable material, a T-Clad thermal clad insulator substrate available from The Bergquist Company of Chanhassen, Materials. As an embodiment of the PCB and variations thereof, the other PCB types may be standard FR-4 PCB, metal core PCB (MCPCB), or other available PCB types. In various aspects, it may be desirable to choose a submount 22 that includes a good electrical insulator material (e.g., AlN) that has low thermal resistance or high thermal conductivity.

Any material that may be used as the submount 22 may be a material having a thermal conductivity of at least about 30 W / m 占 과, such as zinc oxide (ZnO). Another possible material may be a material having a thermal conductivity of at least about 120 W / m · k, such as aluminum nitride (AlN) having a thermal conductivity in the range of 140 W / m · k to 180 W / m · k. In terms of thermal resistance, any possible submount 22 material may have a thermal resistance of 2 ° C / W or less. Other materials having thermal properties outside the ranges disclosed herein may also be used as the submount 22. In particular, as disclosed herein, the various sizes of the submount 22 can be reduced, for example, with respect to the size of the LED chip 12 and / or the different sizes of the various lens 30 sizes, An improved ratio can be obtained to obtain increased light output and optical efficiency in the package or device.

In one aspect, the plurality of light emitting devices 10 can be formed from a single large sub-mount panel, where the individual devices can be singulated from a large panel. The individual devices can be individually diced, sawed, cut, braked, or any other suitable method to provide a method for individualizing the individual device submount 22 from a large submount panel Lt; / RTI &gt; Under singulation, the submount 22 may be of any size and / or shape, e.g., mainly square, rectangular, circular, oval, regular, irregular or asymmetric. In one aspect, as shown in FIG. 3A, the submount 22 may include a rectangular shape having a first width SW1 of the first surface and a second width SW2 of the second surface. In one aspect, the first surface SW1 may include a width of about 2.5 mm or less in at least one direction. In another aspect, SW1 may be the same size as SW2. That is, the size is the same in at least two directions. By way of example, each of the surfaces SW1 and SW2 may comprise the same width of at least about 2.5 mm in at least two optional orthogonal directions that have a surface area of about 6.25 mm &lt; 2 &gt;. By way of example, in one aspect, the submount 22 may include squares in which each surface SW1 and SW2, having a surface area of 6 mm 2 or less, may be about 2.45 mm or less. By way of example, a submount 22 having one or more surface widths SW1 and / or SW2 with a smaller surface and / or surface area of about 2 mm or less (e.g., 1.5 mm, 1.0 mm, 0.5 mm or less) And the various dimensions of the device package, e.g., the ratio of the lens to the submount, can be improved to maximize light output from the smaller package.

1 to 4, the light emitting device 10 may further include a lens 30. The lens 30 may be formed on the top surface 20 of the submount 22 and may be disposed on at least one LED chip 12. The lens 30 may provide environmental and / or mechanical protection of the device 10. The lens 30 may be disposed at another location on the top surface 20 of the submount 22. For example, as shown in one aspect, the lens 30 may be positioned so that the LED chip 12 is located at least approximately below the center of the maximum height of the lens 30. [ The lens 30 may include a protective layer 31 that may extend the same as the face of the device 10 to cover a portion of the device 10, such as a corner of the device. The protective layer 31 is at least partially flat or horizontal to the portion of the lens 30. In one aspect, the lens 30 and the protective layer 31 may comprise the same material. In one aspect, the lens 30 and the protective layer may be formed using other molding techniques and may include any suitable material compatible with the molding process. In one aspect, the lens 30 and the protective layer 31 may comprise, for example, silicon, plastic, epoxy, or a combination thereof. In one aspect, silicon is suitable for molding and provides adequate optical transmission characteristics. It can withstand subsequent reflow processes and does not degrade significantly over time.

As is well known in the art, a mold (not shown) comprising a cavity may be formed by a large submount panel (e.g., a large panel as disclosed before singulation) such that each cavity is arranged on at least one LED chip 12. [ ). &Lt; / RTI &gt; Lens material and / or a liquid encapsulant may be provided to the mold to fill the cavity surrounding the LED chip 12. In one aspect, the lens 30 may comprise liquid curable silicone. The LED chips 12 may each be embedded in liquid silicon in a single cavity. The liquid silicon can then be selectively cured through a known curing process. The mold can then be removed to provide a plurality of lenses that can be placed on each LED chip 12, such as the lens 30, depending on the shape of the given cavity. A light emitting device such as device 10 (including submount 22, LED chip 12, lens 30) may be customized from a large submount panel using any suitable individualization method. As an example, there is a method of dicing, sawing, cutting, breaking, as previously disclosed. The lens arrangement of the light emitting device 10 can also be easily adjusted for use with an auxiliary lens or optics that can be placed on the lens 30, such that the end user can facilitate beam formation. Such assist lenses are known in the art, and most are commercially available. The lens 30 may be optically transparent, colored, transmissive, semi-transparent, opaque and / or a combination thereof. The lens 30 may also be textured to enhance light output, or it may include an optional amount of additive material, such as one or more phosphors, diffusers, or amounts of light scattering particles.

3A and 3B illustrate various light emitting device 10 sizes that can provide unexpectedly advantageous performance with respect to maximized light output and light efficiency based on a smaller device size and that can achieve this. For example, the diameter D1 and / or radius R1 of the lens 30 may be improved with respect to the surfaces SW1 and SW2 and / or the surface area (e.g., the product of SW1 and SW2) of the submount 22 previously disclosed. . In one aspect, the diameter D1 and / or radius R1 of the lens 30 may be improved by minimizing the amount of edge exclusion E between the lens 30 and the submount 22 . Figure 3A shows a lens 30 whose diameter D1 does not extend coplanar with the side of the submount and Figure 3B shows that by expanding the diameter D1 of the lens 30 coplanar with the side of the submount, (E) between the lens and the edge of one or more submounts 22 is minimized. By way of example, in one aspect, the lens 30 may include a diameter D1 greater than about 2.0 mm with a radius R1 of about 1.0 mm or greater. By way of example, the diameter D1 may comprise at least about 2.172 mm with a radius R1 of about 1.086 mm or greater. The various subranges of the diameter D1 and radius R1 of the size of the lens 30 are considered. For example, the diameter may include a range of about 2.0 mm to about 2.5 mm or more, such as to include a width equal to the widths SW1 and SW2 of the submount and coplanar with the submount 22, for example.

Generally, as the diameter D1 increases, the edge margin E decreases. (E.g., the length or area between the base of the lens 30 and the edge of the submount 22) is about 0 mm and about 0.5 mm for at least one edge of the submount 22, mm. &lt; / RTI &gt; As an example, any subrange of the edge margin E may be considered to be 0 mm to 0.3 mm or 0.3 mm or more. 3B, the edge outline E can be substantially zero as the lens extends in all directions to at least one edge of the submount 22. In other words, In another aspect, as the lens 30 extends in all directions to at least two or more different edges of the submount, the edge exclusion E at one or more edges of the submount 22 may be approximately 0 mm. In another aspect, the edge extensions E can extend to each edge of the submount 22. That is, the device 10 has an edge exclusion with all edges of the submount 22 of approximately 0 mm. Particularly, as shown in Fig. 3B, the surface electrical contact 15 can optionally be implemented in the device 10, even if the edge eccentricity E is approximately 0 mm.

In one aspect, the size of the lens 30 can be improved with respect to the size or dimension of the submount 22. [ For example, the ratio of the width of the lens 30 (e.g., the diameter D1 of the lens) to the width of the submount 22 (e.g., SW1 and SW2) may be 0.85 or greater. In one aspect, this ratio can be improved by maximizing the lens / substrate width ratio as minimizing the edge outline E to obtain the largest possible lens. In one aspect, the width of the lens 30 relative to the width of the submount 22 may be a ratio of about 0.887. This increase in the ratio can significantly improve the light output and efficiency of the device 10 to maintain and / or exceed a brightness level of about 100 lumens or more as the device is numerically smaller. In one aspect, the ratio of the width or diameter D1 of lens 30 to the width of SW1 or SW2 may comprise any subranges from about 0.85 to 1. [ By way of example, the subranges range from 0.85 to 0.87; 0.87 to 0.9; 0.9 to 0.92; 0.92 to 0.95; 0.95 to 0.98; And 0.98 to 1. The ratio of the area of the lens 30 to the area of the submount 22 (e.g., the product of SW1 and SW2) can be improved to increase the light output. The improvement may include improving the ratio of the area of the lens 30 to the area of the submount 22 to about 0.60 or more. In one aspect, the area of the lens 30 and the area of the submount 22 may comprise a ratio of about 0.617. As a subrange of the area of the lens 30 and the area of the submount 22, 0.60 to 0.61; 0.61 to 0.62; 0.62 to 0.63; 0.63 to 0.65; 0.65 or more can be considered.

As shown in FIG. 3B, the light emitting device 10 disclosed herein may further include a component for protecting from damage by one or more ESD (electrostatic discharge). Other components may include various vertical silicon (Si) zener diodes, other parallel LEDs, reverse biased LED chips 12, surface mounted varistors and lateral Si diodes. The arrangement of the LED chips 12 and the EDS protection device 32 allow the excess voltage and / or current passing from the EDS through the light emitting device 10 to pass through the protection device 32 instead of the LED chip 12, (12) can be protected from damage. In the illustrated embodiment, the vertically structured ESD protection device 32 may be mounted on, and utilized over, the mounting region 14 using known mounting techniques. The EDS protection device 32 can be reverse biased with respect to the LED chip 12 and electrically connected to the second electrical element via the wire bond 34. [ The ESD protection device 32 may be relatively small compared to the LED chip 12. [ That is, the ESD protection device 32 does not cover the excess area of the mounting area 14 and / or the surface of the submount 22, and therefore does not block a huge amount of light emitted from the LED chip 12. [ The ESD protection device 32 may also be located proximate the edge of the lens 30 so as not to block light at the center of the device 10. [ In some aspects, the light emitting device disclosed herein may be provided without an EDS protection device 32, or alternatively the EDS protection device 32 may be located external to the light emitting device.

FIGS. 3A and 3B may include at least one symbol or mark designated by 36. FIG. The indicia 36 can indicate the electrical polarity of the device 10 and can ensure correct installation of the light emitting device 10 to a PCB, drive circuit, power circuit, or other external substrate or current source. 5) may be in electrical communication with the first electrical component 16 and may be configured to electrically connect the current through the LED chip 12 of the device 10 Can be installed on the positive side of the electrical power source for the key. As shown, the indicia 36 includes a positive (+) sign formed in the first electrical element 16, the positive sign indicates that a positive current flows into the first surface mount area 38, and And then through the electrically conductive path or via, generally designated 44, to the first electrical element 16 and finally to the LED chip 12 (Figure 5).

The negative current flowing from the LED chip 12 flows into the second surface mounting area 40 (see Figs. 3A to 4) conducted by the second electric element 18 and then the conductive via 44 . The second electrical element 18 can be electrically communicated and / or electrically coupled to the second surface mount region 40 (see FIG. 5). That is, current may flow out of device 10 and flow to an external substrate such as a PCB, a power supply, a drive circuit, or other substrate or current source. At least one alignment mark, generally designated 42, may also be present on the device 10 to ensure that the mask of the deposition, etching, and / or plating process of, for example, electrical components 16, 18 is correctly aligned May include a label used. The indicia 36 and the indicia 42 may include many different symbol, shape, and / or indicator formats. A symbol or indicator 36 may also be included on the second battery element 18. The symbol or indicator may also be located at other locations than above the electrical elements 16,18.

Fig. 4 is a side view of the device 10. Fig. As described above, the dimensions and / or the ratio of the lens 30 and the submount 22 on various sides can be reduced and improved in order to significantly increase the light output. In one aspect, the lens diameter D1 and / or radius R1 may be reduced by minimizing the edge exclusion E, in relation to the reduction of the width SW1 and / or SW2 of the submount (see Figures 3A and 3B) And can be improved. As shown in FIG. 4, the device 10 may include an overall package height H1. By way of example, the height H1 may be about 1.85 mm or less. In one aspect, H1 may be about 1.84 mm. In another aspect, height 9H1) is less than 1.0 mm; 1.0 mm to 1.2 mm; 1.2 mm to 1.4 mm; 1.4 mm to 1.6 mm; 1.6 mm to 1.8 mm; And may include various subranges including greater than 1.8 mm. The device 10 may include a base thickness T1 that includes the thickness of the submount 22, the surface mount area 38 and the protection area 31. [ By way of example, the base thickness T1 may be about 0.8 mm or less, such as 0.76 mm. Thickness T1 is less than 0.5 mm; 0.5 mm to 0.6 mm; 0.6 mm to 0.7 mm; And 0.7 mm to 0.8 mm. The device 10 may further include a submount thickness T2 of about 0.65 mm or less. The submount thickness T2 may include the thickness of the surface mount region 38, the submount 22, and the electrical component 16. [ The thickness T2 is less than about 0.4 mm; 0.4 mm to 0.5 mm; 0.5 mm to 0.6 mm; And may include various subranges including 0.6 mm to 0.65 mm. The lens 30 may comprise any suitable cross-sectional shape depending on the desired shape of the light output. By way of example, one suitable cross-sectional shape, as shown, may be hemispherical and, as another example, may be oval, bullet-like, planar, hexagonal, and square. The lens 30 may include vertices or points of maximum height centered on the center of the submount 22 as shown. Or the vertex may be located off center relative to the submount 22. The lens 30 may also include one or more vertices at the same height.

5 is a bottom view of the apparatus 10. Fig. The device 10 may further include surface mount regions 38, 40 for electrically connecting to an external power supply or circuit (not shown). The surface mount regions 38, 40 may be arranged essentially vertically below each of the first and second electrical elements 16, 18. The external power source (not shown) may apply a current or a signal to the device 10 through communication of the signal when the device is mounted on the external power source. For example, the first and second surface mount regions 38, 40 electrically communicate with solder contacts or other conductive paths on an external power source (not shown) and provide electrical current to the first and second electrical components 16 18 may each pass current through a conductive path internally disposed within the submount 22 in turn. The external power supply may include a PCB, a MCPCB, a drive circuit, a power supply, or any other suitable external current source capable of applying current to the surface mount regions 38, 40. The light emitting device 10 may be arranged for mounting to an external substrate or power source using surface mount technology and the device 10 may be mounted on the surface mount areas 38 and 40 and the electrical components 16 , 18), respectively, of the inner conductive path. The internal electrically conductive path may include one or more conductive, typically designated 44, vias.

The one or more conductive vias 44 are configured to electrically connect the first surface mounting area 38 and the first electrical mounting area 38 to conduct electrical current to the first electrical component 16 through the submount when a current or signal is applied to the first mounting area 38. [ And extend through the submount 22 between the elements 16. Likewise, one or more conductive vias 44 may be stretched to conduct electrical signals between the second surface mount region 40 and the second electrical element 18. The first and second surface mount areas 38 and 40 are configured to enable surface mounting of the device 10 in which an electrical signal is applied to the LED chip 12 across the first and second mounting areas 38 and 40 can do. The conductive vias 44 and surface mount regions 38 and 40 may comprise any suitably electrically conductive material and may be provided to provide mounting regions 14 and first and second electrical elements 16 and 18, May be provided using any suitable technique including those used for &lt; / RTI &gt; The surface mount regions 38,40 and the conductive vias 44 may be arranged in a variety of different forms and may include any suitable shape and / or size. The conductive vias 44 connect the electrical components 16 and 18 to the surface mount areas 38 and 40, respectively, and the electrical components can be arranged in other arrangements than shown. The conductive vias 44, which may be arranged obliquely as well as vertically arranged in the submount, may be formed between the surface mount regions 38, 40 and the electrical elements 16, 18. Instead of the vias 44, one or more intermediate metal layers may be provided between one or more submount surfaces, between the surface mount regions and the electrical elements, or even between the surface mount regions and the electrical elements along the sides of the submount 22 have.

As shown in FIG. 5, the light emitting device 10 may further include a thermoelectric element 46 disposed on the bottom surface of the submount 22. The thermoelectric elements 46 may alternatively be disposed between the first and second mounting regions 38, In one aspect, the thermoelectric elements 46 may be disposed in a central portion of the submount 22 under one or more LED chips. The thermoelectric element 46 may comprise any thermally conductive material such as metal, metal alloy, tin (Sn), silver (Ag), copper (Cu), etc. and may be arranged at least partially . In one embodiment, the thermoelectric elements 46 are electrically connected to the first and second surface mount regions 38,40 as well as the electrical components 16,18 on the top surface 20 of the submount 22 Lt; / RTI &gt; Although the heat generated from the LED chip 12 can be diffused laterally over the top surface 20 of the submount 22 via the mounting area 14 and the electrical elements 16 and 18, Is transmitted to the sub-mount 22 around the chip 12 and immediately below. The thermoelectric element 46 can assist heat dissipation by diffusing heat to the thermoelectric element 46 which can more easily dissipate heat from the device. The heat can also be conducted to the first and second surface mount regions 38 and 40, which can emit heat from the top surface 20 of the submount 22 via vias 44, have. In the case of a device using surface mount technology, the thickness of the thermoelectric elements 46 and the first and second surface mount areas 38, 40 may be substantially the same so that the details are in contact with the sides of the PCB or the like. In order to improve the wettability of the solder and to ensure a stronger contact between the thermoelectric element 46 and the external heat sink, the thermoelectric element 46 can be extended a greater distance from the body of the device than the surface mount area. In other words, it can be considered that the thermoelectric elements 46 can be made thicker than the surface mount regions 38, 40.

6A-6C illustrate an embodiment of an LED chip 12 partially disposed at the top of each of the first and second electrical components 16,18 (see Fig. 1). In Fig. 1, the LED chip 12 is generally shown and is composed of one or more straight, angled surfaces. However, the LED chip 12 includes a beveled cut substrate, generally designated 50, and provides a chip with angled or beveled surfaces disposed between the top and bottom surfaces. Specifically, FIGS. 6A-6C illustrate embodiments in which the LED chips 12 are primarily square-shaped chips that the adjacent surfaces 52, 54 may include predominantly the same length. However, FIG. 8 shows an embodiment in which the substrate's adjacent surfaces 52, 54 of the LED chip 12 may include predominantly rectangular shaped chips of different lengths. In one aspect, the length of each of the adjacent sides 52, 54 can be at least about 1 mm in at least one direction. In another aspect, the length of each of the adjacent side surfaces 52, 54 may include not greater than about 0.85 mm in at least two directions, not greater than about 0.70 mm, 0.50 mm, 0.40 mm, and 0.30 mm. The LED chip 12 may include a thickness t of about 0.40 mm or less, such as about 0.34 mm or less. In one aspect, and as shown in FIG. 6B, the LED chip 12 has a thickness (t) of about 0.335 mm or about 0.15 mm to 0.17 mm; 0.17 mm to 0.2 mm; 0.2 mm to 0.25 mm; 0.25 mm to 0.30 mm; And a thickness (t) of 0.15 mm to 0.34 mm, such as 0.30 mm to 0.34 mm.

In one aspect, the LED chip 12 has a thickness of about 0.74 mm 2 (The product of the maximum length of the adjacent sides 52, 54). By way of example, the area may be 0.72 mm 2 or less. In another aspect, LED chip 12 may include various sub-range of about 0.25mm 2 to 0.72mm 2 surface area. By way of example, the subrange may range from about 0.25 mm 2 to about 0.31 mm 2 ; 0.31 mm 2 to 0.36 mm 2 ; 0.36 mm 2 to 0.43 mm 2 ; 0.43mm 2 to 0.49mm 2; 0.49 mm 2 to 0.56 mm 2 ; 0.56 mm 2 to 0.64 mm 2 ; And 0.64mm 2 to 0.72mm may be two days. In one aspect, the top 56 may include a smaller surface area than the bottom 58. One or more tapered or angled sides, such as adjacent surfaces 52, 54, may be disposed between the top and bottom edges 56, 58. At least one groove, such as an X-shaped groove 60, may be disposed at the top 56 of the LED chip 12. Multiple X-shaped grooves and other shaped grooves may also be provided. According to one aspect, the groove 60 can improve light output.

As shown in FIG. 6C, the LED chip 12 may include electrical contacts on the same surface. By way of example, the same surface may be bottom 58. The electrical contacts may collectively include an anode 62 and a cathode 64 that occupy at least about 90% of the active diode area. The anode 62 may be disposed at least partially over the first electrical element 16 (see FIG. 1) and electrically connected to the first electrical element 16. The cathode 64 may be disposed at least partially over the second battery element 18 (see FIG. 1) and electrically connected to the second electrical element 18. In one aspect, the spacing 66 may be less than about 75 占 퐉. When the LED chip 12 is die-attached to the mounting pads 14 extending from the electrical element 18, the spacing 66 is at least partially disposed over the spacing G of the device 10 .

In one aspect, the LED chip 12 may include a horizontally structured direct mount type chip that is not required to connect the chip to the light emitting component by wire bonding. That is, the LED chip 12 may include a horizontally structured device in which each electrical contact (e.g., anode and cathode) is disposed on the lower surface of the LED chip. A die attach LED chip 12 (e.g., LED chip) 12 using any suitable material and / or technique (e.g., solder attachment, preform attachment, flow or nonflow process attachment, silicon epoxy attachment, metal epoxy attachment, thermal compression attachment, and / Can electrically connect the LED chip 12 to the first and second electrical elements 16 and 18 directly without requiring a wire bond.

Figs. 7 and 8 show various dimensions of the LED chip substrate 50. Fig. Figure 7 shows various maximum dimensions for adjacent sides (52, 54) of the square chip. Fig. 8 shows the various maximum dimensions of rectangular chips with different lengths of adjacent sides 52 and 54. Fig. By way of example, the side surface 52 of the rectangular chip may be shorter than the side surface 54. 8 shows various dimensions of the thicknesses of the large and small sides 52, 54 of the LED chip substrate 50. In one aspect, adjacent sides 52 and 54 may include about 350 microns by 470 microns, and may include a thickness and height of about 175 microns. In another aspect, the substrate thickness 50 may have a height of about 290 m. In another aspect, the substrate thickness 50 may have a height of about 335 占 퐉. In one aspect, the top 56 may be a rectangle having a length and width of about 177 占 퐉 占 297 占 퐉. In another aspect, the top may be rectangular in length and width of about 44 占 퐉 x 164 占 퐉. The LED chip 12 may have a ratio of the maximum area of the side surfaces 52, 54 adjacent to the area of the top 56 to about 0.4 or less. It has been found that the light output can be improved as the ratio of the area of the top 56 to the maximum area of the sides 52, 54 is reduced.

In particular, the use of the selected LED chip 12 has been improved to significantly increase the light output efficiency. By way of example, in one aspect, the LED chip size (e.g., the length or width of the chip previously described with reference to FIGS. 6A-6C) versus the size of the lens 30 (e.g., (D1)) can be minimized to improve the light output efficiency. As an example, one way to minimize the ratio is to increase the size of the lens 30 and / or to increase the size of the LED chip 12 by reducing the edge margin E (see FIG. 3A, FIG. 4) . The smaller and smaller the light emitting device and package, the more important the use of smaller chips. However, the LED chip 12 selected for use may be reduced and improved in relation to the features of other devices described herein. This reduction and improvement can result in unpredictable results, and can be achieved simply without considering the size of the chip associated with other packages or device features such as lens kicks and / or selections based on the ratio of LED chip to lens conventionally Since we have relied on coupling small LED chips to smaller devices, the ratio between LED chip size and lens size is not expected to be taken into account. In one aspect described above, the LED chip 12 may have a length and width of about 0.85 mm or less. In one aspect described above, the lens 30 may have a lens size or diameter of about 2.172 mm or more (along the edge exclusion E). The ratio of the size of the chip to the lens size (the width of the LED chip to the diameter of the lens 30) is 0.391 or less and about 0.1 to 0.2; 0.2 to 0.3; 0.3 to 0.4; &lt; / RTI &gt; Minimizing the ratio between chip and lens size can improve light output efficiency.

The ratio of the width of the LED chip 12 to the width of the submount 22 (e.g., SW1 and / or SW2 shown in Figs. 3A and 3B) can also be reduced and significantly improved to significantly improve light output . In one aspect, it may be desirable to achieve the smallest possible ratio to improve light output. By way of example, in one aspect, the ratio of the width of the LED chip 12 (e.g., the maximum dimension of the sides 52, 54) to the width of the submount 22 may be less than or equal to about 0.35. As an example of any subrange in the ratio of about 0 to 0.35, 0 to 0.1; 0.1 to 0.2; 0.2 to 0.3; A range of more than 0.3 may be considered. By improving this ratio, the device 10 can be adjusted to achieve maximum performance with respect to the device footprint. The miniaturized device must maintain and / or exceed a brightness level that can be partially achieved by reducing and improving various package dimensions and / or ratios.

According to the subject matter disclosed herein through the various figures and the foregoing description, a smaller size light emitting device with a desired light output may be used in combination with any or all of the features disclosed above and any suitable combination or combination of one or more of the various May be provided with various feature combinations having features.

The embodiments shown in the drawings and described above are examples of a number of embodiments that can be derived within the scope of the appended claims. The novel light emitting device with improved light output and the method for its manufacture may comprise more forms than those specifically disclosed. Also, reduced and improved values, sizes, and / or ratios may be adjusted to suit any given size and / or shape of the light emitting device to provide the improved light output disclosed herein.

Claims (52)

A submount having an area of about 6 mm 2 or less;
A light emitting chip on the submount;
And a lens disposed on the light emitting chip and disposed on the submount,
A light emitting device emitting light of about 100 lumens or more. The method according to claim 1,
Wherein the submount has a width of about 2.5 mm or less in at least one direction. 3. The method of claim 2,
Wherein the submount has a width of about 2.5 mm or less in at least two directions. The method according to claim 1,
Wherein the submount has a thickness of about 0.7 mm or less. The method according to claim 1,
Wherein the light emitting chip has an area of about 0.72 mm &lt; 2 & gt ;. 6. The method of claim 5,
Wherein the light emitting chip has a width of about 0.85 mm in at least two directions. The method according to claim 1,
Wherein the light emitting chip has a thickness of about 0.34 mm or less. The method according to claim 1,
Wherein the lens has a radius of at least about 1.0 mm. The method according to claim 1,
Wherein the light emitting device has a height of about 1.85 mm or less. The method according to claim 1,
Wherein a ratio of a width of the light emitting chip to a width of the submount is about 0.35 or less. The method according to claim 1,
Wherein the ratio of the width of the lens to the width of the submount is about 0.85 or more. The method according to claim 1,
Wherein the ratio of the area of the lens to the area of the submount is about 0.63 or more. The method according to claim 1,
Wherein a ratio of a width of the light emitting chip to a width of the lens is about 0.4 or less. The method according to claim 1,
Wherein the light emitting device has an edge exclusion of between about 0 mm and less than 0.3 mm between the lens and the edge of the submount. 15. The method of claim 14,
Wherein the light emitting device has an edge exclusion portion of zero extending to at least one edge of the submount. 16. The method of claim 15,
Wherein the light emitting device has an edge exclusion of 0 at one or more edges of the submount, the lens extending to at least two or more different edges of the submount. 17. The method of claim 16,
Wherein the light emitting device has an edge exclusion portion of 0 at all edges of the submount, the lens extending to all the edges of the submount. The method according to claim 1,
Wherein the light emitting device further comprises a surface electrical contact. A submount having an area of about 6 mm 2 or less;
An emitting chip having an area of about 0.72 mm 2 or less on the submount;
And a lens disposed on the light emitting chip and disposed on the submount,
And an edge exclusion of between about 0 mm and less than 0.3 mm between the edge of the lens and the submount. 20. The method of claim 19,
Wherein the light emitting device emits light of about 100 lumens or more. 20. The method of claim 19,
Wherein the submount has a width of about 2.5 mm or less in at least one direction. 20. The method of claim 19,
Wherein the submount has a width of about 2.5 mm or less in at least two directions. 20. The method of claim 19,
Wherein the submount has a thickness of about 0.7 mm or less. 20. The method of claim 19,
Wherein the light emitting chip has a width of about 0.85 mm or less in at least two directions. 20. The method of claim 19,
Wherein the light emitting chip has a thickness of about 0.34 mm or less. 20. The method of claim 19,
Wherein the lens has a radius of at least about 1.0 mm. 20. The method of claim 19,
Wherein the light emitting device has a height of about 1.85 mm or less. 20. The method of claim 19,
Wherein the light emitting device has an edge exclusion portion of 0 so that the lens completely extends to at least one edge of the submount. 29. The method of claim 28,
Wherein the light emitting device has an edge exclusion of 0 at one or more edges of the submount, the lens extending to at least two or more different edges of the submount. 30. The method of claim 29,
Wherein the light emitting device has an edge exclusion portion of 0 at all edges of the submount, the lens extending to all the edges of the submount. 20. The method of claim 19,
Wherein the light emitting device further comprises a surface electrical contact. A submount having an area of about 6 mm 2 or less;
A light emitting chip on the submount;
And a lens disposed on the light emitting chip and disposed on the submount,
The ratio of the width of the light emitting chip to the width of the submount is about 0.35 or less;
The ratio of the width of the lens to the width of the submount is about 0.85 or greater;
The ratio of the area of the lens to the area of the submount is at least about 0.63; And
And a ratio of a width of the light emitting chip to a width of the lens is about 0.4 or less. 33. The method of claim 32,
Wherein the light emitting device emits light of about 100 lumens or more. 33. The method of claim 32,
Wherein the light emitting device further comprises a surface electrical contact. A submount having an area of about 6 mm 2 or less;
A light emitting chip on the submount; And
A lens disposed on the light emitting chip, the lens being disposed on the submount; And
And emitting light from a light emitting device having an optical output of at least about 100 lumens. 36. The method of claim 35,
Said submount providing light from a light emitting device having a width of at least about 2.5 mm in at least one direction. 37. The method of claim 36,
Said submount providing light from a light emitting device having a width of at least about 2.5 mm in at least two directions. 36. The method of claim 35,
Said submount providing light from a light emitting device having a thickness of about 0.7 mm or less. 36. The method of claim 35,
Wherein the light emitting chip has an area of about 0.72 mm or less. 40. The method of claim 39,
Wherein the light emitting chip has a width of about 0.85 mm or less. 36. The method of claim 35,
Wherein the light emitting chip has a thickness of about 0.34 mm or less. 36. The method of claim 35,
Wherein the lens has a radius of at least about 1.0 mm. 36. The method of claim 35,
Wherein the light emitting device has a height of about 1.85 mm or less. 36. The method of claim 35,
Wherein the ratio of the width of the light emitting chip to the width of the submount is about 0.35 or less. 36. The method of claim 35,
Wherein the ratio of the width of the lens to the width of the submount is greater than or equal to about 0.9. 36. The method of claim 35,
Wherein the ratio of the area of the lens to the area of the submount is greater than or equal to about 0.63. 36. The method of claim 35,
Wherein the ratio of the width of the light emitting chip to the width of the lens is about 0.4 or less. 36. The method of claim 35,
Wherein the light emitting device has an edge exclusion greater than about 0 mm and less than about 0.3 mm between the lens and the edge of the submount. 49. The method of claim 48,
Wherein the light emitting device provides light from a light emitting device in which the lens extends to at least one edge of the submount and has an edge exclusion of zero. 50. The method of claim 49,
The light emitting device providing light from a light emitting device wherein the lens extends to at least two or more different edges of the submount to have an edge exclusion of zero at one or more edges of the submount. 51. The method of claim 50,
Wherein the light emitting device provides light from a light emitting device in which the lens extends to all edges of the submount to have a zero edge exclusion at all edges of the submount. 36. The method of claim 35,
Said light emitting device providing light from a light emitting device having a surface electrical contact.
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US10008637B2 (en) 2018-06-26
CN103988324A (en) 2014-08-13

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