KR20140026308A - Apparatus and method for managing power in multi-core system - Google Patents

Abstract

An embodiment of the invention relates to a method for restarting one or more cores in a multi-core processor, which is a part of an electronic apparatus. The method comprises following steps. Wakeup sources are grouped in a plurality of computing domains. Interrupts related to the wakeup sources are received. A first computing domain to which the wakeup source belongs is acknowledged among the computing domains. The first computing domain is mapped to a first identifier among one or more states of a first core of the processor. The first core is set to enter one or more states, which is instructed by the first identifier, and the first core is restarted after the first core is set. [Reference numerals] (300) Computer domain table; (303) Default state table; (AA) Domain A~301; (BB) External interrupt sources; (CC) Key press event; (DD) Power key press event; (EE) Domain B~302; (FF) RTC alarm; (GG) PMIC event; (HH) DPRAM event; (II) Computing domain; (JJ) Core 0; (KK) Core 1; (LL) For computing domain A; (MM) SetFreq=minimum OPP, CPU frequency manager strategy initiated, feature domains restarted, non-boot CPUs disabled; (NN) For computing domain B; (OO) SetFreq=minimum OPP, CPU frequency manager strategy initiated, system devices restarted, non-boot CPUs disabled

Description

Apparatus and method for power management in a multi-core system {APPARATUS AND METHOD FOR MANAGING POWER IN MULTI-CORE SYSTEM}

The present invention relates to a power management apparatus and method in a multi-core system.

With the convergence of telecommunications and entertainment applications, mobile device manufacturers are faced with the challenge of reducing power consumption while providing better performance, ie providing better performance with less power. Power management is important in battery-powered systems because it helps save power when the system is inactive.

The system is placed in a 'sleep state' which is a low power consumption state when not in use. In this 'sleep state' the system does not perform any useful tasks for the user. For example, power can be saved by switching the display off when the system is inactive for a while.

Existing systems address effective power consumption by defining various processor states, called C-states and P-states. The C-state corresponds to a processor executing an instruction or being in an idle state. The P-state corresponds to a set of voltage and frequency state pairs. The operating system deploys CPUIDLE and CPUFREQ subsystems to save power. Depending on the workload, the CPUFREQ subsystem implementation lowers or raises the voltage and frequency of each core present in the system. In some situations, the power demand of the system can be further reduced by choosing to apply different C-states from core to core. Upon wakeup by interrupt, the CPUFREQ subsystem causes the system to transition to the appropriate C-state C0 with cores that are in a higher voltage and frequency state. The voltage and frequency of the cores can then be lowered based on the current workload of the system.

In battery powered portable systems, often most interrupts and their applications can be serviced to low voltage and frequency states to save power. In such a system, the techniques first bring the core into a higher P-state, and then down to a lower P-state that is more suitable for the system's current workload. For example, upon receipt of a wake up event, the device may leave the 'sleep state' and operate at a high performance point regardless of the demand placed on the device. The device can then be placed at an optimal performance point based on the requirements. However, the transition from a high performance point to an optimal performance point may be inefficient in some situations.

Likewise, upon receipt of a wake up event, the secondary core of the device is taken out of sleep state and may be placed in an optimal performance point or sleep state based on the requirements placed on the device. Likewise, this transition can also sometimes be inefficient. Thus, new and more efficient power management techniques are needed.

Embodiments of the present invention may provide an apparatus and method for intelligently using different cores to identify wake-up events and to save additional power consumption that results.

In addition, other embodiments of the present disclosure may provide an apparatus and a method for grouping wake-up sources into domains based on computing needs.

Accordingly, an embodiment of the present invention provides a method for saving power by preventing unnecessary wakeup of a core of a multicore device upon restart of a multicore device, the method comprising at least one wakeup source based on a computing requirement. Grouping into at least one computing domain, configuring at least one computing domain based on core IDs and P-state information, and receiving at least one computing domain based on information upon receipt of at least one interrupt of wake-up sources. Acquiring, and restarting the core to handle at least one interrupt.

In addition, an embodiment of the present invention provides a device that saves power by preventing unnecessary wakeup of a core of a multi-core device upon restart of the multi-core device, the device further comprising at least one processor, and an integrated circuit At least one memory having computer program code in circuitry, the at least one memory and computer program code causing the at least one processor to cause the device to group wake-up sources into at least one computing domain based on a computing requirement. Configure at least one computing domain based on core IDs and P-state information, obtain at least one computing domain based on information upon receipt of at least one interrupt of wake-up sources, and at least one Handle interrupts To restart the core to do so.

In addition, these and other aspects of embodiments of the invention will be more readily appreciated and understood when considered in conjunction with the following description and the annexed drawings. However, it is to be understood that the following description presents preferred embodiments and numerous specific details thereof, but is illustrative and not restrictive. Many modifications and variations can be made without departing from the spirit and scope of the embodiments of the invention, and embodiments of the invention include all such changes.

According to embodiments of the present invention, intelligently using different cores can identify wake-up events and save additional power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is illustrated in the accompanying drawings, wherein like reference numerals designate corresponding parts in the various figures. Embodiments of the present invention will be better understood from the following description with reference to the drawings.
1 is a diagram illustrating a device power state and switching according to the embodiments disclosed in the present invention.
2 is a diagram illustrating a sleep state and a corresponding wake-up source of a device according to embodiments of the present disclosure.
3 is a diagram illustrating a computing domain table and a default state table according to embodiments of the present invention.
4 is a flowchart illustrating a suspend flow according to embodiments disclosed in the present invention.
5 is a flowchart illustrating a wake up sequence according to embodiments of the present invention.
6 is a diagram illustrating a computing environment for implementing an application according to embodiments of the present disclosure.

Embodiments of the present invention and their various features and advantageous details will be more fully described with reference to the non-limiting embodiments shown in the accompanying drawings and described in detail in the following description. Description of well-known components and processing techniques will be omitted so as not to unnecessarily obscure embodiments of the present invention. The examples used herein are merely intended to facilitate understanding of the ways in which the embodiments of the present invention can be practiced and to enable those skilled in the art to practice the embodiments of the present invention. Therefore, the examples should not be construed as limiting the scope of the embodiments of the present invention.

Embodiments of the present invention may provide a method and system for intelligently using different cores and their operating states of a device to identify wake-up events and save power. Wakeup events may be grouped into domains based on computing needs. Each computing domain may then be mapped to one or more core IDs, processor performance states, and processor operating states using the computing domain table and / or default state table. When an interrupt is generated at the device, the computing domain and default state tables can be used to determine which cores are to be powered as well as the specific voltage and frequency level of the cores.

Referring now to the drawings, and more particularly to FIGS. 1 to 6, embodiments are shown wherein like reference numerals indicate corresponding features consistently throughout the figures.

1 is a state diagram of a battery powered device. The battery powered device may be a mobile phone, a personal digital assistant (PDA), and / or any other suitable type of device. 1 illustrates various power states of the device. In this example, the device has several modes, such as normal mode, low power mode, sleep mode and deep sleep mode. The device is switched to lower the power mode during a timeout event. The device returns to the normal state on any wake up event. In sleep mode, all cores of the device are powered off. In deep sleep mode, only RAM is powered on, but the CPU and other peripherals are shut down. If a wake up event occurs in sleep mode, the device is moved to normal mode. The number of other low power states available to the device depends on the type of device and the type of low power option that the hardware can provide. For example, the device will be in sleep mode when not in use, and then when the key is pressed on the device, the device moves to normal mode.

2 illustrates a sleep state and corresponding wakeup sources of a device according to embodiments disclosed herein. Different wake-up sources are shown for each of the plurality of low power states. In FIG. 2, wakeup sources in deep sleep mode are a subset of wakeup sources for sleep mode, and wakeup sources in sleep mode are a subset of wakeup sources for low power mode. For example, a wakeup source when the device is in deep sleep mode handles a real-time clock (RTC) alarm, an external interrupt source, a key press event, an interrupt request handler, and a PMIC that determines which source the interrupt comes from. Modem interrupts such as (Power Management Interrupt Controller) and incoming call.

3 illustrates an example of a computing domain table and a default state table in accordance with embodiments disclosed herein. The figure shows a computing domain table 300 that divides different wake up events into separate domains, such as domain A 301 and domain B 302. In some embodiments, the wake up events can be grouped into different domains based on computing power requirements associated with the events. The default state table 303 may be configured to map each domain defined in the domain table to core IDs and P-states associated with the cores. In some implementations, domain A 301 in computing domain table 300 can group wakeup events such as external interrupt sources, key press events, power key input events, and the like. Domain B 302 may group wake up events such as RTC alarms, PMIC events, DPRAM events, and the like.

In some implementations, according to the default state table 303, when any interrupts occur in the domain A, core 0 of the device is placed in a C0 operating state and a P5 processor performance state, while core 1 of the device Is placed in the C0 operating state and the P2 processor state. In that regard, the techniques described herein set the C-state and P-state of the CPUs when a particular wake-up event occurs based on the type of event. In some examples, the P-states for Core 0 and Core 1 may or may not be different due to design limitations of some chipsets.

The processor performance state (P-state) and the processor's operating state (C-state) result in the processor's ability to adjust power consumption by switching between different supported operating frequencies and voltages. The Advanced Configuration and Power Interface (ACPI) specification defines the CPU P-state power management state. The number of P-states is a processor characteristic. When properly configured according to the workload of the system, this feature provides power savings. Higher P-state numbers indicate slower processor speeds. At higher P-states, power consumption is lower. For example, the P3 state is higher than the P1 state. Processors in the P3 state will run slower and use less power than processors running in the P1 state. In order to operate in any P-state, the processor must be in a C0 operating state where the processor is running and not idle. This state is implementation dependent, but P0 is always the highest performance state, P1 through Pn are sequentially lower performance states, and the implementation specific limit of n is 16 or less. P0 has maximum power and frequency, P1 scales the voltage / frequency lower than P0, and Pn scales the voltage / frequency lower than P (n-1). The ACPI specification also defines the CPU C-state power management state. The operating state (C-state) of the CPU is the ability of an idle processor to turn off unused components to save power. When the processor runs in the C0 state, it is running. Processors running in any other C-state are children. Higher C-state numbers indicate deeper CPU sleep states. At higher C-states, more components are shut down to save power. Some components that are shut down include stopping the clock of the processor and stopping the interrupt. As the CPU power states (C0-C3), C0 is an operating state, and C1 (often known as Halt) is defined as a state in which the processor has not executed an instruction but can essentially return to its execution state immediately. All ACPI-component processors must support this power state. Some processors, such as the Pentium 4, also support enhanced C1 state (C1E or enhanced Holt state) for low power consumption, while C2 (often known as Stop-Clock) allows the processor to be in all software viewable state. But it may take longer to wake up. This processor state is optional and C3 (often known as sleep) is a state where the processor does not need to maintain cache coherent, but maintains a different state. Some processors have a change (deep sleep, deep sleep, etc.) for different C3 states that take longer to wake up the processor. This processor state is optional.

In some implementations, the device can be configured in computing domain A 301 in such a way that the device has the highest OPP (OPP) of CPU0 and allows all cores to operate. In computing domain B 302, the device has the lowest OPP of CPU0 and may cause some of the other cores to not work.

As mentioned, in some implementations, when the device receives certain wakeup events, it may be set to wake up in a sleep mode. In some implementations, wakeup events can be generated by external interrupt sources, RTC alarms, key press events, PMIC events, DPRAM events, and the like. For example, the device may be configured to wake up in sleep mode only when an RTC alarm event occurs.

4 is a flow diagram of a method 400 in accordance with embodiments disclosed herein. As shown, the method stores the current frequency of the CPU and the CPU sets the sleep frequency (SLEEP FREQ) as the default frequency (401). The method also sets a voltage for the CPU. The method then stores the state of one or more devices, which devices are suspended (402). The method then stops 403 non-booting CPUs and system devices. The method then establishes (404) wake-up sources. The method may then set the master CPU to pause or call CPU_Pause internally (405). Various operations in the method 400 may be performed in the order presented, in a different order, or simultaneously. Also, in some embodiments, some operations listed in FIG. 4 may be omitted.

5 is a flow diagram of a method 500 in accordance with embodiments disclosed herein. As shown, the method begins by receiving 501 a new wake up event. The method then wakes up 502 the master CPU (CPU 0-boot core). The method then obtains the computing domain to which the event belongs (eg, domain 301 or domain B 302) by using computing domain table 300 (503). The method also reads (504) the default state for the acquired computing domain by the default state table 303. The method then brings 505 the cores of the processor identified in the default state table 303 into respective states for those cores identified in the default state table 303. The method then restarts the required cores for the event and the other device will remain suspended (506). Finally, the method handles the event (507). The various operations of method 500 may be performed in the order presented, in another order, or concurrently. Also in some implementations, some of the operations listed in FIG. 5 may be omitted.

The additional power saved using the proposed method can be calculated as follows.

Energy = Ni * Nc * Pc * T

From here,

Ni = the number of times the selected interrupt is generated,

Nc = number of cores available in the device,

Pc = power consumed by each core running at the sleep frequency (performance) value,

T = time taken by the manager to respond to identify the correct frequency or number of online CPUs.

6 illustrates a computing environment implementing techniques in accordance with embodiments disclosed herein. As shown, the computing environment 600 includes a control unit 611 and an Arithmetic Logic Unit (ALU) 612, a memory 640, a storage 650, a plurality of networking devices 620, and a plurality of At least one processing unit 610 having input / output (I / O) devices 630. Processing unit 610 is responsible for processing algorithmic instructions. The processing unit 610 receives a command from the control unit 611 to perform the processing. In addition, all logical and arithmetic operations related to the execution of the instructions are calculated with the aid of the ALU 612.

The overall computing environment 600 may be comprised of multiple homogeneous and / or heterogeneous cores, multiple CPUs of different kinds, special media, and other accelerators. The processing unit 610 is responsible for processing the instructions of the algorithm. The processing unit 610 receives a command from the control unit 611 to perform the processing. In addition, all logical and arithmetic operations related to the execution of the instructions are calculated with the aid of the ALU 612. In addition, the plurality of processing units 610 may be located on a single chip or across multiple chips.

Algorithms of instructions and code required for implementation are stored in either or both of memory 640 or storage 650. In execution, the instructions may be fetched from the corresponding memory 640 and / or storage 650 and executed by the processing unit 610.

For any hardware implementation, various networking devices 620 or external I / O devices 630 may be connected to the computing environment to support the implementation through the networking unit and the I / O device unit.

Embodiments disclosed in the present invention may be implemented through at least one software program that is executed on at least one hardware device and performs a network management function to control an element. The element shown in FIG. 6 includes a block that can be at least one or a combination of hardware devices and software modules.

The description of the specific embodiments described above is directed to the general characteristics of the embodiments of the invention such that others may readily adapt and / or modify those specific embodiments for various applications without departing from the general spirit of applying the present knowledge. And are intended to include and, within the meaning and scope of equivalents of the disclosed embodiments, such variations and modifications as such. It is to be understood that the phraseology and terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments of the present invention have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments of the present invention may be modified within the spirit and scope of the embodiments described herein.

The apparatuses and methods of the present disclosure may be implemented in software or computer code executed in hardware or firmware or executed by hardware or firmware or combinations thereof. The controller, central processing unit (CPU), processor, and any unit or device of the present disclosure includes at least hardware and / or other physical structures and elements. In addition, the software or computer code may also be in the form of a non-transitory storage medium, such as a CD ROM, RAM, Read Only Memory (ROM), which may or may not be erased, rewritten, or otherwise. Downloaded locally via a network stored on a DVD, memory chips, hard disk, magnetic storage medium, optical recording medium, or magnetic-optical disc or remote recording medium, computer readable recording medium or non-transitory machine readable medium. Software, computer code, software modules, software objects that may be stored on a recording medium, whereby the methods of the present disclosure are stored in a general purpose computer, digital computer, or a specific processor or programmable or dedicated hardware such as an ASIC or FPGA Fields, instructions, applications, applets, It may be rendered, etc. The (apps). As will be appreciated in the art, a computer, processor, microprocessor controller or programmable hardware may be accessed and executed by temporary and / or non-transitory storage and memory components, such as by the computer, processor or hardware. When, includes temporary and / or non-transitory storage and memory components, such as RAM, ROM, flash, etc., capable of storing or receiving software or computer code that implements the processing methods of the present disclosure. In addition, when accessing code to implement the processing of the present disclosure, execution of the code transforms a general purpose computer into a specific target computer for performing the processing of the present disclosure. In addition, the program is electrically delivered via any medium, such as communication signals and their equivalents transmitted by wireless / wired connections. The program and computer readable recording medium may also be distributed over network-coupled computer systems for storage and execution in a distributed manner.

Although the present disclosure has been discussed, various changes may be included in the present disclosure without departing from the present disclosure. Therefore, the disclosure is not limited to the above embodiments but is defined by the appended claims and their equivalents.

300: computing domain table 303: default state table
600: computing environment 610: processing unit
611: control unit 612: ALU
620: networking devices 630: I / O devices
640: memory 650: storage

Claims (20)

A method of restarting one or more cores of a multi-core processor that is part of an electronic device, the method comprising:
Grouping wake-up sources into a plurality of computing domains;
Receiving an interrupt associated with a wake up source;
Identifying a first computing domain to which the wake-up source belongs from the plurality of computing domains;
Mapping the first computing domain to a first identifier of one or more states of the first core of the processor;
Setting the first core to enter one or more states indicated by the first identifier; And
Restarting the first core after the first core is set, the power management method of a multi-core system.
The method of claim 1, wherein
When the device is in at least one of a sleep mode, a deep sleep mode, and a low power mode, the interrupt is received.
The method of claim 1, wherein the grouping process comprises:
Generating a computing domain table for the plurality of computing domains.
The computing domain table of claim 3, wherein the computing domain table comprises:
Mapping the interrupts in the wakeup sources to the plurality of computing domains.
4. The method of claim 3, wherein the first computing domain is identified based on the computing domain table.
The method of claim 1, wherein
Generating a default state table that associates each of the plurality of computing domains with a different set of one or more states of the first core.
The method of claim 6, wherein the mapping process,
Performed on the basis of the default state table.
7. The method of claim 6, wherein the default state table maps the first computing domain to different P-states for different cores of the processor.
7. The method of claim 6, wherein the default state table maps the first computing domain to a combination of P-state and C-state for the first core.
The method according to claim 6,
The default state table maps the first computing domain to a first state of the first core;
And the default state table maps a second one of the plurality of computing domains to a second state of the first core characterized by a higher power consumption than the first state.
An integrated circuit comprising at least one processor,
The integrated circuit comprising:
Group wake-up sources into a plurality of computing domains,
Receive interrupts associated with the wake-up source,
Identify a first computing domain to which the wake-up source belongs, from the plurality of computing domains,
Map the first computing domain to a first identifier of one or more states of the first core of the processor,
Set the first core to enter one or more states indicated by the first identifier,
And restart the first core after the first core is set.
12. The apparatus of claim 11,
And the interrupt is received when the device is in at least one of a sleep mode, a deep sleep mode, and a low power mode.
The method of claim 11, wherein the grouping,
Generating a computing domain table for the plurality of computing domains.
The computing domain table of claim 13, wherein
And mapping the interrupts in the wakeup sources to the plurality of computing domains.
The apparatus of claim 13, wherein the first computing domain is identified based on the computing domain table.
The method of claim 11, wherein the integrated circuit,
And generate a default state table that associates each of the plurality of computing domains with a different set of one or more states of the first core.
The method of claim 16, wherein the mapping,
The power management device of a multi-core system, performed based on the default state table.
17. The apparatus of claim 16, wherein the default state table maps the first computing domain to different P-states for different cores of the processor.
17. The apparatus of claim 16, wherein the default state table maps the first computing domain to a combination of P-state and C-state for the first core.
17. The method of claim 16,
The default state table maps the first computing domain to a first state of the first core;
And the default state table maps a second computing domain of the plurality of computing domains to a second state of the first core characterized by higher power consumption than the first state.

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