KR20130016893A - Stereoscopic image display device and driving method thereof - Google Patents

Abstract

PURPOSE: A stereoscopic image display device capable of greatly improving the visibility of a displaying image and a driving method thereof are provided to increase the sight angle of the upper side and lower side of a 3D(Three Dimensional) image without lowering the luminance of a 2D(Two Dimensional) image. CONSTITUTION: A patterned retarder(20) divides the light of a display panel(11) into a first polarized light and a second polarized light. In a 3D mode, an upper display unit alternately displays 3D video data and black tone data on the cycle of a frame period. When the 3D video data is displayed on the upper display unit, a lower display unit displays the black tone data. When the black tone data is displayed on the upper display unit, the lower display unit displays the 3D video data.

Description

TECHNICAL FIELD [0001] The present invention relates to a stereoscopic image display device,

The present invention relates to a stereoscopic image display device and a method of driving the same, which can implement a two-dimensional plane image (hereinafter referred to as '2D image') and a three-dimensional image (hereinafter referred to as '3D image').

The stereoscopic image display device implements a stereoscopic image (hereinafter, referred to as a “3D image”) using a binocular parallax technique or an autostereoscopic technique.

The binocular parallax method uses a parallax image of the left and right eyes with a large stereoscopic effect, and there are glasses and no glasses, both of which are put to practical use. In the non-eyeglass system, an optical plate such as a parallax barrier for separating the optical axis of left and right parallax images is installed in front of or behind the display screen. The spectacle method displays left and right parallax images having different polarization directions on a display panel, and implements a stereoscopic image using polarized glasses or liquid crystal shutter glasses.

In the liquid crystal shutter glasses, a left eye image and a right eye image are alternately displayed on a display element in frame units, and 3D image is realized by opening and closing the left and right eye shutters of the liquid crystal shutter glasses in synchronization with the display timing. The liquid crystal shutter glasses open the left eye shutter only during the odd frame period in which the left eye image is displayed and only the right eye shutter is opened during the excellent frame period in which the right eye image is displayed to produce binocular parallax in a time division manner. The liquid crystal shutter glasses have a short data on time, and thus have low luminance of 3D images, and 3D crosstalk is severely generated depending on the synchronization between the display element and the liquid crystal shutter glasses and on / off switching response characteristics.

The polarization glasses method includes a patterned retarder 2 attached to the display panel 1 as shown in FIG. 1. In the polarizing glasses method, the left eye image data L and the right eye image data R are alternately displayed on the display panel 1 in units of horizontal lines, and the polarization incident on the polarizing glasses 3 through the patterned retarder 2 is performed. Switch the characteristic. Through this, the polarized glasses method can realize a 3D image by spatially dividing the left eye image and the right eye image.

In the polarizing glasses method, since the left eye image and the right eye image are displayed adjacent to each other in a line unit, a vertical viewing angle in which 3D crosstalk is not generated is narrow. 3D crosstalk occurs when the left and right eye images are shown superimposed. Accordingly, Japanese Laid-Open Patent Publication No. 2002-185983 has proposed a method of widening the vertical viewing angle of a 3D image by forming a black stripe BS on the patterned retarder 2 as shown in FIG. However, the black stripe BS used to improve the vertical viewing angle causes side effects that greatly reduce the luminance of the 2D image.

In addition, in the polarized glasses method, since the left eye image and the right eye image are displayed to be spatially divided adjacent to each other in a line unit, the visibility (or readability) of the display image is deteriorated on a monocular (left or right eye) basis.

Accordingly, an object of the present invention is to provide a stereoscopic image display apparatus and a driving method thereof, which can widen the vertical viewing angle of a 3D image and increase the visibility of the display image without lowering the brightness of the 2D image. There is.

In order to achieve the above object, a stereoscopic image display device according to an embodiment of the present invention is formed with a plurality of pixels each having an upper display portion and a lower display portion, and the odd pixel lines and the even pixel lines are alternated by the arrangement of the pixels. A display panel configured to selectively implement 2D and 3D images; A patterned retarder that splits the light from the display panel into first and second polarized lights; And displaying the odd left eye image data on the upper display units arranged in the odd pixel lines and the odd right eye image data on the upper display units arranged in the even pixel lines in the odd frame period when the 3D image is implemented. Display black gradation data on the lower display units of the odd and even pixel lines, display the even left eye image data on the lower display units disposed on the odd pixel lines in the even frame period, and arrange the black pixel data on the excellent pixel lines. And a panel driving circuit for displaying even-numbered right eye image data on the lower display units and black gray data on the upper display units of the odd and even pixel lines.

When the 2D image is implemented, the panel driving circuit displays 2D image data on upper and lower display units disposed on the odd pixel lines, and displays 2D image data on upper and lower display units disposed on the even pixel lines. Display.

Each of the pixels is assigned one data line and two gate lines including an upper gate line and a lower gate line; An upper display of each of the pixels is connected to the data line and the upper gate line through a first switch, and the lower display is connected to the data line and the lower gate line through a second switch.

The upper gate line and the lower gate line are alternately arranged along the extending direction of the data line to be driven in a sequential manner; Image data and black gradation data are alternately supplied to the data line every one horizontal period.

The upper gate line and the lower gate line are alternately arranged along an extension direction of the data line to be driven in an interlaced manner; One of the image data and the black gray data is pre-supplied to the data line during the half frame period, and the other one of the image data and the black gray data is later supplied to the remaining half frame period.

The upper gate line is disposed to cross between the upper display portion and the lower display portion, and the lower gate line is disposed in parallel with the upper gate line under the lower display portion.

The upper gate line is disposed above the upper display unit, and the lower gate line is disposed parallel to the upper gate line below the lower display unit.

The vertical width of the upper display portion is selected to be larger than the vertical width of the lower display portion, or is selected to be equal to the vertical width of the lower display portion.

The patterned retarder may include: a first retarder configured to transmit light from the display panel with the first polarization to face the odd pixel lines; And a second retarder configured to transmit light from the display panel with the second polarization to face the even pixel lines.

According to an embodiment of the present invention, a plurality of pixels each having an upper display portion and a lower display portion are formed, and odd pixel lines and even pixel lines are alternately configured by arrangement of the pixels, and selectively implement 2D and 3D images. In the driving method of a stereoscopic image display device including a display panel, when the 3D image is implemented, the left eye image data is displayed on the upper display units disposed on the radix pixel lines in the radix frame period and the superior pixel lines are displayed on the superior pixel lines. Displaying odd-numbered right eye image data on the upper display units arranged and displaying black gray scale data on lower display units of the odd-numbered and even-numbered pixel lines, and even-numbered display on the lower-display units arranged in the odd-numbered pixel lines in the even-numbered frame period. Displaying the left eye image data and the even right in the lower display units disposed in the even pixel lines Displaying the eye image data and displaying black gray data on the upper display portions of the odd and even pixel lines; And dividing the light from the display panel into first polarized light and second polarized light.

The stereoscopic image display device and its driving method according to the present invention divide a pixel into an upper display portion and a lower display portion, and display 2D image data in both the upper display portion and the lower display portion in the 2D mode, whereas the frame period is given in the 3D mode. The black gradation data is displayed alternately on the upper display portion and the lower display portion to function as an active black stripe. Through this, the present invention can widen the upper and lower viewing angles of the 3D image without lowering the brightness of the 2D image.

In addition, in the 3D mode, the 3D image data and the even 3D image data of the odd-numbered 3D image data are alternately displayed on the upper display unit and the lower display unit in a frame period to compensate for the vertical resolution of the 3D image, thereby greatly increasing the visibility of the display image. have.

1 is a view schematically showing a stereoscopic image display device of a conventional polarized glasses method.
FIG. 2 is a view illustrating a black stripe formed on a patterned retarder for improving a viewing angle in a stereoscopic image display device using a conventional polarized glasses. FIG.
3 and 4 are views showing a stereoscopic image display device of a polarizing glasses method according to an embodiment of the present invention.
5A and 5B illustrate an example of the pixel illustrated in FIG. 4.
6A and 6B show another example of the pixel shown in FIG. 4;
FIG. 7 illustrates an example in which 3D image data and black gray data are displayed in a time division and spatial division scheme in a 3D mode. FIG.
8A and 8B illustrate an example of scan pulse and data supply timing in odd and even frames, respectively.
9A and 9B show another example of scan pulse and data supply timing in odd and even frames, respectively.
10 is a view showing the lower viewing angle secured in the cardinal frame and the upper viewing angle secured in the even frame in accordance with the present invention.
11 is a view showing that the average vertical viewing angle is widened in accordance with the same drive as the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 11.

3 and 4 show a three-dimensional image display device of the polarizing glasses method according to an embodiment of the present invention.

3 and 4, the stereoscopic image display device includes a display element 10, a patterned retarder 20, a controller 30, a panel driving circuit 40, and polarizing glasses 50.

The display device 10 includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an inorganic electroluminescent device and an organic light emitting diode device. The display device may be implemented as a flat panel display device such as an electroluminescence device (EL) including an organic light emitting diode (OLED) and an electrophoresis display device (EPD). Hereinafter, the display element 10 will be described mainly with respect to the liquid crystal display element.

The display element 10 includes a display panel 11, an upper polarizer 11a, and a lower polarizer 11b.

The display panel 11 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate line pairs PGL intersecting the data lines DL are disposed on the lower glass substrate of the display panel 11. Due to the cross structure of the signal lines DL and PGL, a pixel array including a plurality of unit pixels UNIT PIX is formed in the display panel 11. A black matrix and a color filter are formed on the upper glass substrate of the display panel 11. Upper and lower polarizing films 11a and 11b are attached to each of the upper and lower glass substrates of the display panel 11, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed. The common electrode supplied with the common voltage (Vcom) may be formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and in plane switching (IPS) mode and FFS. It may be formed on the lower glass substrate together with the pixel electrode in a horizontal electric field driving method such as a (Fringe Field Switching) mode.

The unit pixel UNIT PIX includes three pixels PIX for implementing red (R), green (G), and blue (B). Each of the pixels PIX is allocated with one data line DL and one gate line pair PGL. The gate line pair PGL includes an upper gate line Ga and a lower gate line Gb. Each of the pixels PIX is formed with two display units driven separately. The two display units include an upper display unit driven by an upper gate line Ga and a data line DL, and a lower display unit driven by a lower gate line Gb and a data line DL. In the 3D mode, the upper display unit alternately displays 3D image data and black gray data at frame intervals, the lower display unit displays black gray data when the 3D image data is displayed on the upper display unit, and the black gray data is displayed on the upper display unit. Display 3D image data.

In the 3D mode, the upper display unit and the lower display unit display the black gray data alternately in the frame period and function as an active black stripe, thereby widening the vertical viewing angle of the 3D image, that is, the upper viewing angle and the lower viewing angle. On the other hand, since the upper display unit and the lower display unit both display 2D image data in the 2D mode, side effects such as deterioration of luminance of the 2D image are not generated.

In the 3D mode, the odd third 3D image data is displayed on the upper display in the odd frame period, and the even third 3D image data is displayed on the lower display in the even frame period. By this spatial division and time division display method, the vertical resolution of the 3D image can be compensated, thereby increasing the visibility (or readability) of the display image.

The display device 10 of the present invention may be implemented in any form such as a transmissive display device, a transflective display device, a reflective display device. In the transmissive display device and the transflective display device, the backlight unit 12 is required. The backlight unit 12 may be implemented as a direct type backlight unit or an edge type backlight unit.

The patterned retarder 20 is attached to the upper polarizing film 11a of the display panel 11. The first retarder RT1 is formed in the odd lines of the patterned retarder 20, and the second retarder RT2 is formed in the even lines of the patterned retarder 20. The light absorption axis of the first retarder RT1 and the light absorption axis of the second retarder RT2 are different from each other. The first retarder RT1 of the patterned retarder 20 faces the odd pixel lines of the pixel array, and the second retarder RT2 faces the even pixel lines of the pixel array. The first retarder RT1 delays the phase of the linearly polarized light incident through the upper polarizing film 11a by 1/4 wavelength to pass the first polarized light (eg, left circularly polarized light). The second retarder RT2 delays the phase of linearly polarized light incident through the upper polarizing film 11a by 3/4 wavelength and passes the second polarized light (eg, right circularly polarized light).

The controller 30 controls the operation of the panel driving circuit 40 in the 2D mode or the 3D mode according to the mode selection signal MODE. The controller 30 receives a mode selection signal MODE through a user interface such as a touch screen, an on screen display (OSD), a keyboard, a mouse, and a remote controller, and accordingly, operates the 2D mode. And 3D mode operation can be switched. On the other hand, the controller 30 is a 2D / 3D identification code encoded in the data of the input image, for example, 2D / 3D identification code that can be coded in the EPG (Electronic Program Guide) or ESG (Electronic Service Guide) of the digital broadcast standard May be detected to distinguish between 2D mode and 3D mode.

The controller 30 separates 3D image data input from a video source into left eye image data and right eye image data in the 3D mode. In the radix frame period, the controller 30 assigns the odd left eye image data to the upper display portions arranged in the odd pixel lines and the odd right eye image data to the upper display portions arranged in the even pixel lines and all pixels. The black gradation data is allocated to the lower display portions of the lines. In the even frame period, the controller 30 allocates even-numbered left eye image data to lower displays disposed in odd pixel lines and even-numbered right eye image data to lower displays disposed in even pixel lines and all pixels. The black gradation data is allocated to the upper display portions of the lines. The controller 30 supplies the left eye image data, the right eye image data, and the black gradation data allocated as described above to the data driver 40A in the 3D mode. The controller 30 supplies 2D image data input from the video source to the data driver 40A under the 2D mode.

The controller 30 operates the panel driving circuit 40 by using timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal Data Enable, and a dot clock DCLK. Generate control signals for controlling timing.

The data control signal for controlling the operation timing of the data driver 40A includes a source start pulse (SSP) and a rising point indicating a start point of data in one horizontal period in which data for one horizontal line is displayed. Or a source sampling clock (SSC) that controls the latching operation of data based on a falling edge, a source output enable signal (SOE) that controls the output of the data driver 40A, and a display panel ( And a polarity control signal POL for controlling the polarity of the data voltage to be supplied to the liquid crystal cells of 11).

The gate control signal for controlling the operation timing of the gate driver 40B includes a gate start pulse (GSP) and a gate driver 40B indicating a starting horizontal line at which a scan starts in one vertical period in which one screen is displayed. Gate shift clock signal (GSC) for sequentially shifting the gate start pulse GSP and the gate output enable signal (Gate Output) for controlling the output of the gate driver 40B. Enable: GOE).

The controller 30 multiplies the timing signals Vsync, Hsync, DE, and DCLK in synchronization with the input frame frequency to panel the frame frequency with N × f (N is a positive integer of 2 or more, f is the input frame frequency) Hz. The operation of the driving circuit 40 can be controlled. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the phase-alternating line (PAL) scheme.

The panel driving circuit 40 may include a data driver 40A for driving the data lines DL of the display panel 11, and a gate driver for driving the gate line pairs PGL of the display panel 11. 40B).

Each of the driving ICs of the data driver 40A includes a shift register, a latch, a digital-to-analog converter (DAC), an output buffer, and the like. The data driver 40A latches 2D image data or 3D image data and black gradation data supplied from the controller 30 according to the data control signals SSP, SSC, and SOE. The data driver 40A converts the latched data into the analog positive gamma compensation voltage and the negative gamma compensation voltage in response to the polarity control signal POL to invert the polarity of the data voltage. The data driver 40A outputs a data voltage to the data lines DL to be synchronized with the scan pulse (or gate pulse) output from the gate driver 40B. The driving ICs of the data driver 40A may be bonded to the lower glass substrate of the display panel 11 by a tape automated bonding (TAB) process.

The gate driver 40B generates a scan pulse swinging between the gate high voltage and the gate low voltage according to the gate control signals GSP, GSC, and GOE. The scan pulses are supplied to the gate line pairs PGL in a line sequential manner as shown in FIGS. 8A and 8B according to the gate control signals GSP, GSC, and GOE, or interlace as shown in FIGS. 9A and 9B. Supply in the same way. The gate driver 40B includes a gate shift register array and the like. The gate shift register array of the gate driver 40B may be formed in a non-display area outside the display area in which the pixel array is formed in the display panel 11 by using a gate in panel (GIP) method. By the GIP method, the gate shift registers may be formed together with the pixel array in a thin film transistor (TFT) process of the pixel array. The gate shift register array of the gate driver 40B may be implemented as driving ICs bonded to the lower glass substrate of the display panel 11 by a TAB process.

The polarizing glasses 50 include a left eye 50L having a left eye polarization filter and a right eye 50R having a right eye polarization filter. The left eye polarization filter has the same light absorption axis as the first retarder RT1 of the patterned retarder 20, and the right eye polarization filter has the same light absorption axis as the second retarder RT2 of the patterned retarder 20. Have For example, the left eye polarization filter of the polarizing glasses 50 may be selected as a left circular polarization filter, and the right eye polarization filter of the polarizing glasses 50 may be selected as a right circular polarization filter. The user may view 3D image data displayed on the display device 10 through the polarization glasses 50 in a spatial division and a time division manner.

5A and 5B are diagrams illustrating an example of the pixel PIX illustrated in FIG. 4.

5A and 5B, the upper display unit UP is connected to the upper gate line Ga and the data line DL through the first switch TFT1, and the lower display unit LP is connected to the second switch TFT2. ) Is connected to the upper gate line Ga and the data line DL. The upper gate line Ga is disposed to intersect between the upper display unit UP and the lower display unit LP, and the lower gate line Gb is disposed parallel to the upper gate line Ga at the lower side of the lower display unit LP. do. The gate electrode of the first switch TFT1 is connected to the upper gate line Ga, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the upper display unit UP. The gate electrode of the second switch TFT2 is connected to the lower gate line Gb, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the lower display part LP.

The vertical width W1 of the upper display unit UP is selected to be larger than the vertical width W2 of the lower display unit LP as shown in FIG. 5A, or the vertical width W2 of the lower display unit LP as shown in FIG. 5B. The same can be chosen. In the structure of FIG. 5A, the upper viewing angle of the 3D image may be wider than the lower viewing angle. In the structure of FIG. 5B, the upper viewing angle and the lower viewing angle of the 3D image may be equally secured.

6A and 6B are diagrams illustrating another example of the pixel PIX illustrated in FIG. 4. In the pixel structure of FIGS. 6A and 6B, since the gate line is not disposed between the upper display portion UP and the lower display portion LP, the aperture ratio of the pixel is increased compared to the pixel structure of FIGS. 5A and 5B. have.

6A and 6B, the upper display unit UP is connected to the upper gate line Ga and the data line DL through the first switch TFT1, and the lower display unit LP is connected to the second switch TFT2. ) Is connected to the upper gate line Ga and the data line DL. The upper gate line Ga is disposed above the upper display unit UP, and the lower gate line Gb is disposed parallel to the upper gate line Ga under the lower display unit LP. The gate electrode of the first switch TFT1 is connected to the upper gate line Ga, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the upper display unit UP. The gate electrode of the second switch TFT2 is connected to the lower gate line Gb, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the lower display part LP.

The vertical width W1 of the upper display unit UP is selected to be larger than the vertical width W2 of the lower display unit LP as shown in FIG. 6A, or the vertical width W2 of the lower display unit LP as shown in FIG. 6B. The same can be chosen. In the structure of FIG. 6A, the upper viewing angle of the 3D image may be wider than the lower viewing angle. In the structure of FIG. 6B, the upper viewing angle and the lower viewing angle of the 3D image may be equally secured.

FIG. 7 illustrates an example in which 3D image data and black gray data are displayed in a time division and spatial division scheme in a 3D mode. 8A and 8B show timings in which scan pulses and data are supplied in a line sequential manner in odd and even frames, respectively. 9A and 9B show timings in which scan pulses and data are interlaced in odd and even frames, respectively.

Referring to FIG. 7, a plurality of first pixels PIX1 are disposed in a first pixel line PL # 1 of the display panel 11, and a plurality of second pixels are arranged in a second pixel line PL # 2. Fields PIX2 are disposed, a plurality of third pixels PIX3 are disposed in the third pixel line PL # 3, and a plurality of fourth pixels PIX4 are disposed in the fourth pixel line PL # 4. Is placed. The first retarder RT1 of the patterned retarder 20 faces the odd pixel lines PL # 1 and PL # 3 of the display panel 11 to face the odd pixel lines PL # 1 and PL # 3. The light incident from) is transmitted to the left eye image (L). The second retarder RT2 of the patterned retarder 20 faces even pixel lines PL # 2 and PL # 4 of the display panel 11 to face even pixel lines PL # 2 and PL # 4. The light incident from) is transmitted to the right eye image (R).

In the odd frame period, the upper display units UP of the pixel lines PL # 1 to PL # 4 selectively display the odd-numbered 3D image data L1, R1, L3, and R3, and the pixel lines PL. Lower display parts LP of # 1 to PL # 4 display black gray data BD.

In the odd frame period, the upper display unit UP of each of the first pixels PIX1 disposed in the first pixel line PL # 1 displays the first left eye image data L1 and the first pixels PIX1. Each lower display unit LP displays the black gradation data BD. The upper display unit UP of each of the second pixels PIX2 disposed on the second pixel line PL # 2 displays the first right eye image data R1 and the lower display unit of each of the second pixels PIX2. LP indicates black gradation data BD. The upper display unit UP of each of the third pixels PIX3 disposed on the third pixel line PL # 3 displays the third left eye image data L3 and the lower display unit of each of the third pixels PIX3. LP indicates black gradation data BD. The upper display unit UP of each of the fourth pixels PIX4 arranged on the fourth pixel line PL # 4 displays the third right eye image data R3 and the lower display unit of each of the fourth pixels PIX4. LP indicates black gradation data BD.

To this end, scan pulses may be supplied to the eight gate lines constituting the first to fourth gate line pairs PGL1 to PGL4 as shown in FIG. 8A in a line sequential manner. The image data and the black gradation data are alternately supplied to the data line DL every one horizontal period (supply period of the scan pulse). The odd-numbered left eye image data L1 and L3 are supplied to the data line DL in synchronization with the scan pulse so as to be displayed on the upper display units UP disposed on the odd pixel lines PL # 1 and PL # 3. The odd-numbered right eye image data R1 and R3 are supplied in synchronization with the scan pulse so as to be displayed on the upper display units UP arranged on the even pixel lines PL # 2 and PL # 4, and the black grayscale data BD is applied. May be supplied in synchronization with the scan pulse to be displayed on the lower display parts LP of all the pixel lines PL # 1 to PL # 4.

Meanwhile, as shown in FIG. 9A, scan pulses may be supplied to the eight gate lines constituting the first to fourth gate line pairs PGL1 to PGL4 in an interlaced manner. According to the interlace method, the scan pulse is sequentially supplied first to the upper gate lines Ga of the first to fourth gate line pairs PGL1 to PGL4 for a half frame period, and then for the remaining half frame period. The lower gate lines Gb of the first to fourth gate line pairs PGL1 to PGL4 may be sequentially supplied. When scan pulses are sequentially supplied to the upper gate lines Ga, the image data L1, R1, L3, and R3 are sequentially supplied to the data lines DL, and scan pulses are sequentially supplied to the lower gate lines Gb. When supplied, the black gradation data BD may be supplied. According to the interlace method, the number of swings of data supplied to the data line in the odd frame period, that is, the number of swings between the gray level and the black gray level of the image data is reduced, which is advantageous in reducing power consumption.

In the even frame period, the upper display parts UP of the pixel lines PL # 1 to PL # 4 display the black gray level data BD, and the lower display parts of the pixel lines PL # 1 to PL # 4. LP selectively displays even-numbered 3D image data L2, R2, L4, and R4.

In the even frame period, the upper display unit UP of each of the first pixels PIX1 disposed in the first pixel line PL # 1 displays the black gray data BD, and each of the first pixels PIX1. The lower display unit LP displays second left eye image data L2. The upper display unit UP of each of the second pixels PIX2 disposed on the second pixel line PL # 2 displays black gray data BD, and the lower display unit LP of each of the second pixels PIX2. Indicates second right eye image data R2. The upper display unit UP of each of the third pixels PIX3 disposed on the third pixel line PL # 3 displays black gray data BD, and the lower display unit LP of each of the third pixels PIX3. ) Denotes the fourth left eye image data L4. The upper display unit UP of each of the fourth pixels PIX4 arranged on the fourth pixel line PL # 4 displays black gray data BD, and the lower display unit LP of each of the fourth pixels PIX4. Denotes fourth right eye image data R4.

To this end, scan pulses may be supplied to the eight gate lines constituting the first to fourth gate line pairs PGL1 to PGL4 as shown in FIG. 8B in a line sequential manner. The black gradation data and the image data are alternately supplied to the data line DL every one horizontal period. The even-numbered left eye image data L2 and L4 is supplied to the data line DL in synchronization with the scan pulse so as to be displayed on the lower display units LP disposed on the odd pixel lines PL # 1 and PL # 3. The even-numbered right-eye image data R2 and R4 are supplied in synchronization with the scan pulse so as to be displayed on the lower display parts LP disposed on the even-numbered pixel lines PL # 2 and PL # 4, and the black gradation data BD is applied. Is supplied in synchronization with the scan pulse so as to be displayed on the upper display portions UP of all the pixel lines PL # 1 to PL # 4.

Meanwhile, as shown in FIG. 9B, scan pulses may be supplied to the eight gate lines constituting the first to fourth gate line pairs PGL1 to PGL4 in an interlaced manner. According to the interlace method, the scan pulse is sequentially supplied first to the upper gate lines Ga of the first to fourth gate line pairs PGL1 to PGL4 for a half frame period, and then for the remaining half frame period. The lower gate lines Gb of the first to fourth gate line pairs PGL1 to PGL4 may be sequentially supplied. The black gray data BD is supplied to the data line DL when the scan pulses are sequentially supplied to the upper gate lines Ga, and the image data L2 is supplied when the scan pulses are sequentially supplied to the lower gate lines Gb. , R2, L4, R4 can be supplied. According to the interlace method, the number of swings of the data supplied to the data line in the even frame period, that is, the number of swings between the gray level and the black gray level of the image data is reduced, which is advantageous in reducing power consumption.

10 shows the lower viewing angle secured in the cardinal frame and the upper viewing angle secured in the even frame according to the present invention. In FIG. 10, "GLS1" represents a lower glass substrate, "GLS2" represents an upper glass substrate, "BM" represents a black matrix, and "CF" represents a color filter. 11 shows that the vertical viewing angle is widened on average according to the driving of the present invention.

3D crosstalk (C / T) occurs when the left eye image passes not only the left eye retarder but also the right eye retarder, and the right eye image passes not only the right eye retarder but also the left eye retarder. Such 3D crosstalk is larger when the display panel is viewed obliquely from the upper and lower positions than when the display panel is vertically observed from the front. 3D Crosstalk is not easily noticeable below the threshold. The threshold value may vary depending on the model of the display panel, but may be generally set to 10%.

When the black gray data BD is displayed on the lower display portions of all pixel lines in the odd frame as shown in FIG. 10, the lower viewing angle α1 that satisfies the threshold (10%) of 3D crosstalk is approximately 4 degrees as shown in FIG. 10. It becomes wider. In addition, when the black gray data BD is displayed on the upper display parts of all the pixel lines in the even frame as illustrated in FIG. 10, the upper viewing angle α2 that satisfies the threshold (10%) of 3D crosstalk is approximately as shown in FIG. 11. 4 degrees wider.

On the other hand, as shown in Fig. 10, the odd-numbered 3D image data L1, R1, L3, and R3 are displayed on the upper display portion in the odd-frame period, and the even-numbered 3D image data L2, R2, L4, and R4 are displayed in the even-frame period. It is displayed on the lower display. Since the vertical resolution of the 3D image can be implemented in full by the spatial division and time division display methods, the visibility (or readability) of the display image is improved on a monocular (left or right eye) basis.

As described above, the stereoscopic image display apparatus and its driving method according to the present invention divide the pixel into an upper display portion and a lower display portion, and display 2D image data in both the upper display portion and the lower display portion in the 2D mode, whereas in the 3D mode. In the frame period, the black gray data is alternately displayed on the upper display portion and the lower display portion to function as an active black stripe. Through this, the present invention can widen the upper and lower viewing angles of the 3D image without lowering the brightness of the 2D image.

In addition, in the 3D mode, the 3D image data and the even 3D image data of the odd-numbered 3D image data are alternately displayed on the upper display unit and the lower display unit in a frame period to compensate for the vertical resolution of the 3D image, thereby greatly increasing the visibility of the display image. have.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10 display element 11 display panel
20: patterned retarder 30: controller
40: panel drive circuit 40A: data driver
40B: Gate Driver 50: Polarized Glasses

Claims (11)

A display panel in which a plurality of pixels each having an upper display portion and a lower display portion are formed, and odd pixel lines and even pixel lines are alternately configured by the arrangement of the pixels, and selectively implementing 2D and 3D images;
A patterned retarder that splits the light from the display panel into first and second polarized lights; And
When the 3D image is implemented, the odd left eye image data is displayed on the upper display units disposed in the odd pixel lines in the odd frame period, and the odd right eye image data is displayed on the upper display units disposed on the even pixel lines. Black gray data is displayed on the lower display units of the odd and even pixel lines, and even-numbered left eye image data is displayed on the lower display units disposed on the odd pixel lines in the even frame period and arranged on the even pixel lines. And a panel driving circuit for displaying even-numbered right-eye image data on the lower display parts and displaying black gray-scale data on the upper display parts of the odd and even pixel lines. The method of claim 1,
When the 2D image is implemented, the panel driving circuit displays 2D image data on upper and lower display units disposed on the odd pixel lines, and displays 2D image data on upper and lower display units disposed on the even pixel lines. Stereoscopic display device characterized in that for displaying. The method of claim 1,
Each of the pixels is assigned one data line and two gate lines including an upper gate line and a lower gate line;
The upper display unit of each of the pixels is connected to the data line and the upper gate line through a first switch, and the lower display unit is connected to the data line and the lower gate line through a second switch. Video display. The method of claim 3, wherein
The upper gate line and the lower gate line are alternately arranged along the extending direction of the data line to be driven in a sequential manner;
And the image data and the black gradation data are alternately supplied to the data line every one horizontal period. The method of claim 3, wherein
The upper gate line and the lower gate line are alternately arranged along an extension direction of the data line to be driven in an interlaced manner;
One of the image data and the black gradation data is pre-supplied to the data line for 1/2 frame period, and the other one of the image data and the black gradation data is supplied after the remaining half frame period. Display. The method of claim 3, wherein
And the upper gate line intersects between the upper display unit and the lower display unit, and the lower gate line is disposed in parallel with the upper gate line under the lower display unit. The method of claim 3, wherein
And the upper gate line is disposed above the upper display unit, and the lower gate line is disposed in parallel with the upper gate line under the lower display unit. The method of claim 3, wherein
The vertical width of the upper display unit is selected to be larger than the vertical width of the lower display unit, or is selected to be equal to the vertical width of the lower display unit. The method of claim 1,
The patterned retarder,
A first retarder configured to transmit light from the display panel with the first polarization to face the odd pixel lines;
And a second retarder configured to transmit light from the display panel with the second polarization to face the even pixel lines. A plurality of pixels, each having an upper display portion and a lower display portion, are formed, and a three-dimensional image including a display panel for alternately forming odd pixel lines and even pixel lines by the arrangement of the pixels, and selectively implementing 2D and 3D images. In the driving method of the display device,
When the 3D image is implemented, the odd left eye image data is displayed on the upper display units disposed in the odd pixel lines in the odd frame period, and the odd right eye image data is displayed on the upper display units disposed on the even pixel lines. Black gray data is displayed on the lower display units of the odd and even pixel lines, and even-numbered left eye image data is displayed on the lower display units disposed on the odd pixel lines in the even frame period and arranged on the even pixel lines. Displaying even-numbered right eye image data on lower display parts and displaying black gray level data on upper display parts of the odd and even pixel lines; And
And dividing light from the display panel into first polarized light and second polarized light. 11. The method of claim 10,
When the 2D image is implemented, displaying 2D image data on upper and lower display units disposed on the odd pixel lines, and displaying 2D image data on upper and lower display units disposed on the even pixel lines. A driving method of a three-dimensional image display device comprising a.

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