KR20110012673A - Semiconductor package and stack package using the same - Google Patents

Semiconductor package and stack package using the same Download PDF

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KR20110012673A
KR20110012673A KR1020090070490A KR20090070490A KR20110012673A KR 20110012673 A KR20110012673 A KR 20110012673A KR 1020090070490 A KR1020090070490 A KR 1020090070490A KR 20090070490 A KR20090070490 A KR 20090070490A KR 20110012673 A KR20110012673 A KR 20110012673A
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core layer
package
connection member
group
semiconductor chip
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KR1020090070490A
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Korean (ko)
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이규원
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주식회사 하이닉스반도체
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Publication of KR20110012673A publication Critical patent/KR20110012673A/en

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Abstract

PURPOSE: A semiconductor package and a stack package using the same is provided to reduce the thickness of a package by forming a semiconductor chip as an embedded structure and using a first thin substrate. CONSTITUTION: A substrate is comprised of a first core layer(210) and a second core layer(230). The first core layer comprises a first side(211) a second side(212) facing the first side. The second core layer is laminated on the first core layer. A semiconductor chip(220) comprises a semiconductor chip(221) and a bonding pad(222). A conductive pattern(260) electrically connects a bonding finger(251A) of the semiconductor chip with the bonding pad(221) of the second core layer.

Description

반도체 패키지 및 이를 이용한 스택 패키지{SEMICONDUCTOR PACKAGE AND STACK PACKAGE USING THE SAME}Semiconductor package and stack package using same {{SEMICONDUCTOR PACKAGE AND STACK PACKAGE USING THE SAME}

본 발명은 반도체 패키지 및 이를 이용한 스택 패키지에 관한 것으로, 보다 상세하게는 패키지의 두께를 줄인 경박단소한 새로운 형태의 반도체 패키지 및 이를 이용한 스택 패키지에 관한 것이다.The present invention relates to a semiconductor package and a stack package using the same, and more particularly, to a light and simple semiconductor package having a reduced thickness of the package and a stack package using the same.

집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전되어 왔다. 최근에 들어서는 전기/전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라 스택(stack)에 대한 다양한 기술들이 개발되고 있다.Packaging technology for integrated circuits has been continuously developed to meet the requirements for miniaturization and mounting reliability. Recently, as the miniaturization of electric / electronic products and high performance are required, various technologies for stacks have been developed.

반도체 산업에서 말하는 "스택"이란 적어도 2개 이상의 칩 또는 패키지를 수직으로 쌓아 올리는 것으로서, 이러한 스택 기술을 이용하면 메모리 소자의 경우 반도체 집적 공정에서 구현 가능한 메모리 용량보다 2배 이상의 메모리 용량을 갖는 제품을 구현할 수 있다. 또한, 스택 패키지는 메모리 용량 증대는 물론 실장 밀도 및 실장 면적 사용의 효율성 측면에서 잇점을 갖기 때문에 스택 패키지에 대한 연구 및 개발이 가속화되고 있는 실정이다.In the semiconductor industry, the term "stack" refers to stacking at least two chips or packages vertically. This stacking technology allows a memory device to have a product having a memory capacity that is twice the memory capacity that can be realized in a semiconductor integrated process. Can be implemented. In addition, since stack packages have advantages in terms of increasing memory capacity and efficiency of mounting density and footprint area, research and development on stack packages are being accelerated.

도 1은 종래 기술에 따른 단위 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a unit package according to the prior art.

도 1을 참조하면, 종래 기술에 따른 단위 패키지(100)는 기판(120) 상에 접착제(114)를 매개로 반도체 칩(110)이 실장되고, 반도체 칩(110) 상면에 마련된 본딩 패드(112)와 기판(120) 상면에 마련된 접속 패드(122)가 금속 와이어(116)을 통해 전기적으로 연결된 구조를 갖는다. Referring to FIG. 1, in the unit package 100 according to the related art, a semiconductor chip 110 is mounted on a substrate 120 through an adhesive 114, and a bonding pad 112 provided on an upper surface of the semiconductor chip 110. ) And the connection pad 122 provided on the upper surface of the substrate 120 have an electrically connected structure through the metal wire 116.

미설명된 도면부호 124는 볼랜드 패턴을, 170은 솔더볼을 각각 나타낸다.Unexplained reference numeral 124 denotes a ballland pattern, and 170 denotes a solder ball.

그러나, 전술한 종래 기술은 다음과 같은 문제점이 있다.However, the above-described prior art has the following problems.

반도체 칩(110)의 본딩 패드(112)와 기판(120)의 접속 패드(122)간 전기적인 신호 교환이 금속 와이어(116)를 통해 이루어지므로 속도가 느리다,The electrical signal is exchanged between the bonding pads 112 of the semiconductor chip 110 and the connection pads 122 of the substrate 120 through the metal wire 116, and thus is slow.

그리고, 금속 와이어(116)를 형성하기 위해 기판(120)에 추가 면적이 요구되어 패키지 크기가 증가하고, 반도체 칩(110)에 와이어 본딩하기 위한 갭(gap)이 요구되므로 다수의 단위 패키지들을 수직 방향으로 쌓아 스택 패키지를 구성할 경우 두께 상승이 심하다.In addition, an additional area is required in the substrate 120 to form the metal wire 116, thereby increasing the package size, and a gap for wire bonding to the semiconductor chip 110 is required. If the stack package is stacked in the direction to increase the thickness.

또한, 기판(120) 두께가 두꺼워 스택 패키지를 구성할 경우 두께 상승이 심하고, 패키지 제작 이후에는 추가적인 적층이 힘들다는 단점이 있다.In addition, when the thickness of the substrate 120 is large, when the stack package is configured, the thickness is severely increased, and additional lamination is difficult after the package is manufactured.

본 발명은 패키지의 두께를 줄인 경박단소한 새로운 형태의 반도체 패키지 및 이를 이용한 스택 패키지를 제공한다.The present invention provides a novel and lightweight semiconductor package with a reduced thickness of the package and a stack package using the same.

본 발명의 실시예에 따른 반도체 패키지는, 제1면 및 상기 제1면에 대향하는 제2면을 가지며 상기 제1면으로부터 제2면을 관통하는 제1연결부재를 구비한 제1코어층과, 상기 제1코어층의 제1면 상에 결합되며 상기 제1코어층의 제1면과 접촉하는 일면으로부터 상기 일면에 대향하는 타면을 관통하고 상기 제1연결부재와 전기적으로 연결된 제2연결부재 및 윈도우를 구비하는 제2코어층을 포함하는 기판과, 상기 윈도우 내에 삽입되어 상기 윈도우에 의해 노출된 제1코어층의 제1면 상에 부착되고 상면에 본딩 패드가 구비된 반도체 칩과, 상기 반도체 칩의 본딩 패드와 제2코어층의 제2연결부재를 전기적으로 연결하는 도전 패턴을 포함하는 것을 특징으로 한다.A semiconductor package according to an embodiment of the present invention includes a first core layer having a first surface and a second surface facing the first surface and having a first connection member penetrating through the second surface from the first surface; A second connection member coupled to the first surface of the first core layer and penetrating through the other surface opposite to the one surface from one surface contacting the first surface of the first core layer and electrically connected to the first connection member; And a semiconductor chip including a second core layer having a window, a semiconductor chip inserted in the window and attached to a first surface of the first core layer exposed by the window, and having a bonding pad on the upper surface thereof. And a conductive pattern for electrically connecting the bonding pad of the semiconductor chip and the second connection member of the second core layer.

상기 제1코어층의 제2면을 통해 노출된 상기 제1연결부재 또는 상기 제2코어층의 타면을 통해 노출된 상기 제2연결부재에 부착된 실장 부재를 더 포함하는 것을 특징으로 한다.And a mounting member attached to the first connection member exposed through the second surface of the first core layer or the second connection member exposed through the other surface of the second core layer.

상기 제1코어층은 프리프레그(prepreg)로 이루어진 것을 특징으로 한다.The first core layer may be made of prepreg.

상기 제2코어층은 열가소성 필름으로 이루어진 것을 특징으로 한다.The second core layer is characterized in that made of a thermoplastic film.

상기 열가소성 필름은 폴리이미드기, 아라미드기, 폴리에테르이미드기, 폴리 에틸렌기, 텔레포탈염산기, 에폭시기, 시안염산기, 에스테르기 중 적어도 하나 이상을 포함하는 것을 특징으로 한다.The thermoplastic film is characterized by comprising at least one of polyimide group, aramid group, polyetherimide group, polyethylene group, teleportal hydrochloric acid group, epoxy group, cyan hydrochloric acid group, ester group.

상기 제1연결부재는 상기 제1코어층의 제2면에서 단차를 갖고 형성된 것을 특징으로 한다.The first connection member is formed with a step on the second surface of the first core layer.

상기 제 2 연결부재는 상기 제2코어층의 타면에서 단차를 갖고 형성된 것을 특징으로 한다.The second connection member is characterized in that it is formed with a step on the other surface of the second core layer.

본 발명의 실시예에 따른 스택 패키지는, 청구항 1항의 구조를 가지며, 적어도 2개 이상이 스택된 단위 패키지들과, 상기 단위 패키지들 사이에 개재되는 본딩유지부재를 포함하는 것을 특징으로 한다.The stack package according to an embodiment of the present invention has the structure of claim 1, and includes at least two or more stacked unit packages and bonding holding members interposed between the unit packages.

상기 본딩유지부재는 경화성 본딩 시트로 이루어진 것을 특징으로 한다.The bonding holding member is characterized in that consisting of a curable bonding sheet.

본 발명에 따르면, 반도체 칩을 임베디드 구조로 형성하고 1 레이어의 얇은 기판을 사용하여 패키지 두께를 낮출 수 있다. 또한, 와이어 본딩을 사용하지 않으므로 와이어 본딩 사용에 따른 문제점들(속도가 느림, 특성 열화 발생, 패키지 크기 및 두께가 증가됨)을 극복할 수 있으며, 패키지 제작 이후에도 추가적인 스택이 가능한 장점이 있다.According to the present invention, a semiconductor chip can be formed into an embedded structure and a package thickness can be reduced by using a thin substrate of one layer. In addition, since wire bonding is not used, problems caused by the use of wire bonding (slow speed, deterioration of characteristics, package size and thickness are increased), and an additional stack is possible even after fabrication of the package.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 반도체 패키지를 나타낸 단면도이고, 도 3 은 도 2의 제1코어층을 나타낸 단면도이고, 도 4는 도 2의 제2코어층을 나타낸 평면도이고, 도 5는 도 4의 Ⅰ-Ⅰ' 라인에 따른 단면도이다.2 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention, FIG. 3 is a cross-sectional view showing a first core layer of FIG. 2, FIG. 4 is a plan view showing a second core layer of FIG. 2, and FIG. 5 is It is sectional drawing along the II 'line | wire of FIG.

도 2를 참조하면, 본 발명의 실시예에 따른 반도체 패키지(200)는 제1코어층(210) 및 제2코어층(230)으로 이루어진 기판, 반도체 칩(220), 도전 패턴(260) 및 실장 부재(280)를 포함한다.Referring to FIG. 2, a semiconductor package 200 according to an embodiment of the present invention may include a substrate, a semiconductor chip 220, a conductive pattern 260, and a first core layer 210 and a second core layer 230. The mounting member 280 is included.

도 3 및 도 2를 다시 참조하면, 제1코어층(210)은 플레이트 형상을 가질 수 있다. 플레이트 형상을 갖는 제1코어층(210)은 제1면(211) 및 제1면(211)에 대향하는 제2면(212)을 갖는다.Referring to FIGS. 3 and 2 again, the first core layer 210 may have a plate shape. The first core layer 210 having a plate shape has a first surface 211 and a second surface 212 opposite to the first surface 211.

제1코어층(210)은 프리프레그(prepreg)로 구성될 수 있다.The first core layer 210 may be made of prepreg.

도 2를 다시 참조하면, 제1코어층(210) 상에는 반도체 칩(220)이 삽입되는 윈도우(window, 233)를 갖는 제2코어층(230)이 결합된다. Referring to FIG. 2 again, a second core layer 230 having a window 233 into which the semiconductor chip 220 is inserted is coupled on the first core layer 210.

도 4 및 도 5를 참조하면, 제2코어층(230)은 플레이트 형상을 가질 수 있다.4 and 5, the second core layer 230 may have a plate shape.

플레이트 형상을 갖는 제2코어층(230)은 제1코어층(210)에 대응하는 일면(231) 및 제1코어층(210)에 대향하는 타면(232)을 갖는다.The second core layer 230 having a plate shape has one surface 231 corresponding to the first core layer 210 and the other surface 232 opposite to the first core layer 210.

제2코어층(230)은 일면(231)으로부터 타면(232)을 관통하는 제2연결부재(250)을 구비한다.The second core layer 230 includes a second connection member 250 penetrating from one surface 231 to the other surface 232.

제2코어층(23)은 열가소성 필름으로 구성될 수 있다.The second core layer 23 may be made of a thermoplastic film.

열가소성 필름은 폴리이미드(polyimide)기, 아라미드(aramid)기, 폴리에테르이미드(polyetherimide)기, 폴리에틸렌(polyethylene)기, 텔레포탈염산(terephthalate)기, 에폭시(epoxy)기, 시안염산(cyanate)기, 에스테르(ester)기 중 적어도 하나 이상을 포함한다The thermoplastic film may be a polyimide group, an aramid group, a polyetherimide group, a polyethylene group, a terephthalate group, an epoxy group, or a cyanate group. And at least one of ester groups

윈도우(233)를 통해 노출된 제1코어층(210)의 제1면(211) 상에는 접착 부재(270)을 매개로 반도체 칩(220)이 부착된다.The semiconductor chip 220 is attached to the first surface 211 of the first core layer 210 exposed through the window 233 through the adhesive member 270.

제2코어층(230)은 고온 및 고압에서 진행되는 열압착 과정을 통해 반도체 칩(220)의 측면 및 제1코어층(210)의 제1면(211)과 밀착된다.  The second core layer 230 is in close contact with the side surface of the semiconductor chip 220 and the first surface 211 of the first core layer 210 through a thermocompression process performed at high temperature and high pressure.

제2코어층(230)의 열압착 과정은 예를 들어, 100 내지 300℃의 온도, 0.1 내지 10Mpa의 압력 하에서 10 내지 300초 동안 진행될 수 있다.The thermocompression process of the second core layer 230 may be performed, for example, for 10 to 300 seconds under a temperature of 100 to 300 ° C. and a pressure of 0.1 to 10 MPa.

열압착 과정에서 가해지는 높은 온도에 의해 열가소성 필름으로 구성된 제2코어층(230)이 유동성을 갖게 되는데, 유동성을 갖는 제2코어층(230)에 높은 압력이 가해짐에 따라서 제2코어층(230)의 일면(231)은 제1코어층(210)의 제1면(211)과 밀착되고, 제2코어층(230)의 측면은 반도체 칩(220)의 측면과 밀착된다.Due to the high temperature applied in the thermocompression process, the second core layer 230 made of the thermoplastic film has fluidity. As the high pressure is applied to the second core layer 230 having the fluidity, the second core layer ( One surface 231 of 230 may be in close contact with the first surface 211 of the first core layer 210, and the side surface of the second core layer 230 may be in close contact with the side surface of the semiconductor chip 220.

반도체 칩(220)은 반도체 칩 몸체(221), 본딩 패드(222)를 포함한다.The semiconductor chip 220 includes a semiconductor chip body 221 and a bonding pad 222.

반도체 칩 몸체(221)는 회로부(미도시)를 포함한다. 회로부는, 예를 들어 데이터를 저장하기 위한 저장부 및 데이터를 처리하기 위한 데이터 처리부를 포함한다.The semiconductor chip body 221 includes a circuit unit (not shown). The circuitry includes, for example, a storage for storing data and a data processor for processing the data.

본딩 패드(222)는 제1코어층(210)과 대향하는 반도체 칩 몸체(221)의 상면에 배치되며 상기 회로부와 전기적으로 연결된다. The bonding pad 222 is disposed on an upper surface of the semiconductor chip body 221 facing the first core layer 210 and is electrically connected to the circuit unit.

반도체 칩(220)의 상면은 제2코어층(230)의 타면(232)과 동일한 표면 높이를 가질 수 있다. The upper surface of the semiconductor chip 220 may have the same surface height as the other surface 232 of the second core layer 230.

도 3 및 도 2를 다시 참조하면, 제1코어층(210)은 반도체 칩(220) 양측으로 제1면(211)에서부터 제2면(212)을 관통하는 제1관통홀(213)을 포함한다. 3 and 2, the first core layer 210 includes a first through hole 213 penetrating through the second surface 212 from the first surface 211 to both sides of the semiconductor chip 220. do.

제1관통홀(213)은 도전볼이 삽입될 수 있도록 제1면(211)에서보다 제2면(212)에서 더 큰 사이즈의 직경을 가질 수 있다. 예를 들어, 제1관통홀(213)은 V자 형태를 가질 수 있다.The first through hole 213 may have a larger diameter on the second surface 212 than on the first surface 211 so that the conductive ball can be inserted therein. For example, the first through hole 213 may have a V shape.

제1관통홀(213)에는 제1연결부재(240)가 형성된다.The first connecting member 240 is formed in the first through hole 213.

제1연결부재(240)는 도전볼이 삽입될 수 있는 제1홈(243)이 제공되도록 V자 형태를 갖는 제1관통홀(213)의 내부 벽면을 따라서 단차를 갖고 형성될 수 있다.The first connection member 240 may have a step along the inner wall surface of the first through hole 213 having a V-shape so that the first groove 243 into which the conductive ball can be inserted is provided.

제1코어층(210)의 제2면(212) 상에는 제1코어층(210)의 제2면(212)을 통해 노출된 제1연결부재(240)의 단부와 전기적으로 연결되는 랜드 패드(241)가 형성되고, 제1코어층(210)의 제1면(211) 상에는 제1코어층(210)의 제1면(211)을 통해 노출된 제1연결부재(240)의 단부와 전기적으로 연결되는 제1본드패드(242)가 형성된다. On the second surface 212 of the first core layer 210, a land pad electrically connected to an end of the first connection member 240 exposed through the second surface 212 of the first core layer 210 ( 241 is formed on the first surface 211 of the first core layer 210 and electrically connected to an end portion of the first connection member 240 exposed through the first surface 211 of the first core layer 210. A first bond pad 242 is formed to be connected.

상기 랜드 패드(241) 및 제1본드패드(242)는 제1연결부재(240)와 일체로 구성될 수 있다.The land pad 241 and the first bond pad 242 may be integrally formed with the first connection member 240.

도 2, 도 4 및 도 5를 다시 참조하면, 제2코어층(230)은 제2관통홀(234)을 포함한다.Referring to FIGS. 2, 4 and 5 again, the second core layer 230 includes a second through hole 234.

제2관통홀(234)은 도전볼이 삽입될 수 있도록 일면(231)에서보다 타면(232)에서 더 큰 사이즈의 직경을 가질 수 있다. 예를 들어, 제2관통홀(234)은 Y자 형태를 가질 수 있다.The second through hole 234 may have a larger diameter on the other surface 232 than on one surface 231 to allow the conductive ball to be inserted. For example, the second through hole 234 may have a Y shape.

제2관통홀(234)에는 제2연결부재(250)가 형성된다.A second connecting member 250 is formed in the second through hole 234.

제2연결부재(250)는 도전볼이 삽입될 수 있는 제2홈(253)이 제공되도록 Y자 형태를 갖는 제2관통홀(234)의 내부 벽면을 따라서 단차를 갖고 형성될 수 있다.The second connection member 250 may have a step along the inner wall surface of the second through hole 234 having a Y-shape to provide a second groove 253 into which the conductive ball can be inserted.

제2코어층(230)의 타면(232) 상에는 일측 단부가 제2코어층(230)의 타면(232)을 통해 노출된 제2연결부재(250)에 연결되고 일측 단부에 대향하는 타측 단부가 윈도우(233)의 측면을 통해 노출되는 회로 배선(251)이 구성된다. On the other surface 232 of the second core layer 230, one end thereof is connected to the second connection member 250 exposed through the other surface 232 of the second core layer 230, and the other end opposite to the one end thereof is formed. The circuit wiring 251 is exposed through the side surface of the window 233.

회로 배선(251)은 윈도우(233)의 가장자리에 배치되는 본딩 핑거(251A), 본딩 핑거(251A)와 제2연결부재(250)를 전기적으로 연결하는 트레이스(251B)를 포함한다.The circuit wiring 251 includes a bonding finger 251A disposed at an edge of the window 233, and a trace 251B electrically connecting the bonding finger 251A and the second connection member 250.

제2코어층(230)의 일면(231)에는 제2코어층(230)의 일면(231)을 통해 노출된 제2연결부재(250)의 단부와 전기적으로 연결되는 제2본드 패드(252)가 형성된다.The second bond pad 252 is electrically connected to one end 231 of the second core layer 230 through an end of the second connection member 250 exposed through the one surface 231 of the second core layer 230. Is formed.

제2본드 패드(252)는 제1본드 패드(242)와 전기적으로 연결된다.The second bond pad 252 is electrically connected to the first bond pad 242.

제1본드 패드(242) 및 제2본드 패드(252)는 열압착되는 제2코어층(230)에 의하여 그 측면이 감싸진다.Side surfaces of the first bond pad 242 and the second bond pad 252 are surrounded by a second core layer 230 which is thermocompressed.

상기 본딩 핑거(251A), 트레이스(251B) 및 제2본드 패드(252)는 제2연결부재(250)와 일체로 구성될 수 있다.The bonding finger 251A, the trace 251B, and the second bond pad 252 may be integrally formed with the second connection member 250.

도전 패턴(260)은 동일한 표면 레벨을 갖는 반도체 칩(220)의 상면 및 제2코어층(230)의 타면(232) 상에 형성되어 반도체 칩(220)의 본딩 핑거(251A)와 제2코어층(230)의 본딩 패드(221)를 전기적으로 연결한다.The conductive pattern 260 is formed on the upper surface of the semiconductor chip 220 and the other surface 232 of the second core layer 230 having the same surface level so that the bonding fingers 251A and the second core of the semiconductor chip 220 are formed. The bonding pads 221 of the layer 230 are electrically connected.

실장 부재(280)는 제1연결부재(240) 상에 제1홈(243)을 채우면서 부착될 수 있다. 이와 다르게, 실장 부재(280)는 제2연결부재(250) 상에 제2홈(253)을 채우면 서 부착될 수도 있다.The mounting member 280 may be attached to the first connecting member 240 while filling the first groove 243. Alternatively, the mounting member 280 may be attached while filling the second groove 253 on the second connection member 250.

도 6은 본 발명의 일 실시예에 따른 스택 패키지를 나타낸 단면도이다.6 is a cross-sectional view showing a stack package according to an embodiment of the present invention.

도 6을 참조하면, 상부에 위치하는 단위 패키지(200A)의 제 1 연결부재(240) 상에 부착된 실장 부재(280)가 하부에 위치하는 단위 패키지(200B)의 제 2 연결부재(250) 상에 연결되어 스택 패키지가 구성된다. 그리고, 단위 패키지들(200A, 200B) 사이 사이에는 상, 하부 단위 패키지(200A, 200B)들간 결합을 강화시키기 위한 본딩유지부재(291)가 구성된다.Referring to FIG. 6, the second connection member 250 of the unit package 200B having the mounting member 280 attached to the first connection member 240 of the unit package 200A positioned at the bottom thereof is located at the bottom thereof. Connected to the stack package. A bonding holding member 291 is formed between the unit packages 200A and 200B to strengthen the coupling between the upper and lower unit packages 200A and 200B.

본딩유지부재(291)로는 경화성 본딩 시트가 사용될 수 있다.As the bonding holding member 291, a curable bonding sheet may be used.

그리고, 최상부에 위치하는 단위 패키지(200A)의 상면에는 노출된 반도체 칩(220) 및 도전 패턴(260)을 보호하기 위한 보호막(292)이 배치된다.In addition, a passivation layer 292 for protecting the exposed semiconductor chip 220 and the conductive pattern 260 is disposed on the upper surface of the unit package 200A positioned at the top.

보호막(292)은 솔더 레지스트 또는 보호 필름일 수 있다.The protective film 292 may be a solder resist or a protective film.

이와 다르게, 최상부에 위치하는 단위 패키지(200A) 상면은 몰딩재에 의해 완전히 몰딩될 수도 있다.Alternatively, the upper surface of the unit package 200A positioned at the top may be completely molded by the molding material.

도 7 본 발명의 다른 실시예에 따른 스택 패키지를 타낸 단면도이다.7 is a cross-sectional view showing a stack package according to another embodiment of the present invention.

도 7을 참조하면, 상부에 위치하는 단위 패키지(200A)의 제 2 도전성 연결부재(250) 상에 부착된 도전볼(280)이 하부에 위치하는 단위 패키지(200B)의 제 1 연결부재(240) 상에 연결되어 스택 패키지가 구성된다. 그리고, 단위 패키지들(200A, 200B) 사이 사이에는 상, 하부 단위 패키지(200A, 200B)들간 결합을 강화시키기 위한 본딩유지부재(291)가 구성된다.Referring to FIG. 7, the first connection member 240 of the unit package 200B in which the conductive ball 280 attached on the second conductive connection member 250 of the unit package 200A positioned in the upper portion is located in the lower portion thereof. Connected to the stack package. A bonding holding member 291 is formed between the unit packages 200A and 200B to strengthen the coupling between the upper and lower unit packages 200A and 200B.

본딩유지부재(291)로는 경화성 본딩 시트가 사용될 수 있다. As the bonding holding member 291, a curable bonding sheet may be used.

그리고, 최하부에 위치하는 단위 패키지(200B)의 하면에는 노출된 반도체 칩(220) 및 도전성 라인(260)을 덮고 제 2 연결부재(250) 및 도전볼(280)을 노출하는 윈도우를 갖는 보호막(292)이 배치된다.In addition, a lower surface of the unit package 200B positioned at the bottom thereof may include a passivation layer having a window covering the exposed semiconductor chip 220 and the conductive line 260 and exposing the second connection member 250 and the conductive ball 280. 292 is disposed.

보호막(292)은 솔더레지스트 또는 보호 필름일 수 있다.The protective film 292 may be a solder resist or a protective film.

전술한 실시예들에서는, 적층되는 단위 패키지들의 개수가 2개인 경우에 한하여 설명하였으나, 본 발명은 이에 한정되지 않으며 적층되는 단위 패키지들의 개수가 3개 이상인 경우도 가능하다.In the above-described embodiments, the present invention has been described only when the number of stacked unit packages is two. However, the present invention is not limited thereto, and the number of stacked unit packages may be three or more.

이상에서 상세하게 설명한 바에 의하면, 반도체 칩을 임베디드 구조로 형성하고 1 레이어의 얇은 기판을 사용하여 패키지 두께를 낮출 수 있다. 또한, 와이어 본딩을 사용하지 않으므로 와이어 본딩 사용에 따른 문제점들(속도가 느림, 특성 열화 발생, 패키지 크기 및 두께가 증가됨)을 극복할 수 있으며, 패키지 제작 이후에도 추가적인 스택이 가능한 장점이 있다.As described in detail above, the semiconductor chip may be formed in an embedded structure and the thickness of the package may be reduced by using a thin substrate of one layer. In addition, since wire bonding is not used, problems caused by the use of wire bonding (slow speed, deterioration of characteristics, package size and thickness are increased), and an additional stack is possible even after fabrication of the package.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

도 1은 종래 기술에 따른 반도체 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor package according to the prior art.

도 2는 본 발명의 실시예에 따른 반도체 패키지를 나타낸 단면도이다.2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도 3은 도 2의 제1코어층을 나타낸 단면도이다. 3 is a cross-sectional view illustrating the first core layer of FIG. 2.

도 4는 도 2의 제2코어층을 나타낸 평면도이다.4 is a plan view illustrating the second core layer of FIG. 2.

도 5는 도 4의 Ⅰ-Ⅰ' 라인에 따른 단면도이다.5 is a cross-sectional view taken along the line II ′ of FIG. 4.

도 6은 본 발명의 일 실시예에 따른 스택 패키지를 나타낸 단면도이다.6 is a cross-sectional view showing a stack package according to an embodiment of the present invention.

도 7은 본 발명의 다른 실시예에 따른 스택 패키지를 나타낸 단면도이다.7 is a cross-sectional view showing a stack package according to another embodiment of the present invention.

<도면의 주요부분에 대한 설명><Description of main parts of drawing>

210 : 제1코어층210: first core layer

220 : 반도체 칩220: semiconductor chip

230 : 제2코어층230: second core layer

260 : 도전 패턴260: Challenge Pattern

280 : 실장 부재280: mounting member

Claims (9)

제1면 및 상기 제1면에 대향하는 제2면을 가지며 상기 제1면으로부터 제2면을 관통하는 제1연결부재를 구비한 제1코어층과, 상기 제1코어층의 제1면 상에 결합되며 상기 제1코어층의 제1면과 접촉하는 일면으로부터 상기 일면에 대향하는 타면을 관통하고 상기 제1연결부재와 전기적으로 연결된 제2연결부재 및 윈도우를 구비하는 제2코어층을 포함하는 기판;A first core layer having a first surface and a second surface opposite to the first surface, the first core layer having a first connecting member penetrating through the second surface from the first surface, and on the first surface of the first core layer; A second core layer coupled to the first core layer, the second core layer having a second connection member and a window penetrating through the other surface facing the first surface and electrically connected to the first connection member from one surface in contact with the first surface of the first core layer. A substrate; 상기 윈도우 내에 삽입되어 상기 윈도우에 의해 노출된 제1코어층의 제1면 상에 부착되고 상면에 본딩 패드가 구비된 반도체 칩;및A semiconductor chip inserted in the window and attached to the first surface of the first core layer exposed by the window and having a bonding pad on the upper surface thereof; and 상기 반도체 칩의 본딩 패드와 제2코어층의 제2연결부재를 전기적으로 연결하는 도전 패턴;A conductive pattern electrically connecting the bonding pad of the semiconductor chip and the second connection member of the second core layer; 을 포함하는 것을 특징으로 하는 반도체 패키지.A semiconductor package comprising a. 제 1항에 있어서,The method of claim 1, 상기 제1코어층의 제2면을 통해 노출된 상기 제1연결부재 또는 상기 제2코어층의 타면을 통해 노출된 상기 제2연결부재에 부착된 실장 부재를 더 포함하는 것을 특징으로 하는 반도체 패키지. And a mounting member attached to the first connection member exposed through the second surface of the first core layer or the second connection member exposed through the other surface of the second core layer. . 제 1항에 있어서,The method of claim 1, 상기 제1코어층은 프리프레그(prepreg)로 이루어진 것을 특징으로 하는 반도 체 패키지.The first core layer is a semiconductor package, characterized in that made of prepreg (prepreg). 제 1항에 있어서,The method of claim 1, 상기 제2코어층은 열가소성 필름으로 이루어진 것을 특징으로 하는 반도체 패키지.The second core layer is a semiconductor package, characterized in that made of a thermoplastic film. 제 4에 있어서,According to claim 4, 상기 열가소성 필름은 폴리이미드기, 아라미드기, 폴리에테르이미드기, 폴리에틸렌기, 텔레포탈염산기, 에폭시기, 시안염산기, 에스테르기 중 적어도 하나 이상을 포함하는 것을 특징으로 하는 반도체 패키지.The thermoplastic film comprises at least one of polyimide group, aramid group, polyetherimide group, polyethylene group, teleportal hydrochloric acid group, epoxy group, cyan hydrochloric acid group, ester group. 제 1항에 있어서,The method of claim 1, 상기 제1연결부재는 상기 제1코어층의 제2면에서 단차를 갖고 형성된 것을 특징으로 하는 반도체 패키지.The first connection member is a semiconductor package, characterized in that formed with a step on the second surface of the first core layer. 제 1항에 있어서,The method of claim 1, 상기 제 2 연결부재는 상기 제2코어층의 타면에서 단차를 갖고 형성된 것을 특징으로 하는 반도체 패키지. The second connecting member is a semiconductor package, characterized in that formed with a step on the other surface of the second core layer. 청구항 1항의 구조를 가지며, 적어도 2개 이상이 스택된 단위 패키지들;및Unit packages having the structure of claim 1 and stacked at least two; and 상기 단위 패키지들 사이에 개재되는 본딩유지부재;Bonding holding members interposed between the unit packages; 를 포함하는 것을 특징으로 하는 스택 패키지.Stack package comprising a. 제 8항에 있어서,The method of claim 8, 상기 본딩유지부재는 경화성 본딩 시트로 이루어진 것을 특징으로 하는 스택 패키지.The bonding holding member is a stack package, characterized in that consisting of a curable bonding sheet.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110447102A (en) * 2017-03-15 2019-11-12 东芝存储器株式会社 Semiconductor storage

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110447102A (en) * 2017-03-15 2019-11-12 东芝存储器株式会社 Semiconductor storage
CN110447102B (en) * 2017-03-15 2024-03-05 铠侠股份有限公司 Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell

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