KR20100087517A - Frequency down-converter for wibro base-station system and method of frequency down-converting for the same - Google Patents

Abstract

PURPOSE: A frequency down-converter for a WiBro(Wireless Broadband) base-station system and a method of frequency down-converting for the same are provided to improve the procedures of frequency conversion, lower pass filtering and decimation for a WiBro intermediate frequency signal which is oversampled. CONSTITUTION: Mixers(101) perform frequency down-conversion by mixing an oversampled sampling data stream received from channels with an intermediate frequency signal received form an intermediate frequency generator. A decimation tab loader(211) comprises shift registers. The shift register receives a frequency down-converted sampling data stream from a corresponding mixer to output sampling data from the sampling data stream. A multiplexer(212) receives and outputs the sampling data from the shift register in order.

Description

Frequency downconversion device and frequency downconversion method for WiBro base station system {FREQUENCY DOWN-CONVERTER FOR WIBRO BASE-STATION SYSTEM AND METHOD OF FREQUENCY DOWN-CONVERTING FOR THE SAME}

The present invention relates to a downconversion device applied to a WiBro base station system, and more particularly, to a downlink path corresponding to a heterogeneous RE (Radio Equipment) of a WiBro base station system supporting the Common Public Radio Interface (CPRI) standard. The present invention relates to a frequency downconversion device and a frequency downconversion method for processing operations such as intermediate frequency conversion and filtering.

With the maturity of the high-speed wired internet market, users' desire to access high-speed Internet services anytime, anywhere, while on the move and on the move is increasing, so the convenience of service connection, the integration of wired / wireless communication networks, and multimedia WiBro exists as a system newly introduced as a request for a service (collectively, 'WiBro' is a technology similar to OFDM-based mobile WiMAX as defined in IEEE 802.16, and hereinafter referred to as Mobile WiMax in the present specification. Note that the term is used synonymously with

However, in order for new communication systems such as WiBro to rapidly spread to the market, there is a need for a method of utilizing base station and wired / wireless network resources used in 3GPP WCDMA, which is a third generation mobile communication network in which a global network is formed.

In order to provide such a method, industry cooperative organizations such as the Common Public Radio Interface (CPRI) have been formed with the aim of defining a publicly available specification for the main internal interface of a wireless base station.

For example, in CPRI, a base station system is divided into RECs (Radio Equipment Control) and REs (Radio Equipment), and the ultimate purpose is to enable compatible use between RECs and REs between heterogeneous communication systems.

As one example, the REC may be configured to correspond to the WiBro system, but the RE may be recyclable to correspond to a 3GPP WCDMA system that is conventionally installed. At this time, in order to use WiBro REC and recycle the 3GPP WCDMA RE, an up / down converter module is required between them.

1 is a block diagram illustrating a configuration of a downlink frequency conversion apparatus of a conventional WiBro base station system.

That is, FIG. 1 corresponds to a block diagram for exemplarily describing a downconverting device among the uplink and downconverting devices existing between WiBro REC and 3GPP WCDMA RE.

One WiBro cell can be configured with a total of three sectors and two antennas per sector (for MIMO support for antenna diversity and spatial multiplexing), and one antenna is composed of I and Q channels. From WiBro REC, input signals for a total of 12 channels are passed to the RE. The frequency downconversion device illustrated in FIG. 1 illustrates a frequency downconversion device corresponding to one channel of twelve channels.

Referring to FIG. 1, the conventional downlink frequency converter 100 includes a mixer 101, a low pass filter 103, and a decimator 104.

The mixer 101 receives the WiBro signal from the WiBRO REC. For the 8.75 MHz (10 MHz) OFDMA channel bandwidth, the mixer 101 samples per second (10 Msps) upconverted to an intermediate frequency (IF) of the 15 MHz band. In order to reduce aliasing, a 60Msps signal is input, which is generally oversampled six times.

At this time, the mixer 101 receives an intermediate frequency 15 MHz band signal from the IF frequency generator 102, which is a local oscillator (LO), and mixes it with a signal input from the WiBro REC to downward the signal of the 10 MHz band. Will be converted.

The low pass filter (LPF) 103 after the mixer 101 is an essential component to be provided at the rear end of the mixer in such a frequency downconversion, and an image frequency component output from the mixer. The image filter corresponds to an image filter for outputting only a desired down-converted frequency component by eliminating. In other words, the signal after the mixer is down-converted with twice the IF component and the spurious components of the previous stage, so that the spurious components, which are unwanted frequency signals, are responsible for RF signal processing. In this case, the performance of the RF stage can be severely degraded by being affected by a feedback loop or causing intermodulation between harmonics. To reduce this effect, lowpass filtering in the channel bandwidth is required for the baseband signal passing through the mixer stage.

Finally, the decimator 104 decimates the six times over-sampled signal from the WiBro REC to lower the sampling frequency to the original 10 Msps signal. That is, the decimator 104 enables efficient computation in hardware by lowering the sampling rate within a range where no aliasing occurs for 6 oversampled input data.

 Finally, the 10 MHz signal output from the decimator 104 is input to a mapper 110 to perform rate matching (10 MHz-> 3.84 MHz) between the WiBro device and the WCDMA UMTS, and is matched for the bandwidth of 3.84 MHz of the WCDMA. Sent to 3GPP WCDMA RE.

In the design of such a frequency downconversion device, the portion requiring the greatest complexity and chip design resources corresponds to the low pass filter 103.

In addition, as mentioned above, in order to support a total of 12 channels, 12 means that the frequency downconversion device 100 should exist for each base station and 12 low pass filters should also exist. In addition, since low pass filtering has to be performed on the 6 times oversampled 60Msps signal, there is a problem in that it takes a lot of cost and development time for designing a high speed circuit structure.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is a frequency downconversion device for supporting CPRI in a WiBro base station system, the frequency downconversion, lowpass filtering and decimation performed on an oversampled WiBro intermediate frequency signal. By improving a series of processing processes, the complexity of the low pass filter is reduced, and the low pass filtering of a plurality of channels that a base station needs to process can be processed in a time sharing manner using only one low pass filter configuration. It is to provide a frequency down converter.

Another object of the present invention for solving the above problems is a frequency downconversion method for supporting CPRI in a WiBro base station system, frequency downconversion, lowpass filtering and decimation performed on an oversampled WiBro intermediate frequency signal. The low pass filter complexity is reduced by improving the series of processing processes, and the low pass filtering for a plurality of channels to be processed by one base station can be processed in a time sharing manner using only one low pass filter configuration. The present invention provides a frequency downconversion method.

The present invention for achieving the above object is a downlink frequency down converter device applied to a WiBro base station system, N times (N is a natural number) from each of M channels (M is a plurality) M mixers that receive the oversampled sampling data stream, mix with the intermediate frequency signal received from the IF frequency generator, and down-convert the frequency, respectively corresponding to the M mixers, and frequency down from the corresponding mixers. A decimation tap loader comprising M shift registers each receiving the converted sampling data streams and sequentially outputting N pieces of sampling data from the received sampling data streams, and from the M shift registers of the decimation tap loaders. Multiplexer that sequentially receives and outputs N pieces of sampling data and taps as many taps as P A shift register corresponding to a series of N taps of the P shift registers, wherein the N pieces of sampling data sequentially output from the multiplexer are stored in the shift register corresponding to the N shift registers, and the N shift registers are simultaneously shifted. And time-divisionally process the sampling data stream of each of the M channels input through the M mixers, while storing the next N sampling data output from the multiplexer in a shift register corresponding to the series of N taps. A frequency downconversion device including a low pass filter is provided.

Here, the N-times oversampled sampling data stream received by the M mixers from a corresponding channel among the M channels may be an I channel or a Q channel of an output signal per antenna corresponding to the WiBro base station system.

In addition, the mixer is a digital mixer, the IF frequency generator is a local oscillator for generating an orthogonal sinusoidal intermediate frequency signal corresponding to the I channel or Q channel, the mixer is only +1 or -1 value from the output of the local oscillator The configured I component or Q component may be configured to multiply the N times oversampled sampling data stream received from the corresponding channel by only sign conversion without using a multiplication operation resource.

Here, the P shift registers included in the low pass filter may be configured to have a depth of M + N-1.

The present invention for achieving the above another object is a downlink frequency down converter method applied to a WiBro base station system, wherein N times (N is a natural number) from each of M channels (M is a plurality). Receiving an oversampled sampling data stream, mixing an intermediate frequency signal received from an intermediate frequency generator, down-converting the frequency, receiving the frequency down-converted sampling data streams, and receiving the received sampling data stream. Sequentially outputting N pieces of sampling data from the plurality of taps and the number of taps (P) shift registers, and sequentially outputting the N pieces of sampling data sequentially output to a series of N shift registers of the P shift registers. Store and shift the N shift registers simultaneously, from the multiplexer A low pass filtering step of time-divisionally processing the sampling data streams of each of the M channels input in the frequency downconverting step, while storing the next N sampling data output in the series of N shift registers. Provides a down conversion method.

Here, the N times oversampled sampling data stream input in the frequency downconversion step may be an I channel or a Q channel of an output signal per antenna corresponding to the WiBro base station system.

In this case, the frequency down-conversion step corresponds to the I component or Q component consisting of only +1 or -1 values from an IF frequency generator which is a local oscillator for generating an orthogonal sinusoidal intermediate frequency signal corresponding to an I channel or a Q channel. The N times oversampled sampling data stream received from a channel to be multiplied may be configured to be multiplied only by sign conversion without using a multiplication operation resource.

In the case of using the frequency downconversion device according to the present invention as described above, in the prior art downconversion device, different channels have to be provided with a low pass filter for each channel, but several channels share one low pass filter in time division ( With a sharing structure, the multiplication resource of the filter which occupies a relatively large chip area can be made efficient.

 Thus, in the case of constructing a WiBro base station system using the frequency downconversion device according to the present invention, since a low pass filter which must exist for each channel can be configured to be shared by several channels, the system complexity can be reduced. It can bring the effect of lowering the price.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an embodiment of a downlink frequency downconversion device of a WiBro base station system according to the present invention.

Referring to FIG. 2, the downlink frequency down-conversion device 200 of the WiBro base station system according to the present invention includes a mixer 101, a decimation tap loader 211, a multiplexer 212, and a low pass filter 220. It can be configured to include.

First, the mixer 101 is referred to using the same reference numerals as the same components as the mixer 101 of the frequency down converter according to the prior art described with reference to FIG.

In the conventional frequency down converter described with reference to FIG. 1, one mixer 101, a low pass filter 103, and a decimator 104 have to correspond to each channel. There is only one mixer 101 and includes a decimation tap loader 211 and a multiplexer 212 that allow multiple channels (e.g., 12 channels) to operate by time-dividing one low pass filter 220. Can be configured.

That is, the mixer 101 illustrated in FIG. 2 is a necessary component per channel, and the decimation tap loader 211, the multiplexer 212, and the low pass filter 220 are components shared by several channels in time division. Corresponds to

As mentioned above, an object of the present invention is to perform the low pass filtering in the low pass filter for the signal over-sampled at 60Msps as described in the prior art illustrated in FIG. And to increase the area occupied in the chip.

That is, in the downlink frequency downconversion apparatus according to the present invention, the decimation is performed first before the lowpass filtering, not by performing the low pass filtering immediately after the mixer unit (), but by performing the decimation anyway. And a shift register for each tap of the low pass filter so as to time-division process the input data output from the plurality of channels to the low pass filter so that the low pass filtering of the plurality of channels may be time-divided. .

Therefore, in the conventional downconversion device, each low pass filter should be provided for each channel. However, the downconversion device according to the present invention has a structure in which several channels share a single lowpass filter in a time-division manner. Therefore, the multiplication resources of the filter which occupy a large chip area can be improved.

First, the mixer 101 receives a 60Msps signal six times oversampled from WiBro REC, receives a 15MHz intermediate frequency signal from the IF frequency generator 102, and mixes with a signal input from WiBro REC to 10MHz band. Downconvert to the signal of.

On the other hand, the mixer 101 multiplies orthogonal sinusoids (cos, sin) according to whether the signal input to the frequency downconversion device is an I (In-Phase) channel signal or a Q () channel signal to perform frequency downconversion. do.

In this case, when the digital 15 MHz IF data generated by the IF frequency generator 102 is sampled at 60 MHz, the I component that is actually multiplied is [-1, -1, +1, +1] / [+ according to the polarity value. 1, +1, -1, -1], and Q component is [+1, -1, -1, +1] because it is polarity symmetry. Therefore, if the digital mixer is designed in consideration of this point, it can be implemented by only sign change without a multiplier, which means that an efficient frequency down converter can be implemented without using a dedicated multiplication resource in the target FPGA. . This is also an efficient design method to improve the characteristics of the filter by increasing the number of possible taps of the FIR filter in the future.

3 is a block diagram illustrating a low pass filter and a decimation process applied to a frequency downconversion device according to the present invention.

Referring to FIG. 3, a configuration example of a low pass filter and decimation processing applied to a frequency downconversion device according to the present invention includes a component 302 for processing tap processing or coefficients processing, and an implementation of multichannel. It can be divided into a component 301 that handles multiplexing and shifting (MAS) and a component 303 that handles multiply and accumulation (MACC).

First, the MAS component 301 may reduce the required FIR operation for each channel by the number of multiple channels by applying the time division concept to the multi-channel signal input from the mixer. To achieve this, a fast operating clock is required, but the number of lowpass filters can be reduced, thereby reducing the overall chip area and complexity.

The component 301 for performing such multiplexing and shifting may be implemented by the decimation tap loader 211 and the multiplexer 212 in the frequency downconversion device 200 according to the present invention illustrated in FIG. 2. It may be described as corresponding to shift registers corresponding to the number of taps corresponding to the taps included in the pass filter.

The decimation tap loader 201 corresponds to the M mixers, respectively, and receives the sampling data streams frequency down-converted from the corresponding mixers, and outputs N pieces of sampling data sequentially from the input sampling data streams. A component containing two shift registers.

In addition, it is an element that sequentially receives and outputs N pieces of sampling data from the M sheet registers of the decimation tap loader.

4 is a block diagram illustrating in detail the decimation tab loader and multiplexer according to the present invention.

Referring to FIG. 4, the decimation tap loader 211 is configured to include shift registers 211-1,..., 211-12 as many as the number of channels (eg, 12) supported by the WiBro base station system. Can be. In this case, each shift register corresponding to the number of channels includes a shift register SRL16_16 having a size equal to the number of taps of the low pass filter to be described later and the number of bits (sampling quantization bits) of sampling data input from each channel. Can be.

 For example, the shift register 211-1 corresponding to the channel # 1 may sequentially receive and store sampling input data of the sampling input data stream 60Msps inputted from the channel # 1 and down-converted through the mixer 101. N sampling data at a time is output to the multiplexer 212 to move to the shift register corresponding to the tap of the low pass filter, which will be described later.

Table 1 below describes the operation of the decimation tap loader 211, the multiplexer 212 and the low pass filter 220 applicable to the downconversion device according to the present invention in detail. This can be explained through.

Referring to Table 1 below, a flowchart for processing filter input data is shown. Here, only the result of the decimation time point is taken and the values of the other time points are obsolete, so they are not put into the tap input of the filter operation. This optimization design method enables the implementation of multichannel Systolic FIR through time-division of parallel channels, which increases the DSP resource utilization for multiplication after multiplication.

TABLE 1

Sample time Decimation points Current tab value jump Next tab value -16 Tap16 -15 Tap15 -14 Tap14 -13 Tap13 -12 O Tap12 -11 Tap11 -10 Tap10 -9 Tap9 -> Tap15 -8 Tap8 -> Tap14 -7 Tap7 -> Tap13 -6 O Tap6 -> Tap12 -5 Tap5 -> Tap11 -4 Tap4 -> Tap10 -3 Tap3 -> Tap9 -2 Tap2 -> Tap8 -One Tap1 -> Tap7 0 O Tap0 -> Tap6 One Tap5 2 Tap4

This concept is illustrated in Table 1. In other words, six consecutive 16-bit sampling data are stacked from Tap0 to Tap5, and the next main clock (120MHz) takes a jumping structure in which values are skipped by six taps in consideration of six decimations. That is, the values stored in Tap0 through Tap5 are skipped by 6 taps and moved from Tap6 to Tap11.

Such an operation may be performed by sequentially inputting sampling data for each channel from the multiplexer 212 to the low pass filter 220.

5 is a block diagram for explaining a configuration example of a low pass filter according to the present invention.

Referring to FIG. 5, the MAS component (such as the number of multiple channels) may be reduced by applying the time division concept to the signal input of the multi-channel input from the mixer, which has been described with reference to FIG. Implementation is achieved by placing shift registers 502-1, ..., 502-16 between taps constituting the low pass filter to realize 301.

In addition, the low pass filter has components (501-1, ..., 501-16) that process multiply and accumulation (MACC) for each tap, and the MACC component of the last tap ( In 501-16, the filter output is finally output.

In this case, the depth (Dynamic Depth) of the shift registers (502-1, ..., 502-16) must be processed in a time division manner by the number of jumped taps (i.e., oversampling multiple N = decimation multiple) and the low pass filter. It may be determined in consideration of the number of the plurality of channels.

For example, the depth of the SRL32_16 component implemented by the shift registers 502-1,.

[Equation 1]

Shift register depth = Number of channels + decimation factor -1

For example, assuming the embodiment described with reference to FIGS. 1 and 2, since 12 channels are supported and the decimation factor is 6, the depths of the shift registers 502-1,. Becomes 17.

6 and 7 are graphs illustrating the magnitude response and the impulse response of the low pass filter applied to the frequency downconversion device according to the present invention.

Referring to FIGS. 6 and 7, it can be seen that it has excellent ripple characteristics in a pass band.

On the other hand, in the above-described low pass filter, the filter is configured with 16 taps, but it is apparent that a configuration of 32 taps or more is possible in consideration of an environment in which more spurious components are included.

Finally, the 10 MHz signal output from the downconversion device 200 through the low pass filter 220 is input to a mapper 110 to perform rate matching (10 MHz-> 3.84 MHz) between the WiBro device and the WCDMA UMTS. Matched for 3.84MHz bandwidth of WCDMA and sent to 3GPP WCDMA RE. Mapper 110 is cited using the same reference numerals as the same components as the prior art mapper 110 described with reference to FIG. 1.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

1 is a block diagram illustrating a configuration of a downlink frequency conversion apparatus of a conventional WiBro base station system.

2 is a block diagram illustrating an embodiment of a downlink frequency downconversion device of a WiBro base station system according to the present invention.

3 is a block diagram illustrating a low pass filter and a decimation process applied to a frequency downconversion device according to the present invention.

4 is a block diagram illustrating in detail the decimation tab loader and multiplexer according to the present invention.

5 is a block diagram for explaining a configuration example of a low pass filter according to the present invention.

6 and 7 are graphs illustrating the magnitude response and the impulse response of the low pass filter applied to the frequency downconversion device according to the present invention.

<Description of Major Symbols Used in Drawings>

200: frequency down converter

211: Decimation Tab Loader 212: Multiplexer

220: low pass filter

Claims (7)

A downlink frequency down converter device applied to a WiBro base station system, M (M is a plurality) M (N is a natural number) received from each of the channels over-sampled sampling data streams are input, M (M) which down-converts the frequency by mixing with the intermediate frequency signal received from the intermediate (IF) frequency generator mixer; A decimation including M shift registers respectively corresponding to the M mixers and receiving the frequency down-converted sampling data streams from the corresponding mixers and sequentially outputting N pieces of sampling data from the received sampling data streams. Tap loader; A multiplexer for receiving and outputting N pieces of sampling data sequentially from M sheet registers of the decimation tap loader; And A shift register corresponding to each tap as many taps as P, and storing N sampling data sequentially output from the multiplexer in a shift register corresponding to a series of N taps among the P shift registers, Shifting the N shift registers simultaneously and storing the next N sampling data output from the multiplexer in a shift register corresponding to the series of N taps, each of the M channels input through the M mixers Frequency downconversion device including a lowpass filter for time-division processing of sampling data streams. The method of claim 1, N-times oversampled sampling data streams received by the M mixers from corresponding channels among the M channels are I or Q channels of signals output per antenna corresponding to the WiBro base station system. Converter. The method of claim 2, The mixer is a digital mixer, the IF frequency generator is a local oscillator for generating an orthogonal sinusoidal intermediate frequency signal corresponding to the I channel or Q channel, The mixer multiplies an I component or Q component consisting of only +1 or -1 values from the output of the local oscillator to an N times oversampled sampling data stream received from the corresponding channel using only sign conversion without using multiplication operation resources. Frequency downconversion device, characterized in that. The method of claim 1, And the P shift registers of the low pass filter have an M + N-1 depth. A downlink frequency down converter method applied to a WiBro base station system, Receiving down-sampled sampling data streams N times (N is a natural number) from each of M channels (N is a plurality of channels), mixing the intermediate frequency signals received from an intermediate frequency generator, and down-converting the frequencies; Receiving the frequency down-converted sampling data streams and sequentially outputting N pieces of sampling data from the received sampling data streams; And By using the shift register equal to the number of taps (P), the N-sampling data sequentially output is stored in a series of N shift registers among the P shift registers, and the N shift registers are simultaneously shifted. A low pass filtering step of time-division processing the sampling data streams of each of the M channels input in the frequency down-conversion step, while storing the next N sampling data output from the multiplexer in the series of N shift registers; Frequency downconversion method included. The method of claim 5, And the N times oversampled sampling data stream input in the frequency downconversion step is an I channel or a Q channel of an output signal per antenna corresponding to the WiBro base station system. The method of claim 6, In the frequency downconverting step, an I component or a Q component including only +1 or -1 values is generated from the IF frequency generator, which is a local oscillator for generating an orthogonal sinusoidal intermediate frequency signal corresponding to an I channel or a Q channel. And multiplying the N times oversampled sampling data stream received from the multiplication using only sign conversion without using a multiplication operation resource.

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