KR20080050858A - Scan chain test method by function logic - Google Patents

Abstract

A scan chain test method using a function logic is provided to improve reliability of scan chain test by finding accurate error position in a scan chain. According to a method for testing a scan chain(20), test data bits are outputted by inputting data bits into a function logic(10). The test data bits are stored in the scan chain. The data stored in the scan chain are outputted. The test data bits and the data outputted from the scan chain are compared. The test data bits are stored in scan chain cells(24) of the scan chain in parallel.

Description

SCAN CHAIN TEST METHOD BY FUNCTION LOGIC}

1 is a diagram illustrating a connection between a general functional logic and a scan chain;

2 exemplarily illustrates a general scan chain inspection method;

3 shows an exemplary scan chain inspection method according to the present invention;

4 is a flowchart showing a scan chain inspection method according to the present invention in order.

The present invention relates to a method for inspecting a semiconductor integrated circuit device, and more particularly, to a method for inspecting a scan chain using functional logic.

As the high density integrated circuit design and processing technology has been rapidly developed in recent years, the density and complexity of the circuit has been greatly increased. As a result, the cost of inspection to determine whether the completed high-density integrated circuit system is operating normally is greatly increased. Testing to ensure the perfect operation of the finished system is just as important as the perfect design to meet the design specifications. Therefore, Design For Testability (DFT) was introduced as a technique to easily test from the design stage.

Most microprocessors and microcontrollers developed in recent years are almost impossible to test themselves, so various testing design methods are widely applied from the initial design stage. In order to efficiently test a circuit, a design method that considers various testing needs to be used according to the characteristics of the circuit, and a technique that minimizes the overhead imposed such as deterioration in performance and increase in area required must be applied.

Testing-oriented design methods are made by modifying a given circuit or adding extra hardware to make testing easier. However, when the testing design method is applied, the circuit size, the number of input / output terminals, and the performance deterioration are additionally caused. However, compared to these side effects, the benefit of the testing design method, such as test cost and test time reduction, is very large, and the testing itself is almost impossible unless the testing design method is applied to recently developed systems. It is utilized as.

Scan path design is one of several design techniques that considered testing. According to the scan path design, all of the memory elements (such as flip-flops) in the sequential circuits found in the component circuits of the semiconductor integrated circuit device are designed to form a series of linked shift registers as long as their fault diagnostic tests are performed. Is designed. Using fault diagnostic tests based on the scan path technique, the bit shift operation of the above shift register is used to continuously supply desired fault diagnostic test data for every memory element found in the component circuit of a semiconductor integrated circuit device. do. In addition, when the component circuits actually operate according to such test data, the contents stored and held in the respective memory elements are successively output using the bit shift operation of the shift registers as described above. The bit shift path of such shift registers is called the scan path.

Due to the emergence of various techniques for automatic test pattern generation, test pattern generation for a combination circuit is relatively easy. However, many automatic test pattern generation techniques have not been applied to sequential circuits. The scan technique makes it easy to control the memory elements that form the basis of a sequential circuit from the outside in a test mode.

1 is a diagram illustrating a connection relationship between a general functional logic 10 and a scan chain 20.

The functional logic 10 may be a combination circuit or a sequential circuit. There is a multiplexer in the feedback path of the functional logic 10. And flip-flops are connected and the multiplexer and flip-flops make up the scan chain 20. Flip-flops store data and the multiplexer chooses a normal mode path or a scan mode path.

In the embodiment, when 0 is input to the select terminal of the multiplexer, the output of the function logic 10 forms a normal path fed back to the input of the function logic 10, and when 1 is input to the select terminal of the multiplexer, each flip-flop They are connected in series to form a scan path. Through this, there is an advantage in that the function logic 10 can be checked for errors only by the scan in and scan out terminals without a plurality of external connection terminals.

However, in such a scan technique, when there is an error on the scan chain 20 that is woven to detect an error on the functional logic 10, there is a problem that it is difficult to find the exact location of the error due to the serial connection characteristics of the scan chain 20. This problem is illustrated in FIG.

2 is a diagram illustrating a general scan chain inspection method.

Referring to FIG. 2, the scan data is first inputted through the scan in terminal during scan chain inspection. In the example shown in the figure, values 11001100 are sequentially input to the scan chain 20. However, if the fourth cell 24 of the scan chain 20 is fixed to zero (Stuck-At 0), the stored value from the first cell 21 to the fourth cell 24 is not due to the series connection nature of each cell. All zeros. Therefore, the value actually stored in the scan chain 20 is 11000000. In fact, when the simulation is performed with the values stored in the scan chain 20, an output value different from the simulation result value by the data originally intended to be input is obtained.

In the embodiment, in order to determine the normal scan chain, 01001101, which is a simulation value corresponding to 11001100, should be output through the scan out. However, since the data value is already changed during the data input into the scan chain (11001100-> 11000000), the corresponding simulation result also has a value (00000001) different from the expected value. Therefore, when comparing the expected value (01001101) and the simulation result value (00000001), the third cell (23) has a different value for the first time, so the third cell ( 23) will be mistaken for an error.

In addition, it is necessary to store the inspection data in the scan chain through the scan in prior to the scan chain inspection, which results in a long inspection time. In this embodiment, a total of eight clocks must be applied to store data in a total of eight scan chain cells 21 to 28.

It is an object of the present invention to provide a scan chain inspection method that finds the exact error location in the scan chain and improves the reliability of the scan chain inspection.

Another object of the present invention is to provide a scan chain inspection method which can reduce the time required for the scan chain inspection.

According to an aspect of the present invention for achieving the above-mentioned objects, a scan chain inspection method includes inputting data bits into functional logic to output test data bits, storing test data bits in a scan chain, and scanning Outputting the data stored in the chain, and comparing the test data bits with the data output from the scan chain.

In an exemplary embodiment, the test data bits are stored in parallel in scan chain cells of the scan chain.

In an exemplary embodiment, the data stored in the scan chain cells of the scan chain are output in series.

In an exemplary embodiment, the test data bits and the data output from the scan chain are compared sequentially from the first scan chain value.

The scan test method includes inputting basic input values into the functional logic; The functional logic generating a scan chain input value in response to the basic input value; Outputting a scan chain input value through scan out; And comparing the value output through the scan out with the scan chain input value.

Exemplary embodiments of the invention will be described in detail below on the basis of reference drawings.

3 is a view showing a scan chain inspection method according to the present invention.

Referring to FIG. 3, first, a basic input value is input to the functional logic 10, and the functional logic 10 outputs a simulation result in response to the basic input value. In the embodiment shown in FIG. 3, 11001100 is output as a simulation result value in response to the basic input value.

Under normal mode, simulation results are input in parallel to each scan chain cell 21-28. In the embodiment, the simulation result is input to each of the eight scan chain cells. For example, when the fourth scan chain cell 24 is fixed to 0 (Stuck-At 0), the value actually input is due to the serial characteristic of the scan chain. 11000100. Then, in order to output the value stored in the scan chain cell 20, the scan mode is selected so that each scan chain is connected in series. The selection of the scan mode is made by the selector terminal of the multiplexer. Thereafter, through the scan out, the values stored in the scan chain cell 20 are sequentially shifted and output in series through the scan pass.

The value output by the scan out is compared with the scan out expected value, in which case the scan out expected value is the same as the simulation result. Thus, in the embodiment the scan out expected value is 11001100. In the embodiment, the scan out output values output all zeros from the fourth value since the fourth scan chain cell 24 is fixed to zero. Therefore 00000100 is output. In this case, comparing the scan-out expected value with the scan-out output value, the fourth value is different, and the observation shows that there is a stuck-at 0 error in the fourth scan chain cell 24, which is a correct test result.

4 is a flowchart illustrating a scan chain inspection method according to the present invention in an inspection procedure.

Referring to FIG. 4, in operation S1, a basic input value is input to the functional logic.

In step S2, in response to the basic input value, the functional logic performs a simulation and outputs a simulation result corresponding to the basic input value. In this case, the simulation results are stored in parallel in each scan chain cell because they are in normal mode instead of scan mode. Therefore, the conventional technique takes less inspection time than the method of storing the inspection data serially through scan in.

In step S3, a scan mode is selected to output a value stored in each scan chain cell. In this case, a multiplexer constituting the scan chain cell is used.

In operation S4, data stored in the scan chain cell is sequentially output through scan out in synchronization with a clock applied to a flip-flop constituting the scan chain cell. This operation consists of applying clocks as many as the number of scan chain cells. In the embodiment there are eight scan chain cells and therefore eight clocks are required.

In step S5, it is determined whether data of all scan chain cells is output.

In step S6, the scan-out expectation value and the scan-out output value are compared. If the two values are the same, the step S7 determines that there is no error in the scan chain. If the two values are not the same, an error occurs in any part of the scan chain in the step S8. Diagnosis

Although the inspection method according to the present invention has been shown in accordance with the above description and drawings, this is merely an example, and various changes and modifications are possible without departing from the spirit and scope of the present invention.

In checking whether there is an error in the scan chain as described above,

By inputting the inspection data in parallel using functional logic instead of serially through scan in, the reliability of the scan chain inspection is improved by preventing an erroneous determination during the scan chain inspection due to an error in the scan chain.

In addition, compared to the conventional method of inputting an initial value into the scan chain, the present invention does not require a process of inputting an initial value, so the time required for inspection is short.

Among the existing scan chain inspection techniques, there is a technique that uses a dictionary and compares it with an output value and ranks and analyzes it. In the present invention, since a separate dictionary is not required, less memory is required.

Claims (4)

How to check the scan chain: Inputting data bits into the functional logic to output test data bits; Storing the test data bits in a scan chain; Outputting data stored in the scan chain; And Comparing the test data bits with data output from the scan chain. The method of claim 1, And said test data bits are stored in parallel in scan chain cells of said scan chain. The method of claim 2, And the data stored in the scan chain cells of the scan chain are output in series. The method of claim 3, wherein And comparing the test data bits with data output from the scan chain sequentially from an initial scan chain value.

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