KR20050002516A - Method for forming fine pattern of semiconductor device - Google Patents
Method for forming fine pattern of semiconductor device Download PDFInfo
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- KR20050002516A KR20050002516A KR1020030043896A KR20030043896A KR20050002516A KR 20050002516 A KR20050002516 A KR 20050002516A KR 1020030043896 A KR1020030043896 A KR 1020030043896A KR 20030043896 A KR20030043896 A KR 20030043896A KR 20050002516 A KR20050002516 A KR 20050002516A
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- Prior art keywords
- etching
- semiconductor device
- gas
- thin film
- fine pattern
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 7
- 238000004380 ashing Methods 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000007261 regionalization Effects 0.000 claims 1
- 239000007789 gas Substances 0.000 abstract description 18
- 229920000642 polymer Polymers 0.000 abstract description 10
- 239000004215 Carbon black (E152) Substances 0.000 abstract description 3
- 229930195733 hydrocarbon Natural products 0.000 abstract description 3
- 150000002430 hydrocarbons Chemical class 0.000 abstract description 3
- HJUGFYREWKUQJT-UHFFFAOYSA-N tetrabromomethane Chemical compound BrC(Br)(Br)Br HJUGFYREWKUQJT-UHFFFAOYSA-N 0.000 abstract 6
- 238000001020 plasma etching Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 3
- 125000001145 hydrido group Chemical group *[H] 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000006884 silylation reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
- G03F7/427—Stripping or agents therefor using plasma means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로서, 보다 상세하게는 ECR-RIBE(elelctron cyclotron resonance reactive ion beam etching) 식각장비로 높은 자기 바이어스 전압(high self bias voltage)을 사용하지 않고 InP 식각을 진행하는데 진행가스로 CBr4로 식각하고, O2가스로 폴리머 에싱(ashing)을 실시하여 표면데미지 감소, 하이드로기로 형성된 폴리머 미발생, 부드러운 표면을 만들 수 있는 반도체소자의 미세패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to InP etching without using a high self bias voltage as an ECR-RIBE (elelctron cyclotron resonance reactive ion beam etching) etching equipment. The present invention relates to a method of forming a fine pattern of a semiconductor device capable of reducing surface damage, not generating a polymer formed of a hydro group, and making a smooth surface by etching with CBr 4 as a progress gas and subjecting the polymer to ashing with O 2 gas. .
반도체의 높은 유용성 반도체 포톤 디바이스 및 집적회로(PICs)의 미세 및 복잡한 구조는 매우 중요하다. 특히, InP는 장파장영역(1.3∼1.6um)에서 위에서 언급된 디바이스의 기초 물질로서 중요하다. 그러나, 이러한 물질의 식각은 쉽지가 않다.High Availability of Semiconductors The fine and complex structures of semiconductor photon devices and integrated circuits (PICs) are very important. InP is particularly important as the base material of the above-mentioned device in the long wavelength region (1.3 to 1.6 um). However, etching of these materials is not easy.
종래에는 RIE(reactive ion etching)로 CH4/H2혼합가스로 식각을 실시하였으나 InP박막의 표면위에 금속성 인듐(indium)의 축적을 야기시킬 뿐만 아니라 이러한 문제를 해결하기 위해 CH4증가로 인듐 식각률을 증가시키려고 하면 표면위에 유기 폴리머가 증착되어 식각을 억제시킨다.Conventionally, etching was performed with CH 4 / H 2 mixed gas by RIE (reactive ion etching), but it causes not only the accumulation of metallic indium on the surface of the InP thin film but also the indium etching rate by increasing CH 4 to solve this problem. Attempting to increase the deposition of organic polymers on the surface inhibits etching.
유기 폴리머를 제거시키기 위해 O2, CO2등의 가스를 첨가하면 식각률이 상당히 감소할 뿐만 아니라 패턴 언더컷 현상도 발생되어 공정 처리(throughput) 및 디바이스 특성을 저하시키고 있다.The addition of gases such as O 2 and CO 2 to remove organic polymers not only significantly reduces the etch rate, but also results in pattern undercuts, thereby degrading throughput and device characteristics.
상기와 같은 문제점을 해결하기 위해 종래의 평행한 플레이트 RIE 시스템도 사용할 수 있으나 자기 바이어스 전압이 200 V이상이 나와 표면에 데미지를 유발시킨다.In order to solve the above problems, a conventional parallel plate RIE system can also be used, but the self bias voltage is more than 200 V to cause damage to the surface.
또한, 진행시 하이드로 기로 형성된 폴리머가 발생하기 때문에 보다 줄일 수 있는 새로운 케미스트리가 요구되고 개선된 식각장비와 공정기술이 요구된다.In addition, since a polymer formed of a hydro group is generated during the process, a new chemistry that can be further reduced is required, and improved etching equipment and process technology are required.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, ECR-RIBE(elelctron cyclotron resonance reactive ion beam etching) 식각장비로 높은 자기 바이어스 전압(high self bias voltage)을 사용하지 않고 InP 식각을 진행하는데 진행가스로 CBr4로 식각하고, O2가스로 폴리머 에싱(ashing)을 실시하여 표면데미지 감소, 하이드로기로 형성된 폴리머 미발생, 부드러운 표면을 만들 수 있는 반도체소자의 미세패턴 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, an InP etch without using a high self bias voltage (electron cyclotron resonance reactive ion beam etching) etching equipment ECR-RIBE To proceed, it is etched with CBr 4 as the progress gas and polymer ashing with O 2 gas to reduce the surface damage, no polymer formed with hydro groups, and to provide a method for forming a fine pattern of a semiconductor device. The purpose is.
도 1은 본 발명에 따른 반도체소자의 미세패턴 형성방법을 설명하기 위한 ECR-RIBE 플라즈마 식각시스템의 개략도,1 is a schematic diagram of an ECR-RIBE plasma etching system for explaining a method for forming a fine pattern of a semiconductor device according to the present invention;
도 2a 및 도 2b는 본 발명에 따른 반도체소자의 미세패턴 형성방법을 설명하기 위한 공정단면도.2A and 2B are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
31 : 하부층 33 : InP 박막31: lower layer 33: InP thin film
35 : 감광막패턴35: photosensitive film pattern
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 미세패턴 형성방법 은, 하부층상에 InP 박막을 형성하는 단계;Method for forming a fine pattern of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an InP thin film on the lower layer;
상기 InP 박막상에 감광막패턴을 형성하는 단계; 및Forming a photoresist pattern on the InP thin film; And
상기 감광막패턴을 배리어로 ECR-RIBE(elelctron cyclotron resonance reactive ion beam etching)장비에서 CBr4가스와 O2가스를 이용하여 상기 InP 박막을 식각하는 단계를 포함하여 구성되는 것을 특징으로한다.And etching the InP thin film using CBr 4 gas and O 2 gas in an ECR-RIBE (elelctron cyclotron resonance reactive ion beam etching) apparatus using the photoresist pattern as a barrier.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 미세패턴 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 반도체소자의 미세패턴 형성방법을 설명하기 위한 ECR-RIBE 플라즈마 식각시스템의 개략도이다.1 is a schematic diagram of an ECR-RIBE plasma etching system for explaining a method of forming a fine pattern of a semiconductor device according to the present invention.
도 2a 및 도 2b는 본 발명에 따른 반도체소자의 미세패턴 형성방법을 설명하기 위한 공정단면도이다.2A and 2B are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 미세패턴 형성방법은, 도 1에 도시된 ECR-RIBE장비에서 CBr4식각과 O2의 에싱(ashing)을 이용하여 InP를 식각하는데, 식각장비 자체가 높은 자기 바이어스 전압(self bias voltage) (200V 이상)을 사용하지 않기 때문에 표면 데미지를 상당히 감소시킬 수 있다. 여기서, 미설명부호 1은 식각챔버, 3은 ECR 플라즈마지역, 5는 이온빔, 7은 라디칼 빔, 11은 시료, 9는 마그네트 코일, 13은 준비챔버, 15은 터보펌프, 17는 건조챔버, 19는 유량조절기, 21는 유량밸브, 23은 컴퓨터이다.In the method of forming a micropattern of a semiconductor device according to the present invention, InP is etched by using CBr 4 etching and ashing of O 2 in the ECR-RIBE device shown in FIG. 1, and the etching device itself has a high self bias voltage. Since it does not use (self bias voltage) (above 200V) it can significantly reduce the surface damage. Here, reference numeral 1 denotes an etch chamber, 3 denotes an ECR plasma region, 5 denotes an ion beam, 7 denotes a radical beam, 11 denotes a sample, 9 denotes a magnet coil, 13 denotes a preparation chamber, 15 denotes a turbopump, 17 denotes a drying chamber, and 19 Is the flow regulator, 21 is the flow valve and 23 is the computer.
이러한 조건에서 문제가 되었던 하이드로 기 폴리머는 새로운 케미스트리인 CBr4를 이용하여 그 발생을 방지할 수 있고, CBr4로 식각을 하면 매끄러운 표면을 만들 수 있으며, CBr4에 약간의 O2첨가시에 폴리머 제거효과도 있어 식각속도를 증가시킬 수 있다.Dihydro-based polymer in such a condition that was a problem that it is possible to prevent the occurrence with the new chemistry of CBr 4, when the etching as CBr 4 can create a smooth surface, some of the O 2 polymer upon addition of the CBr 4 There is also a removal effect can increase the etching rate.
또한, 새로운 케미스트리의 기타 가스로 Cl 기를 함유한 가스로 식각을 할 수 있으나 부식(corrosion), 장비 및 환경데미지도 있는 것을 감안하면 CBr4는 더욱 잇점이 있는 가스이다.In addition, other gases in the new chemistry can be etched with a Cl-containing gas, but CBr 4 is a more advantageous gas, given corrosion, equipment and environmental damage.
InP 식각시에 감광막과의 선택비가 부족하면 건조 현상(dry develop)인 3중 레지스트 또는 실릴레이션에 의한 상부표면 이미지 공정을 이용하여 보완하면 된다.If the selectivity with the photoresist film is insufficient at the time of InP etching, it can be compensated by using a triple surface resist process, which is a dry develop triple resist or silylation.
상기 도 1에 도시된 ECR-RIBE장비를 이용한 반도체소자의 미세패턴 형성방법에 대해 도 2a 및 도 2b를 참조하여 설명하면, 도 2a에 도시된 바와같이, 하부층(31)상에 InP 박막(33)을 증착한후 그 위에 상기 InP 박막(33)상에 감광물질층을 도포한후 이를 포토리소그라피 공정기술에 의한 노광 및 현상공정을 거친후 패터닝하여 감광막패턴(35)을 형성한다.A method of forming a fine pattern of a semiconductor device using the ECR-RIBE device illustrated in FIG. 1 will be described with reference to FIGS. 2A and 2B. As shown in FIG. 2A, an InP thin film 33 is formed on a lower layer 31. ), After the photosensitive material layer is applied on the InP thin film 33, and subjected to the exposure and development process by the photolithography process technology and then patterned to form a photosensitive film pattern 35.
그다음, 도 2b에 도시된 바와같이, 도 1의 ECR-RIBE장비내에서 상기 감광막패턴(35)을 배리어로 CBr4가스와 O2가스를 이용하여 상기 InP 박막(33)을 식각한다. 이때, 수소(H) 기를 사용하지 않으므로써 하이드로카본(hydrocarbon) 폴리머 발생을 방지할 수 있고 표면이 매끄러워질 뿐만 아니라 자기 바이어스를 사용하지 않기 때문에 표면 및 측벽에 데미지가 없게 된다.Next, as shown in FIG. 2B, the InP thin film 33 is etched using CBr 4 gas and O 2 gas as the barrier of the photoresist pattern 35 in the ECR-RIBE device of FIG. 1. In this case, by not using a hydrogen (H) group it is possible to prevent the generation of a hydrocarbon (hydrocarbon) and smooth the surface and does not use a magnetic bias there is no damage to the surface and sidewalls.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 미세패턴 형성방법에 의하면, ECR-RIBE(elelctron cyclotron resonance reactive ion beam etching) 식각장비로 높은 자기 바이어스 전압(high self bias voltage)을 사용하지 않고 InP 식각을 진행하는데 진행가스로 CBr4로 식각하고, O2가스로 폴리머 에싱(ashing)을 실시하여 표면데미지 감소, 하이드로기로 형성된 폴리머 미발생, 부드러운 표면을 만들 수 있다.As described above, according to the method for forming a micropattern of a semiconductor device according to the present invention, an EP-elebe (elelctron cyclotron resonance reactive ion beam etching) etching equipment is used without InP without high self bias voltage The etching process is performed by etching with CBr 4 as the progress gas and polymer ashing with O 2 gas to reduce surface damage, non-hydrogenated polymer, and create a smooth surface.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030043896A KR20050002516A (en) | 2003-06-30 | 2003-06-30 | Method for forming fine pattern of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030043896A KR20050002516A (en) | 2003-06-30 | 2003-06-30 | Method for forming fine pattern of semiconductor device |
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| KR20050002516A true KR20050002516A (en) | 2005-01-07 |
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2003
- 2003-06-30 KR KR1020030043896A patent/KR20050002516A/en not_active Application Discontinuation
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