KR20040083191A - Method for forming STI having vertical profile - Google Patents

Method for forming STI having vertical profile Download PDF

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KR20040083191A
KR20040083191A KR1020030017763A KR20030017763A KR20040083191A KR 20040083191 A KR20040083191 A KR 20040083191A KR 1020030017763 A KR1020030017763 A KR 1020030017763A KR 20030017763 A KR20030017763 A KR 20030017763A KR 20040083191 A KR20040083191 A KR 20040083191A
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polysilicon
layer
pattern
film
trench
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KR1020030017763A
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Korean (ko)
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이병석
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주식회사 하이닉스반도체
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Publication of KR20040083191A publication Critical patent/KR20040083191A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

PURPOSE: A method for forming an isolation layer is provided to prevent well punch by forming vertically STI(Shallow Trench Isolation) profile using a polysilicon mask pattern. CONSTITUTION: A pad oxide layer, a pad nitride layer and a polysilicon layer are sequentially formed on a semiconductor substrate(31). A polysilicon pattern is formed by selectively etching the polysilicon layer. A trench is formed by over etching of the pad nitride layer, the pad oxide layer and the substrate using the polysilicon pattern as a mask. An isolation layer(43) is then formed in the trench.

Description

수직한 프로파일을 갖는 소자분리막 형성방법{Method for forming STI having vertical profile}Method for forming a device isolation layer having a vertical profile {Method for forming STI having vertical profile}

본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로서, 보다 상세하게는 반도체소자에서 폴리실리콘 마스크패턴을 사용하여 STI(shallow trench isolation) 프로파일을 수직하게 형성하여 웰펀치(well punch)를 방지할 수 있는 수직한 프로파일을 갖는 반도체소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method for forming a device isolation layer of a semiconductor device, and more particularly, to form a shallow trench isolation (STI) profile vertically using a polysilicon mask pattern in a semiconductor device to prevent well punch. A device isolation film forming method of a semiconductor device having a vertical profile.

에스램 반도체소자는 디램 디바이스와 달리 일반적으로 래치-업 문제 및 웰 펀치문제를 막기 위해 트렌치 깊이를 깊게 형성하고 있다.Unlike DRAM devices, SRAM semiconductor devices generally form deep trench depths to prevent latch-up problems and well punch problems.

그러나, 트렌치 깊이를 깊게 형성하여 실리콘기판의 스트레스 문제로 인해 리키지가 증가하는 문제가 있다.However, since the trench depth is deeply formed, there is a problem in that the liquidity increases due to the stress problem of the silicon substrate.

따라서, 이러한 문제를 막기 위해 적당한 선에서 트렌치 깊이를 형성한다. 또한, 현재의 일반적인 방법으로 트렌치 프로파일을 형성하면, 슬로프 프로파일(slope profile)을 피하기가 어렵다. 경사진 트렌치 프로파일은 향후의 웰 형성공정이후에 웰간의 거리가 가까워지는 문제가 존재하여 웰펀치 문제가 종종 발생한다.Therefore, to avoid this problem, the trench depth is formed at an appropriate line. In addition, if the trench profile is formed by the current general method, it is difficult to avoid the slope profile. Inclined trench profiles have a problem that the distance between the wells is close after the well-forming process in the future, so the well punch problem often occurs.

종래의 일반적인 에스램 소자에 있어서의 소자분리막 형성방법에 대해 도 1a 내지 도 1d를 참조하여 설명하면, 먼저 도 1a에 도시된 바와같이, 실리콘기판(11)상에 패드산화막(13)과 패드질화막(15)을 증착한후 상기 패드질화막(15)상에 소자분리 형성용 마스크패턴(17)을 형성한다.A method of forming a device isolation film in a conventional general SRAM device will be described with reference to FIGS. 1A to 1D. First, as shown in FIG. 1A, a pad oxide film 13 and a pad nitride film on a silicon substrate 11 are described. After depositing (15), a mask pattern 17 for forming device isolation is formed on the pad nitride film 15.

그다음, 도 1b에 도시된 바와같이, 상기 소자분리 형성용 마스크패턴(17)을 식각마스크로 패드질화막(15)과 패드산화막(13) 및 실리콘기판(11)을 순차적으로 식각하여 소자분리용 트렌치(19)을 형성한후 소자분리패턴 형성용 마스크패턴(17)을 제거한다.Next, as shown in FIG. 1B, the isolation layer trench is sequentially etched by using the mask pattern 17 for forming the isolation layer as an etch mask. The pad nitride layer 15, the pad oxide layer 13, and the silicon substrate 11 are sequentially etched. After forming (19), the mask pattern 17 for forming the device isolation pattern is removed.

이어서, 도면에는 도시하지 않았지만, 상기 공정진행후 소자분리 목적으로 상기트렌치(19)를 포함한 전체 구조의 상면에 트렌치산화막(미도시)을 증착하여 상기 트렌치(19)를 매립한다.Subsequently, although not shown in the figure, a trench oxide film (not shown) is deposited on the upper surface of the entire structure including the trench 19 for the purpose of device isolation after the process, and the trench 19 is buried.

그다음, 도 1c에 도시된 바와같이, 상기 트렌치산화막(미도시)에 CMP 공정을 진행하여 트렌치산화막패턴(21)을 형성한후 패드질화막(15) 및 패드산화막(13)을 제거한다.Next, as illustrated in FIG. 1C, the trench oxide layer pattern 21 is formed by performing a CMP process on the trench oxide layer (not shown), and then the pad nitride layer 15 and the pad oxide layer 13 are removed.

이어서, 도 1d에 도시된 바와같이, 상기 공정후 후속 웰공정과 임플란트공정을 진행하여 반도체기판(11)내에 P웰(23a)과 N웰(23b) 및 P형영역(25a)과 N형영역(25b)을 형성한다.Subsequently, as shown in FIG. 1D, a subsequent well process and an implant process are performed after the above process, so that the P well 23a, the N well 23b, the P-type region 25a, and the N-type region are formed in the semiconductor substrate 11. It forms 25b.

그러나, 종래기술에 의하면, 상기 패드질화막(15)과 패드산화막(13) 및 실리콘 기판(11) 식각시에 측벽에 폴리머가 형성되어 경사진 프로파일이 갖게 된다.However, according to the related art, polymers are formed on sidewalls during etching of the pad nitride layer 15, the pad oxide layer 13, and the silicon substrate 11 to have an inclined profile.

또한, 도 1d의 "A"에서와 같이, P웰과 N웰사이의 거리가 가까워 리키지로 인한 웰펀치 문제가 존재하게 된다.Also, as in " A " of FIG. 1D, the distance between the P well and the N well is so close that a well punch problem due to the liquid exists.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 반도체소자에서 폴리실리콘 마스크패턴을 사용하여 소자분리막 패턴 프로파일을 수직하게 형성하여 웰 펀치현상을 방지할 수 있는 수직한 프로파일을 갖는 소자분리막패턴 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, by using a polysilicon mask pattern in a semiconductor device to form a vertical pattern of the device isolation layer pattern having a vertical profile that can prevent the well punch phenomenon An object of the present invention is to provide a method of forming an isolation layer pattern.

도 1a 내지 도 1d는 종래기술에 따른 반도체소자 제조시의 소자분리막 형성방법을 설명하기 위한 공정 단면도.1A to 1D are cross-sectional views illustrating a method of forming a device isolation film in manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2e는 본 발명에 따른 반도체소자 제조시의 수직한 프로파일을 갖는 소자분리막 형성방법을 설명하기 위한 공정 단면도.2A to 2E are cross-sectional views illustrating a method of forming a device isolation film having a vertical profile when a semiconductor device is manufactured according to the present invention.

[도면부호의설명][Description of Drawing Reference]

31 : 실리콘기판 33 : 패드산화막31 silicon substrate 33 pad oxide film

35 : 패드질화막 37 : 폴리실리콘막35 pad nitride film 37 polysilicon film

39 : 감광막패턴 41 : 트렌치39: photoresist pattern 41: trench

43 : 소자분리막 45a : P 웰43: device isolation layer 45a: P well

45b : N 웰 47a : P형 영역45b: N well 47a: P-type region

47b : N형 영역47b: N-type region

상기 목적을 달성하기 위한 본 발명에 따른 수직한 프로파일을 갖는 소자분리막 형성방법은, 실리콘기판상에 패드질화막과 패드산화막 및 폴리실리콘 막을 순차적으로 형성하는 단계;A device isolation film forming method having a vertical profile according to the present invention for achieving the above object comprises the steps of sequentially forming a pad nitride film, a pad oxide film and a polysilicon film on a silicon substrate;

상기 폴리실리콘막을 선택적으로 제거하여 폴리실리콘막패턴을 형성하는 단계;Selectively removing the polysilicon film to form a polysilicon film pattern;

상기 폴리실리콘막패턴을 마스크로 상기 패드질화막과 패드산화막 및 실리콘기판을 순차적으로 과도식각하여 트렌치패턴을 형성하는 단계; 및Sequentially trenching the pad nitride layer, the pad oxide layer, and the silicon substrate using the polysilicon layer pattern as a mask to form a trench pattern; And

상기 트렌치패턴내에 소자분리막을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.And forming an isolation layer in the trench pattern.

(실시예)(Example)

이하, 본 발명에 따른 본 발명에 따른 수직한 프로파일을 갖는 소자분리막 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a device isolation film forming method having a vertical profile according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명에 따른 본 발명에 따른 수직한 프로파일을 갖는소자분리막 형성방법을 설명하기 위한 공정단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a device isolation film having a vertical profile according to the present invention.

본 발명에 따른 수직한 프로파일을 갖는 소자분리막 형성방법은, 도 2a에 도시된 바와같이, 실리콘기판(31)상에 패드산화막(33)과 패드질화막(35) 및 폴리실리콘막(37)을 차례로 증착한후 그 위에 소자분리패턴 형성용 감광막패턴(39)을 형성한다. 이때, 상기 패드산화막으로 열적 산화막을 이용하며, 적용 두께는 0∼200Å이 바람직하며, 상기 패드질화막으로는 Si3N4을 사용한다. 또한, 상기 폴리실리콘막으로는 언도프트 폴리실리콘 또는 비정질 폴리실리콘을 사용한다.In the method of forming a device isolation film having a vertical profile according to the present invention, as shown in FIG. 2A, a pad oxide film 33, a pad nitride film 35, and a polysilicon film 37 are sequentially formed on a silicon substrate 31. After the deposition, a photosensitive film pattern 39 for forming an isolation pattern is formed thereon. In this case, a thermal oxide film is used as the pad oxide film, and an application thickness is preferably 0 to 200 kPa, and Si 3 N 4 is used as the pad nitride film. In addition, an undoped polysilicon or an amorphous polysilicon is used as the polysilicon film.

그다음, 도 2b에 도시된 바와같이, 상기 소자분리패턴 형성용 감광막패턴(39)을 식각마스크로 상기 폴리실리콘막(37)을 선택적으로 제거하여 폴리실리콘막패턴(37a)을 형성한후 상기 감광막패턴(39)을 제거한다.Next, as shown in FIG. 2B, the polysilicon layer 37 is selectively removed by using the photoresist layer pattern 39 for forming the device isolation pattern as an etch mask to form the polysilicon layer pattern 37a, and then the photoresist layer. The pattern 39 is removed.

이어서, 도 2c에 도시된 바와같이, 상기 폴리실리콘막패턴(37a)을 식각마스크로 상기 패드질화막(35)과 패드산화막(33) 및 실리콘기판(31)을 식각하여 상기 실리콘기판(31)내에 소자분리용 트렌치(41)을 형성한다. 이때, 상기 트렌치(41) 형성시에 실리콘기판(31)이 식각되면서 상부의 폴리실리콘막패턴(37a)이 완전 제거되고, 패드질화막(35)도 일부 식각된다. 또한, 카본이 없는 폴리실리콘막을 하드마스크로 하여 식각하기 때문에 트렌치(41)측면벽에 폴리머(polymer)가 형성되지 않아 수직한 트렌치 프로파일을 얻게 된다. 또한, 상기 실리콘기판 식각시에 Cl2또는 HBr 가스를 포함한 가스를 사용한다.Subsequently, as shown in FIG. 2C, the pad nitride layer 35, the pad oxide layer 33, and the silicon substrate 31 are etched using the polysilicon layer pattern 37 a as an etch mask. A device isolation trench 41 is formed. At this time, as the silicon substrate 31 is etched when the trench 41 is formed, the upper polysilicon layer pattern 37a is completely removed, and the pad nitride layer 35 is partially etched. In addition, since a polysilicon film without carbon is etched as a hard mask, a polymer is not formed on the sidewalls of the trench 41, thereby obtaining a vertical trench profile. In addition, a gas containing Cl 2 or HBr gas is used when etching the silicon substrate.

그다음, 도면에는 도시하지 않았지만, 상기 공정진행후 소자분리 목적으로 상기트렌치(41)를 포함한 전체 구조의 상면에 트렌치산화막(미도시)을 증착하여 상기 트렌치(41)를 매립한다.Next, although not shown in the figure, a trench oxide film (not shown) is deposited on the upper surface of the entire structure including the trench 41 for the purpose of device isolation after the process, and the trench 41 is buried.

이어서, 도 2d에 도시된 바와같이, 상기 트렌치산화막(미도시)에 CMP 공정을 진행하여 트렌치산화막패턴(43)을 형성한후 패드질화막(35) 및 패드산화막(33)을 제거한다.Subsequently, as shown in FIG. 2D, the trench oxide layer pattern 43 is formed by performing a CMP process on the trench oxide layer (not shown), and then the pad nitride layer 35 and the pad oxide layer 33 are removed.

그다음, 도 2e에 도시된 바와같이, 상기 공정후 후속 웰공정과 임플란트공정을 진행하여 실리콘기판(31)내에 P웰(45a)과 N웰(45b) 및 P형영역(47a)과N형영역(47b)을 형성한다. 이때, "B"에서와 같이, 트렌치 프로파일이 수직하게 되어 P 웰과 N 웰사이의 거리가 어느 정도 확보되어 리키지로 인한 웰 펀치(well punch) 문제가 개선됨을 알 수 있다.Subsequently, as shown in FIG. 2E, subsequent well and implant processes are performed after the above process, so that the P wells 45a, N wells 45b, P-type regions 47a, and N-type regions are formed in the silicon substrate 31. It forms 47b. At this time, as in the "B", the trench profile is vertical to ensure that the distance between the P well and the N well to some extent it can be seen that the problem of the well punch (well punch) due to the liquidity is improved.

상기에서 설명한 바와같이, 본 발명에 따른 수직한 프로파일을 갖는 소자분리막 형성방법에 의하면, 트렌치 형성시에 폴리실리콘막패턴을 마스크로 식각공정을 진행하므로써 트렌치 측면벽에 폴리머 생성이 방지되므로써 소자분리막 형성시 프로파일을 수직하게 형성할 수 있어 추후 웰 형성 공정후에 웰 간의 스페이스 마진을 확보하여 웰 펀치 문제를 막을 수 있다.As described above, according to the method for forming a device isolation film having a vertical profile according to the present invention, the device isolation film is formed by preventing the formation of polymers in the trench sidewalls by performing an etching process using a polysilicon film pattern as a mask during trench formation. Since the eye profile can be formed vertically, a space margin between the wells can be secured after the well forming process, thereby preventing the well punch problem.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (6)

실리콘기판상에 패드질화막과 패드산화막 및 폴리실리콘막을 순차적으로 형성하는 단계;Sequentially forming a pad nitride film, a pad oxide film, and a polysilicon film on a silicon substrate; 상기 폴리실리콘막을 선택적으로 제거하여 폴리실리콘막패턴을 형성하는 단계;Selectively removing the polysilicon film to form a polysilicon film pattern; 상기 폴리실리콘막패턴을 마스크로 상기 패드질화막과 패드산화막 및 실리콘기판을 순차적으로 과도식각하여 트렌치패턴을 형성하는 단계; 및Sequentially trenching the pad nitride layer, the pad oxide layer, and the silicon substrate using the polysilicon layer pattern as a mask to form a trench pattern; And 상기 트렌치패턴내에 소자분리막을 형성하는 단계를 포함하여 구성되는 것을 특징으로하는 수직한 프로파일을 갖는 소자분리막 형성방법.Forming a device isolation film in the trench pattern; and forming a device isolation film in the trench pattern. 제1항에 있어서, 상기 패드산화막으로 열적 산화막을 이용하며, 적용 두께는 0∼200Å 인 것을 특징으로하는 수직한 프로파일을 갖는 소자분리막 형성방법.The method of claim 1, wherein a thermal oxide film is used as the pad oxide film, and an application thickness is 0 to 200 microseconds. 제1항에 있어서, 상기 패드질화막으로는 Si3N4을 사용하는 것을 특징으로 하는 수직한 프로파일을 갖는 소자분리막 형성방법.The method of claim 1, wherein the pad nitride layer is formed of Si 3 N 4 . 제1항에 있어서, 폴리실리콘막패턴으로는 언도프트 폴리실리콘 또는 비정질 폴리실리콘을 사용하는 것을 특징으로하는 수직한 프로파일을 갖는 소자분리막 형성방법.The method of claim 1, wherein an undoped polysilicon or an amorphous polysilicon is used as the polysilicon film pattern. 제1항에 있어서, 상기 실리콘기판 식각시에 상기 폴리실리콘막패턴이 동시에 제거되는 것을 특징으로하는 수직한 프로파일을 갖는 소자분리막 형성방법.The method of claim 1, wherein the polysilicon layer pattern is simultaneously removed when the silicon substrate is etched. 제1항에 있어서, 상기 실리콘기판 식각시에 Cl2또는 HBr 가스를 포함한 가스를 사용하여 식각하는 것을 특징으로하는 수직한 프로파일을 갖는 소자분리막 형성방법.The method of claim 1, wherein the silicon substrate is etched using a gas containing Cl 2 or HBr gas during etching of the silicon substrate.
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