KR20030050180A - A test pattern of a semiconductor device - Google Patents

A test pattern of a semiconductor device Download PDF

Info

Publication number
KR20030050180A
KR20030050180A KR1020010080579A KR20010080579A KR20030050180A KR 20030050180 A KR20030050180 A KR 20030050180A KR 1020010080579 A KR1020010080579 A KR 1020010080579A KR 20010080579 A KR20010080579 A KR 20010080579A KR 20030050180 A KR20030050180 A KR 20030050180A
Authority
KR
South Korea
Prior art keywords
gate oxide
gate electrode
gate
oxide film
mosfet
Prior art date
Application number
KR1020010080579A
Other languages
Korean (ko)
Inventor
김하중
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020010080579A priority Critical patent/KR20030050180A/en
Publication of KR20030050180A publication Critical patent/KR20030050180A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A test pattern of a semiconductor device is provided to protect MOSFET pattern by using a phenomenon that the current of a gate oxide layer increases suddenly with reducing the thickness of the gate oxide layer. CONSTITUTION: The test pattern of a semiconductor device comprises the first MOSFET having the first gate oxide layer(33) thick between the first gate electrode(37a) and a semiconductor substrate(31), including the first source/drain(39a,41a), and the second MOSFET having the second gate oxide layer(33) thin between the second gate electrode(37b) and the semiconductor substrate(31), including the first source/drain(39b,41b).

Description

반도체소자의 테스트 패턴{A test pattern of a semiconductor device}A test pattern of a semiconductor device

본 발명은 반도체소자의 테스트 패턴에 관한 것으로, 특히 MOSFET 테스트 패턴의 게이트산화막이 플라즈마 차징 손상 ( plasma charging demage ) 으로 부터 보호할 수 있도록 함으로써 상기 MOSFET 의 전기적 특성을 향상시켜 GIDL 특성을 평가할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern of a semiconductor device. In particular, the gate oxide layer of the MOSFET test pattern can be protected from plasma charging demage, thereby improving the electrical characteristics of the MOSFET to evaluate the GIDL characteristics. It's about technology.

도 1 은 종래기술에 따른 반도체소자의 테스트 패턴을 도시한 단면도이다.1 is a cross-sectional view showing a test pattern of a semiconductor device according to the prior art.

도 1를 참조하면, 상기 테스트 패턴은 반도체기판(11)상에 게이트전극(15)을 형성하되, 상기 게이트전극(15)과 반도체기판(11) 사이에 게이트산화막(13)이 개재되고, 상기 게이트전극(15) 이외의 활성영역에 소오스/드레인(17,19)이 구비되는 MOSFET 가 구비되고, 상기 트랜지스터와 병렬로 연결된 다이오드(11)를 형성한다.Referring to FIG. 1, in the test pattern, a gate electrode 15 is formed on a semiconductor substrate 11, and a gate oxide layer 13 is interposed between the gate electrode 15 and the semiconductor substrate 11. MOSFETs having source / drains 17 and 19 are provided in active regions other than the gate electrode 15, and a diode 11 connected in parallel with the transistor is formed.

이때, 상기 다이오드(11)는 플라즈마 차징 손상으로부터 MOSFET 의 게이트산화막(13)을 보호하기 위하여 게이트전극(15)와 다이오드(23)를 병렬 연결하였다.In this case, the diode 11 is connected to the gate electrode 15 and the diode 23 in parallel in order to protect the gate oxide film 13 of the MOSFET from plasma charging damage.

그러나, 상기 게이트산화막(13)의 누설전류 특성 평가시 다이오드의 접합 누설 전류가 비정상으로 클 경우 게이트 전류에 다이오드의 접합누설전류가 함께 측정되는 문제가 있다.However, there is a problem in that the junction leakage current of the diode is measured together with the gate current when the junction leakage current of the diode is abnormally large when the leakage current characteristic of the gate oxide layer 13 is evaluated.

또한, GIDL 측정을 할 경우에 게이트 전압을 소오스 전압보다 낮게 인가하므로 게이트와 같이 연결된 다이오드는 포워드 바이어싱 ( forming biasing ) 되는 문제가 있다.In addition, since the gate voltage is applied lower than the source voltage when the GIDL measurement is performed, the diode connected with the gate is forward biased.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 게이트산화막의 두께가 감소함에 게이트산화막의 전류가 급격하게 증가하는 현상을 이용하여 MOSFET 테스트패턴을 보호하는 반도체소자의 테스트 패턴을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention provides a test pattern of a semiconductor device that protects a MOSFET test pattern by using a phenomenon in which the current of the gate oxide film is rapidly increased while the thickness of the gate oxide film is reduced in order to solve the problems of the prior art. There is this.

도 1 은 종래기술에 따른 반도체소자의 테스트 패턴을 도시한 단면도.1 is a cross-sectional view showing a test pattern of a semiconductor device according to the prior art.

도 2 내지 도 3 은 본 발명에 따른 반도체소자의 테스트 패턴을 도시한 단면도 및 평면도.2 to 3 are cross-sectional views and plan views showing a test pattern of the semiconductor device according to the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11, 31 : 반도체기판13 : 게이트산화막11, 31: semiconductor substrate 13: gate oxide film

15 : 게이트전극17,19 : 소오스/드레인15: gate electrode 17, 19: source / drain

21 : 다이오드 확산층23 : 보호 다이오드21: diode diffusion layer 23: protection diode

33 : 제1게이트산화막35 : 제2게이트산화막33: first gate oxide film 35: second gate oxide film

37a : 제1게이트산화막37b : 제2게이트산화막37a: first gate oxide film 37b: second gate oxide film

39a,41a : 제1 소오스/드레인39b,41b : 제2 소오스/드레인39a, 41a: first source / drain 39b, 41b: second source / drain

43 : 활성영역45 : 금속배선43: active area 45: metal wiring

47 : 콘택47: contact

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 테스트 패턴은,In order to achieve the above object, the test pattern of the semiconductor device according to the present invention,

(a) 반도체기판의 일측에 구비되는 테스트 패턴인 제1 MOSFET ;(a) a first MOSFET which is a test pattern provided on one side of a semiconductor substrate;

(ⅰ) 상기 일측에 구비되는 제1게이트전극,(Iii) a first gate electrode provided at one side;

(ⅱ) 상기 일측과 제1게이트전극 사이에 개재되는 제1게이트산화막,(Ii) a first gate oxide film interposed between the one side and the first gate electrode,

(ⅲ) 상기 게이트전극의 끝부분에 일정폭 중첩되는 활성영역에 소오스/드레인이 구비되고,(Iii) a source / drain is provided in an active region that overlaps a predetermined width of the gate electrode;

(b) 상기 반도체기판의 타측에 구비되는 제2 MOSFET ;(b) a second MOSFET provided on the other side of the semiconductor substrate;

(ⅰ) 상기 타측에 구비되는 제2게이트전극,(Iii) a second gate electrode provided on the other side;

(ⅱ) 상기 타측과 제2게이트전극 사이에 개재되며 상기 제1게이트산화막보다 얇은 제2게이트산화막이 구비되고,(Ii) a second gate oxide film interposed between the other side and the second gate electrode and thinner than the first gate oxide film,

(c) 상기 제1게이트전극과 제2게이트전극이 병렬 연결된 것과,(c) the first gate electrode and the second gate electrode are connected in parallel;

(a) 에서 제1 MOSFET 의 제1 소오스/드레인 은 그라운드 ( ground ) 상태인 것과,In (a), the first source / drain of the first MOSFET is grounded,

(c) 에서 제1게이트전극과 제2게이트전극은 게이트전압이 인가되는 것을 특징으로 한다.In (c), the gate voltage is applied to the first gate electrode and the second gate electrode.

한편, 본 발명의 원리 및 동작원리는 다음과 같다.On the other hand, the principle and operation principle of the present invention are as follows.

1. 두꺼운 게이트산화막과 얇은 게이트산화막을 갖는 각각 두 개의 MOSFET 의 게이트전극이 배선을 통하여 병렬연결된 구조를 갖는다.1. The gate electrodes of two MOSFETs each having a thick gate oxide film and a thin gate oxide film are connected in parallel through wiring lines.

상기 얇은 게이트산화막을 갖는 MOSFET 는 기본적으로 MOS 구조를 가지며,소오스/드레인 영역은 없어도 무방하다.The MOSFET having the thin gate oxide film basically has a MOS structure, and may not have a source / drain region.

2. 본 발명에 따른 보호된 ( protected ) MOSFET 은 듀얼 게이트 산화막 공정 적용시에만 가능하며, 듀얼 게이트 산화막 형성 방법은 여러 가지가 있으나 본 발명의 요지와는 무관하여 논외로 한다.2. The protected MOSFET according to the present invention is possible only when the dual gate oxide process is applied, and there are various methods of forming the dual gate oxide, but it is not discussed regardless of the gist of the present invention.

3. 두꺼운 게이트산화막 MOSFET 는 공정 진행후 평가하고자 하는 소자이며, 얇은 게이트산화막 MOSFET 는 상기 두꺼운 게이트산화막 MOSFET 의 게이트산화막을 보호하는 기능을 갖는다.3. The thick gate oxide MOSFET is a device to be evaluated after the process, and the thin gate oxide MOSFET has a function of protecting the gate oxide of the thick gate oxide MOSFET.

반도체 제조 공정은 증착, 식각 등의 많은 고정에서 플라즈마 공정을 사용하는데, 이때 상기 플라즈마 공정의 특성상 플라즈마 차징 손상이 발생한다.The semiconductor manufacturing process uses a plasma process in many fixtures, such as deposition and etching, in which plasma charging damage occurs due to the characteristics of the plasma process.

상기 플라즈마 공정중 게이트에 플라즈마 중의 전하가 측정되어 게이트와 반도체기판 간에 전압이 인가되는데 이때 게이트에 인가된 전압은 게이트산화막에 걸리는 전압과 같으며 이로 인하여 FN ( fowler-Nordheim ) 터널링 전류가 발생하고, 결과적으로 게이트산화막의 절연성을 파괴한다. 즉, 게이트산화막에 비가역적인 손상을 준다.During the plasma process, the charge in the plasma is measured at the gate, and a voltage is applied between the gate and the semiconductor substrate. At this time, the voltage applied to the gate is equal to the voltage applied to the gate oxide film, which causes a fowler-nordheim tunneling current. As a result, the insulation of the gate oxide film is destroyed. That is, irreversible damage to the gate oxide film is caused.

그러나, 도 2와 같은 구조를 가질 경우 게이트에 전하가 축적되고 이로 인하여 게이트에 일정 전압, Vg 가 인가되더라도 대부분의 전류는 얇은 게이트산화막을 통하여 흐르게 된다.However, in the structure shown in FIG. 2, electric charges are accumulated in the gate, so that most of the current flows through the thin gate oxide film even when a constant voltage, Vg is applied to the gate.

즉, FN 터널링 전류는 Jox ∼ exp(-B*Tox/Vox)로 표현되기 때문에 게이트산화막의 두께(Tox)에 지수함수 의존성을 갖기 때문에 얇은 게이트 산화막에서는 두꺼운 게이트산화막에서 보다 훨씬 큰 전류가 흐른다.That is, since the FN tunneling current is expressed as Jox to exp (-B * Tox / Vox), the FN tunneling current has an exponential function dependency on the thickness of the gate oxide film Tox, so that a much larger current flows in the thin gate oxide film than in the thick gate oxide film.

결과적으로 얇은 게이트산화막 MOSFET 는 두꺼운 게이트산화막의 게이트 전류에 대한 우회경로 ( by-pass ) 역할을 한다.As a result, the thin gate oxide MOSFET serves as a by-pass to the gate current of the thick gate oxide.

따라서, 두꺼운 게이트산화막을 통하여 전류가 거의 흐르지 못하게 되므로 얇은 게이트 산화막은 플라즈마 차징 손상을 입지 않게 된다.Therefore, since the current hardly flows through the thick gate oxide film, the thin gate oxide film is not damaged by plasma charging.

4. 도 2 의 보호된 MOSFET에서 두꺼운 게이트산화막을 통하여 흐르는 누설전류를 측정할 경우 Vs=Vd=Vb=GND, Vg=inversion 모드에서 측정을 하면 얇은 게이트산화막 MOSFET 는 소오스/드레인 이 플로팅 ( floating ) 되어 있기 때문에 깊은 공핍 ( deep depletion ) 영역에 gm르게 되고 그로인하여 얇은 게이트산화막이 두꺼운 게이트산화막보다 얇기는 하지만 얇은 게이트산화막을 통해서는 전류가 거의 흐르지 않게 된다.4. In case of measuring leakage current flowing through the thick gate oxide film in the protected MOSFET of FIG. 2, when measuring in Vs = Vd = Vb = GND, Vg = inversion mode, the thin gate oxide MOSFET has a floating source / drain. As a result, it is in the deep depletion region, whereby a thin gate oxide film is thinner than a thick gate oxide film, but little current flows through the thin gate oxide film.

결과적으로 평가하고자 하는 두꺼운 게이트산화막을 통하여 흐르는 전류만을 측정할 수 있게 된다.As a result, only the current flowing through the thick gate oxide film to be evaluated can be measured.

5. 한편, GIDL 평가시에는 게이트에 소오스 보다 낮은 전압을 인가하게 되는데, 이때 얇은 게이트산화막 MOSFET 는 전류 경로를 형성하지 않으므로 보호된 다이오드를 사용하였을 경우에 다이오드가 포워딩 바이어싱 ( forwarding biasing ) 되는 등의 문제점이 유발되지 않는다.5. On the other hand, during GIDL evaluation, a lower voltage is applied to the gate than the source. At this time, since the thin gate oxide MOSFET does not form a current path, the diode is forwarding biased when the protected diode is used. Does not cause problems.

왜냐하면, 다이오드가 한 방향에 대해서만 절연특성을 보이는 반면에 게이트산화막은 양방향 모두에 대하여 절연특성을 보이기 때문이다.This is because the gate oxide film shows insulation properties in both directions while the diode shows insulation properties in only one direction.

도 2 는 본 발명에 따른 반도체소자의 테스트 패턴을 도시한 단면도이다.2 is a cross-sectional view illustrating a test pattern of a semiconductor device according to the present invention.

도 2 를 참조하면, 상기 테스트 패턴은 반도체기판(31) 상의 일측에 제1게이트전극(37a)을 형성하되, 상기 제1게이트전극(37a)과 반도체기판(31) 사이에 두꺼운 제1게이트산화막(33)이 개재되고, 상기 제1게이트전극(37a) 이외의 활성영역에 제1소오스/드레인(39a,41a)이 구비되는 제1 MOSFET 와,Referring to FIG. 2, the test pattern forms a first gate electrode 37a on one side of the semiconductor substrate 31, and has a thick first gate oxide layer between the first gate electrode 37a and the semiconductor substrate 31. A first MOSFET having 33 interposed therebetween and having first sources / drains 39a and 41a in active regions other than the first gate electrode 37a;

상기 제1 MOSFET 에 병렬로 연결되는 제2 MOSFET가 구비되되,A second MOSFET is provided in parallel with the first MOSFET,

상기 제2 MOSFET 는 상기 반도체기판(11)의 타측에 제2게이트전극(37b)을 형성하되, 상기 제2게이트전극(37a)과 반도체기판(31) 사이에 상기 제1게이트산화막(33) 보다 얇은 제2게이트산화막(35)이 개재되고, 상기 제2게이트전극(37b) 이외의 활성영역에 제2소오스/드레인(39b,41b)이 구비된다. 이때, 상기 제2소오스/드레인(39b,41b)은 생략될 수도 있다.The second MOSFET may form a second gate electrode 37b on the other side of the semiconductor substrate 11, but may be formed between the second gate electrode 37a and the semiconductor substrate 31 than the first gate oxide layer 33. A thin second gate oxide film 35 is interposed, and second sources / drains 39b and 41b are provided in an active region other than the second gate electrode 37b. In this case, the second source / drain 39b and 41b may be omitted.

도 3 은 상기 도 2 의 레이아웃도를 도시한 것으로서, 금속배선(45)으로 제1게이트전극(37a)과 제2게이트전극(27b)이 병렬 연결된 것을 도시한다.FIG. 3 illustrates the layout diagram of FIG. 2, in which the first gate electrode 37a and the second gate electrode 27b are connected in parallel with the metal line 45.

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 테스트 패턴은, GIDL 평가를 위하여 제1 게이트전극에 소오스 보다 낮은 전압을 인가하였을 때 종래기술과 같이 다이오드가 포워딩 바이어싱 ( forwarding biasing ) 되는 현상을 방지하여 GIDL 평가를 정확하게 실시할 수 있는 효과를 제공한다.As described above, the test pattern of the semiconductor device according to the present invention prevents a diode from forwarding biasing as in the prior art when a voltage lower than a source is applied to the first gate electrode for GIDL evaluation. It provides the effect of accurately performing GIDL evaluation.

Claims (3)

(a) 반도체기판의 일측에 구비되는 테스트 패턴인 제1 MOSFET ;(a) a first MOSFET which is a test pattern provided on one side of a semiconductor substrate; (ⅰ) 상기 일측에 구비되는 제1게이트전극,(Iii) a first gate electrode provided at one side; (ⅱ) 상기 일측과 제1게이트전극 사이에 개재되는 제1게이트산화막,(Ii) a first gate oxide film interposed between the one side and the first gate electrode, (ⅲ) 상기 게이트전극의 끝부분에 일정폭 중첩되는 활성영역에 소오스/드레인이 구비되고,(Iii) a source / drain is provided in an active region that overlaps a predetermined width of the gate electrode; (b) 상기 반도체기판의 타측에 구비되는 제2 MOSFET ;(b) a second MOSFET provided on the other side of the semiconductor substrate; (ⅰ) 상기 타측에 구비되는 제2게이트전극,(Iii) a second gate electrode provided on the other side; (ⅱ) 상기 타측과 제2게이트전극 사이에 개재되며 상기 제1게이트산화막보다 얇은 제2게이트산화막이 구비되고,(Ii) a second gate oxide film interposed between the other side and the second gate electrode and thinner than the first gate oxide film, (c) 상기 제1게이트전극과 제2게이트전극이 병렬 연결된 것을 특징으로 하는 반도체소자의 테스트 패턴.(c) The test pattern of the semiconductor device, characterized in that the first gate electrode and the second gate electrode is connected in parallel. 제 1 항에 있어서,The method of claim 1, (a) 에서 제1 MOSFET 의 제1 소오스/드레인 은 그라운드 ( ground ) 상태인 것을 특징으로 하는 반도체소자의 테스트 패턴.The test pattern of the semiconductor device according to (a), wherein the first source / drain of the first MOSFET is in a ground state. 제 1 항에 있어서,The method of claim 1, (c) 에서 제1게이트전극과 제2게이트전극은 게이트전압이 인가되는 것을 특징으로 하는 반도체소자의 테스트 패턴.The test pattern of the semiconductor device, characterized in that the gate voltage is applied to the first gate electrode and the second gate electrode in (c).
KR1020010080579A 2001-12-18 2001-12-18 A test pattern of a semiconductor device KR20030050180A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010080579A KR20030050180A (en) 2001-12-18 2001-12-18 A test pattern of a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010080579A KR20030050180A (en) 2001-12-18 2001-12-18 A test pattern of a semiconductor device

Publications (1)

Publication Number Publication Date
KR20030050180A true KR20030050180A (en) 2003-06-25

Family

ID=29575946

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010080579A KR20030050180A (en) 2001-12-18 2001-12-18 A test pattern of a semiconductor device

Country Status (1)

Country Link
KR (1) KR20030050180A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100664786B1 (en) * 2004-12-29 2007-01-04 동부일렉트로닉스 주식회사 Method of manufacturing test pattern for measuring damage caused by plasma induced charge
KR100896842B1 (en) * 2007-10-01 2009-05-12 주식회사 동부하이텍 Method for forming test pattern of gate ox integrity and test pattern structure for the gate ox integrity

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100664786B1 (en) * 2004-12-29 2007-01-04 동부일렉트로닉스 주식회사 Method of manufacturing test pattern for measuring damage caused by plasma induced charge
KR100896842B1 (en) * 2007-10-01 2009-05-12 주식회사 동부하이텍 Method for forming test pattern of gate ox integrity and test pattern structure for the gate ox integrity

Similar Documents

Publication Publication Date Title
US7728363B2 (en) Protective structure for semiconductor sensors
JPH07321318A (en) Protective device for semiconductor device
US6351362B1 (en) Protection circuit for an LCD controller IC
KR100369361B1 (en) Integration circuit with self-aligned silicided ESD protection transistors
US5962876A (en) Low voltage triggering electrostatic discharge protection circuit
US5949634A (en) Electrostatic discharge protection circuit triggered by MOS transistor
KR0175989B1 (en) Semiconductor device having internal circuit other than initial input stage circuit
KR20030050180A (en) A test pattern of a semiconductor device
US7898035B2 (en) Semiconductor device
US5561387A (en) Method for measuring gate insulation layer thickness
JP2006019671A (en) Electrostatic discharge protective device
US7282768B2 (en) MOS field-effect transistor
US6218705B1 (en) Semiconductor device having protective element to conduct current to substrate
Mishra et al. On the interaction of ESD, NBTI and HCI in 65nm technology
US6847082B2 (en) Semiconductor integrated device including an electrostatic breakdown protection circuit having uniform electrostatic surge response
US7843009B2 (en) Electrostatic discharge protection device for an integrated circuit
US5712492A (en) Transistor for checking radiation-hardened transistor
US6445601B1 (en) Electrostatic discharge protection circuit
KR970053847A (en) Antistatic circuit for semiconductor device and manufacturing method thereof
US5565692A (en) Insulated gate transistor electrostatic charge protection
KR100353529B1 (en) ESD protection device of semiconductor device
JP4006023B2 (en) Integrated circuit
Gill et al. Plasma induced damage on sub-0.5/spl mu/m MOSFETs using a CMOS driver as input protection
JPH0374870A (en) Semiconductor device
KR100476699B1 (en) Electrostatic discharge protection circuit and method of manufacturing the same

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination