KR102593450B1 - Organic Light Emitting Display Device - Google Patents

Abstract

The organic light emitting display device of the present invention has a pixel array including an OLED (Organic Light Emitting Diode) for each pixel, and a gate driver built into the panel that drives the pixel array. The pixel array includes a pixel TFT array in which a plurality of unit TFT (Thin Film Transistor) regions constituting one pixel are disposed, and a pixel light-emitting array in which a plurality of unit light-emitting regions constituting the one pixel are disposed. The pixel TFT array is located in a first area (AA) of the display panel, the panel-embedded gate driver is located in a second area (GA) outside the first area of the display panel, and the pixel light emitting array is: It is located in the first area AA and also in a part of the second area GA.

Description

Organic Light Emitting Display Device

The present invention relates to an organic light emitting display device.

The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, and has the advantages of fast response speed, high luminous efficiency, brightness, and viewing angle. OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL). When a driving voltage is applied to the anode and cathode electrodes, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, and as a result, the emitting layer (EML) Visible light is generated.

The organic light emitting display device includes a gate driver for driving the gate lines of the display panel. This gate driver is formed in the non-display area of the display panel through the GIP (Gate driver in panel) method TFT (Thin Film Transistor) process to reduce process steps and manufacturing costs. These panel-embedded gate drivers include multiple GIP elements connected to gate lines. Each GIP device consists of multiple TFTs and capacitors.

In FIG. 1, a pixel array for displaying an input image is formed in the active area AA of the display panel PNL. The pixel array includes a light emitting layer array that implements OLED, and a pixel TFT array for driving the OLED. The light emitting layer array formed only in the active area (AA) becomes the light emitting surface of the organic light emitting display device and overlaps the pixel TFT array in the active area (AA). The area where the GIP elements are formed in the display panel (PNL) becomes the non-emissive surface of the organic light emitting display device. Accordingly, the area where the panel-embedded gate driver is formed becomes the bezel area (BZ) of the organic light emitting display device.

The area where GIP elements are formed is a non-emission area and is a major factor in increasing the bezel size in display devices. Organic light emitting display devices include a larger number of pixel TFTs and gate lines than other display devices, so the gate drivers built into the panel are complex and their formation area is large.

As the resolution of the display panel increases, the problem of increased bezel size becomes more serious. Since the number of gate lines increases as the resolution of a display screen of a certain size increases, the number of GIP elements increases in a high-resolution display device. As the number of GIP elements increases, the area of the non-emission area in which they are formed inevitably increases, making it difficult to reduce the bezel in an organic light emitting display device.

The purpose of the present invention is to effectively reduce the bezel size in an organic light emitting display device having a gate driver built into the panel.

In order to achieve the above object, the organic light emitting display device of the present invention has a pixel array including an OLED (Organic Light Emitting Diode) for each pixel, and a panel-embedded gate driver that drives the pixel array. The pixel array includes 1 It includes a pixel TFT array in which a plurality of unit TFT (Thin Film Transistor) regions constituting a pixel are disposed, and a pixel light-emitting array in which a plurality of unit light-emitting regions constituting one pixel are disposed. The pixel TFT array is located in a first area (AA) of the display panel, the panel-embedded gate driver is located in a second area (GA) outside the first area of the display panel, and the pixel light emitting array is: It is located in the first area AA and also in a part of the second area GA.

The pixel light emitting array overlaps the pixel TFT array in the first area AA, and overlaps a portion of the panel built-in gate driver in the second area GA.

The unit light emission area is wider than the unit TFT area.

At some positions of the display panel, the unit light emitting area partially overlaps a plurality of unit TFT areas.

A plurality of unit TFT areas constituting the pixel TFT array are arranged at equal intervals.

A plurality of unit TFT areas constituting the pixel TFT array are arranged at differential intervals.

The gap between adjacent unit TFT areas is wider in the center portion than in the edge portion of the display panel, and the edge portion is closer to the second area GA than in the center portion.

The OLED includes a light-emitting element provided in the unit light-emitting area, a pixel electrode connecting the light-emitting element to a driving TFT provided in the unit TFT area, and the pixel electrode includes a main electrode directly connected to the driving TFT and , which is directly connected to the light emitting element and includes an auxiliary electrode that penetrates the insulating film and is always connected to the main electrode.

In the present invention, the pixel light emitting array is formed wider than the pixel TFT array to expand the pixel light emitting array to the area where the panel built-in gate driver is formed. Accordingly, the present invention can reduce the bezel area by the area where the pixel light emitting array is located among the areas where the panel-embedded gate driver is formed. The present invention can further increase the completeness of the product by effectively reducing the bezel size.

1 is a diagram showing a panel-embedded gate driver formed outside the active area of a display panel.
Figure 2 is a diagram showing the formation positions of the pixel array and the panel-embedded gate driver in the organic light emitting display device of the present invention.
3 is a diagram showing the pixel light emitting array overlapping with a portion of the pixel TFT array and the GIP TFT array.
FIG. 4 is a diagram showing a tendency for the spacing between unit TFT areas to become wider in the center portion of the display panel compared to the edge portion.
Figure 5 is a diagram showing the connection form of pixel electrodes when unit TFT areas are arranged at equal and differential intervals.
Figure 6 is a cross-sectional view of a display panel showing an example in which a portion of the pixel light-emitting array is expanded into the GIP area.
Figure 7 is a cross-sectional view of a display panel showing another example in which part of the pixel light-emitting array is expanded into the GIP area.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Additionally, the component names used in the following description were selected in consideration of ease of specification preparation, and may therefore differ from the component names of the actual product.

Figure 2 shows the formation positions of the pixel array and the panel-embedded gate driver in the organic light emitting display device of the present invention. Figure 3 shows the pixel light emitting array overlapping with a portion of the pixel TFT array and the GIP TFT array. Figure 4 shows a tendency for the spacing between unit TFT areas to become wider in the center portion of the display panel compared to the edge portion. And, Figure 5 shows the connection form of the pixel electrodes when the unit TFT areas are arranged at equal and differential intervals.

Referring to FIGS. 2 to 5 , an organic light emitting display device according to an embodiment of the present invention includes a display panel (PNL) and a built-in panel gate driver (GDV).

The display panel (PNL) is provided with a pixel array that displays an input image. In a pixel array, multiple data lines and multiple gate lines intersect, and pixels are arranged in a matrix form. Each pixel includes an OLED and at least one TFT. The pixel array may further include a power supply line that supplies a high-potential driving voltage to the pixels.

The pixel array consists of a pixel TFT array in which multiple unit TFT areas (T1 to Ti, i is a positive integer of 2 or more) constituting one pixel are arranged, and a plurality of unit emission areas (E1 to Ei) constituting one pixel are arranged. It includes a arranged pixel light emitting array.

Each unit TFT area (T1 to Ti) belonging to the pixel TFT array includes multiple gate lines, data lines, power supply lines, multiple pixel TFTs (including driving TFTs and switch TFTs), capacitors, etc. The pixel TFT array is located in the first area AA of the display panel PNL.

The panel embedded gate driver (GDV) includes multiple GIP elements connected to gate lines. Each GIP device includes multiple TFTs and capacitors to form a GIP TFT array. The GIP TFT array is located in the second area GA outside the first area AA in the display panel PNL.

The unit light-emitting areas (E1 to Ei) belonging to the pixel light-emitting array are divided by the light-emitting layer (EL, light-emitting element) of the OLED. OLED light-emitting devices are patterned on a pixel basis. OLED has a light emitting element, a pixel electrode (ANO), and a common electrode. The pixel electrode (ANO) connects the light emitting element to the driving TFT of the unit TFT area (T1 to Ti) and is patterned on a pixel basis. The common electrode is commonly connected to the light emitting elements of all pixels. The pixel electrode (ANO) may be an anode electrode and the common electrode may be a cathode electrode. Additionally, in contrast, the pixel electrode (ANO) may be a cathode electrode and the common electrode may be an anode electrode.

The pixel light emitting array is located in the first area AA and also in a part of the second area GA. As shown in FIG. 3 , the pixel light emitting array overlaps the pixel TFT array in the first area AA and overlaps a portion of the GIP TFT array in the second area GA. Since the pixel light emitting array is formed to extend to a portion of the second area GA, the bezel size is effectively reduced. In the prior art, the entire second area GA became the bezel area BZ, but in the present invention, the bezel area BZ is reduced by the area TD where the pixel light emitting array is located in the second area GA.

The area occupied by the pixel light-emitting array is larger than the area occupied by the pixel TFT array. For this purpose, the unit light emission area (E1 to Ei) is designed to be wider than the unit TFT area (T1 to Ti). As a result, as shown in FIG. 5 , at some positions of the display panel PNL, the unit emission areas E1 to Ei may partially overlap with the plurality of unit TFT areas T1 to Ti.

Under a structure in which the unit emission areas (E1 to Ei) are wider than the unit TFT areas (T1 to Ti), the multiple unit TFT areas (T1 to Ti) constituting the pixel TFT array are equally spaced as shown in (A) of FIG. 5. It can be placed as . However, in this case, since the connection form of the pixel electrode (ANO) becomes complicated, it may be disadvantageous in terms of process convenience for the pixel electrode (ANO). For high-resolution models, the process margin is limited, so it is important to minimize process complexity. Therefore, in this case, it is more desirable to arrange the plurality of unit TFT regions (T1 to Ti) constituting the pixel TFT array at differential intervals as shown in (B) of FIG. 5.

More specifically, in order to simplify the connection form of the pixel electrode (ANO), the spacing (D) between neighboring unit TFT areas is set at the center portion compared to the edge portion of the display panel (PNL), as shown in FIGS. 2 and 4. It is important to expand further. Here, the edge portion is closer to the second area GA than the center portion. That is, in the present invention, the closer to the edge of the display panel (PNL), the closer the spacing (D) between the unit TFT areas is designed. Conversely, the closer to the center of the display panel (PNL), the closer the spacing (D) between the unit TFT areas is designed. D) can be designed sparsely.

Figures 6 and 7 show examples where part of the pixel light emitting array is expanded into the GIP area.

6 and 7 show that a portion of the pixel light emitting array is expanded into the GIP area.

The pixel electrode (ANO) connecting the light emitting element (EL) to the driving TFT of the unit TFT area may be implemented with a one-layer structure as shown in FIG. 6 or a two-layer structure as shown in FIG. 7. In the one-layer structure, a single pixel electrode (ANO) is directly connected to the light emitting element (EL) and the driving TFT. On the other hand, in the two-layer structure, the pixel electrode (ANO) is directly connected to the main electrodes (ANO1, ANO2), which are directly connected to the driving TFT, and the light emitting element (EL), and also penetrates the insulating film (BA) to connect the main electrodes (ANO1, ANO2) to the driving TFT. It may include auxiliary electrodes (SNO1, SNO2) connected to ANO2). The two-layer structure of Figure 7 requires one more mask process, but has the advantage of effectively expanding the pixel light-emitting array when the resolution is high.

Referring to FIG. 6, the present invention has a GIP TFT array including a first TFT (T1), a pixel TFT array including a second TFT (T2), and a pixel light emitting array including an OLED.

The present invention includes a first TFT (T1) formed in the second area (GA) and a second TFT (T2) formed in the first area (AA). The present invention includes an OLED formed over a first area (AA) and a second area (GA).

A buffer layer (BUF) is laminated on the entire surface of the substrate (SUB). In some cases, the buffer layer (BUF) may be omitted and may have a structure in which a plurality of thin film layers are stacked.

A first semiconductor layer (A1) and a second semiconductor layer (A2) are disposed on the buffer layer (BUF).

The first semiconductor layer (A1) includes a channel region of the first TFT (T1). The channel area is defined as an area where the first gate electrode (G1) and the first semiconductor layer (A1) overlap. Since the first gate electrode G1 overlaps the center of the first TFT (T1), the center of the first TFT (T1) becomes a channel area. Both sides of the channel region are doped with impurities and are defined by a first source region SA1 and a first drain region DA1.

The second semiconductor layer (A2) includes a channel region of the second TFT (T2). The channel area is defined as an area where the second gate electrode (G2) and the second semiconductor layer (A2) overlap. Since the second gate electrode G2 overlaps the center of the second TFT (T2), the center of the second TFT (T2) becomes a channel region. Both sides of the channel region are doped with impurities and are defined by a second source region SA2 and a second drain region DA2.

When the first and second TFTs (T1, T2) are driving TFTs, they preferably have characteristics suitable for performing high-speed driving processing. For example, a P-MOS or N-MOS type thin film transistor can be used, or a C-MOS type thin film transistor containing both can be provided. P-MOS, N-MOS and/or C-MOS type thin film transistors preferably contain a polycrystalline semiconductor material such as poly-silicon. Additionally, it is desirable for the first and second TFTs (T1, T2) to have a top-gate structure.

A gate insulating film GI is stacked on the entire surface of the substrate SUB on which the first and second semiconductor layers A1 and A2 are disposed. The gate insulating film (GI) can be formed of silicon oxide (SiOx).

A first gate electrode (G1) and a second gate electrode (G2) are formed on the gate insulating film (GI). The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer A1. The second gate electrode G2 is disposed to overlap the central portion of the second semiconductor layer A2. An intermediate insulating film is stacked to cover the first and second gate electrodes G1 and G2. The intermediate insulating film is preferably formed of a nitride film (SIN) containing silicon nitride (SiNx). Alternatively, the intermediate insulating film preferably has a multi-layer structure in which a nitride film (SIN) containing silicon nitride (SiNx) and an oxide film (SIO) containing silicon oxide (SiOx) are alternately stacked. Here, for convenience, the minimal component is described as a double-layer structure in which an oxide film (SIO) is stacked on a nitride film (SIN).

On the intermediate insulating film, first source-drain electrodes (S1-D1) and second source-drain electrodes (S2-D2) are disposed. The first source electrode (S1) and the first drain electrode (D1) are arranged to face each other at a certain distance apart from the first gate electrode (G1). The first source electrode S1 is connected to the first source area SA1, which is one side of the first semiconductor layer A1 exposed through a first source contact hole (not shown). The first drain electrode D1 is connected to the first drain area DA1, which is the other side of the exposed first semiconductor layer A1, through a first drain contact hole (not shown). The second source electrode (S2) and the second drain electrode (D2) are arranged to face each other at a certain distance apart from the second gate electrode (G2). The second source electrode S2 is connected to the second source area SA2, which is one side of the second semiconductor layer A2 exposed through a second source contact hole (not shown). The second drain electrode D2 is connected to the second drain area DA2, which is the other side of the exposed second semiconductor layer A2, through a second drain contact hole (not shown).

A protective film (PAS) and a planarization film (OC) are sequentially deposited on the substrate (SUB) on which the first source-drain electrodes (S1-D1) and the second source-drain electrodes (S2-D2) are formed. A drain contact hole (PH) exposing the second drain electrode (D2) is formed in the protective film (PAS) and the planarization film (OC).

The pixel electrode (ANO) serves as the lower electrode of the OLED, is located on the planarization film (OC), and is connected to the drain electrode (D2) of the second TFT (T2) through the drain contact hole (PH). The pixel electrode (ANO) may include at least one transparent dielectric layer containing an oxide such as ITO or IZO, and a highly reflective and opaque metal layer such as Al, Ag, or AlNd.

The bank pattern BA is located on the substrate SUB on which the pixel electrode ANO is formed and defines a unit light emission area of the pixel. The light emitting layer (EL) is a light emitting element of OLED and is in contact with the pixel electrode (ANO) and is located across the first area (AA) and the second area (GA). The common electrode (CAT) serves as an upper electrode of the OLED and is located on the light emitting layer (EL), and may include dielectric layer(s) and one or two metal layers.

Compared to FIG. 6, FIG. 7 shows the remaining configuration except that the pixel electrode (ANO) is composed of a main electrode (ANO1) and an auxiliary electrode (SNO1) connected to each other through a bank film (insulating film, BA). It is substantially the same as described in.

As described above, in the present invention, the pixel light emitting array is formed wider than the pixel TFT array to extend the pixel light emitting array to the area where the panel built-in gate driver is formed. Accordingly, the present invention can reduce the bezel area by the area where the pixel light emitting array is located among the areas where the panel-embedded gate driver is formed. The present invention can further increase the completeness of the product by effectively reducing the bezel size.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

PNL: Display panel AA: First area
GA: Second area BZ: Bezel area
T1~T8: Unit TFT area E1~E8: Unit light emitting area

Claims (9)

An organic light emitting display device having a pixel array including an organic light emitting diode (OLED) for each pixel, and a panel-embedded gate driver that drives the pixel array,
The pixel array includes a pixel TFT array in which a plurality of unit TFT (Thin Film Transistor) regions constituting one pixel are disposed, and a pixel light emitting array in which a plurality of unit light emitting regions constituting the one pixel are disposed,
The pixel TFT array is located in the first area AA of the display panel,
The panel built-in gate driver is located in a second area (GA) outside the first area in the display panel,
The pixel light emitting array is located in the first area (AA) and a portion of the second area (GA),
The pixel light emitting array is,
Overlapping with the pixel TFT array in the first area (AA) and overlapping with a portion of the panel built-in gate driver in the second area (GA),
The gap between adjacent unit TFT areas is wider in the center portion than in the edge portion of the display panel,
The edge portion is closer to the second area GA than the center portion. delete According to claim 1,
An organic light emitting display device wherein the unit light emitting area is wider than the unit TFT area. According to claim 3,
An organic light emitting display device wherein the unit light emitting area partially overlaps a plurality of unit TFT areas at some positions of the display panel. delete delete delete According to claim 1,
The OLED includes a light-emitting element provided in the unit light-emitting area, and a pixel electrode connecting the light-emitting element to a driving TFT provided in the unit TFT area,
The pixel electrode includes a main electrode directly connected to the driving TFT, and an auxiliary electrode directly connected to the light emitting element and connected to the main electrode through an insulating film. According to claim 1,
The OLED includes a light-emitting element provided in the unit light-emitting area, and a pixel electrode connecting the light-emitting element to a driving TFT provided in the unit TFT area,
The organic light emitting display device wherein the pixel electrode overlaps both at least one area of the driving TFT and at least one area of the gate driver TFT included in the panel built-in gate driver.