KR102279315B1 - A PLL with an Unipolar Charge Pump and a Loop Filter consisting of Sample-Hold Capacitor and FVCO-sampled Feedforward Filter - Google Patents

Abstract

The present invention is a phase-locked loop having a unidirectional charge pump in which the resistance is removed from the secondary RC loop filter and a switch and a capacitor are added, the frequency divider 100 dividing and lowering the frequency of the output signal at a certain ratio; a phase frequency detector 200 connected to the divider 100; a voltage-controlled oscillator (300) connected to the divider (100) and generating an output oscillation frequency according to a change in an input control voltage; a loop filter 400 for removing high-frequency components; The signal of the phase frequency detector 200 is connected to the output of the switch 1a 500 and the phase frequency detector 200 connected to the loop filter 400 to open and close the circuit to transfer the charge by the UP / DN signal. and a charge pump 600 for flowing a current according to the , and the loop filter 400 is connected to the charge pump 600 through the switch 1a 500 to receive the output of the charge pump 600 as an input. a capacitor 2 (700) that receives and removes a high-frequency component, forms a node between the charge pump (600) and the switch 1a (500), and is connected to a ground terminal; an OR gate 800 connected to the phase frequency detector 200; a NOR gate 900 connected to the phase frequency detector 200; a switch 2 (1000) connected to the output of the NOR gate (900), operating on and off, and connected to the divider (100) in parallel with the voltage-controlled oscillator (300); a reset switch 1100 that is connected to the output of the OR gate 800 and operates on and off, forms a node between the charge pump 600 and the switch 1a (500) and is connected to a ground terminal; It is connected to the output of the OR gate 800 and the output terminal further includes an NMOS 1200 that forms a node with the switch 2 1000 and the loop filter 400 and controls the switch 1a (500) on and off. characterized in that

Description

{A PLL with an Unipolar Charge Pump and a Loop Filter consisting of Sample-Hold Capacitor and FVCO-sampled Feedforward Filter }

The present invention relates to a phase locked loop having a unidirectional charge pump having a sample-and-hold capacitor and a feedforward loop filter operating on a voltage controlled oscillator signal.

In the recently developed wireless communication field, the phase-locked loop is widely used as a frequency synthesizer. As the available frequency band of a communication system increases, a phase-locked loop having a fast phase lock time, low phase noise characteristics, and low reference spurs is required in a desired frequency band. And since the noise characteristics of the signal source directly affect the circuit performance, it is important to design a signal source with good noise characteristics.

As a solution to these characteristics, an adaptive structure is widely used. This structure improves the bandwidth problem by increasing the charge pump current ratio or reducing the time constant of the loop filter by using a wide band in the out-of-lock state and switching to a narrow band while the loop is fixed.

However, the loop bandwidth of the prior art is still limited by the reference frequency for stability. Also, a study to solve the current mismatch of the charge pump affecting the reference signal pseudo noise was published.

In the case of conventional research, a change in charge pump current according to the loop filter voltage and an increase in the number of MOSs may cause mismatch problems between devices due to a difference in channel length modulation constant.

In addition, a method of improving the phase noise characteristics by using a low-gain voltage-controlled oscillator and a dual-slope phase-locked loop is also being used.

However, since the dual slope phase locked loop uses two loops, the complexity of the circuit increases and the phase lock time becomes slow.

The circuits of the dual slope phase locked loop have disadvantages in that the circuit area and power consumption increase because one or two phase frequency detectors and a charge pump are additionally required.

KR 10-2011-0109394 A KR 10-1331794 B1 KR 10-0830898 B1

[1] S. Sidiropoulos, D. Liu, J. Kim, G. Wei and M. Horowitz, “Adaptive bandwidth DLLs and PLLsusing regulated supply CMOS buffers,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 124-127, 2000. [2] M.S. Hwang, J. Kim and D. K. Jeong, “Reduction of pump current mismatch in charge-pump PLL,” IEE Electronics Lett., vol. 45, no. 3, pp. 135-136, Jan. 2009. [3] Chun-Yi Kuo, Jung-Yu Chang and Shen-Iuan Liu, “A Spur-Reduction Technique for a 5-GHz Frequency Synthesizer,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 53, no. 3, 526-533, March. 2006. [4] Wu-Hsin Chen, Wing-Fai Loke, and ByunghooJung, “A 0.5-V, 440-μW Frequency Synthesizer for Implantable Medical Devices,” IEEE Journal of Solid-State Circuits, vol. 47, no. 8, pp 1896-1907, Aug. 2012. [5] Ching-Yuan Yang, Shen-Iuan Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1445-1452, Oct. 2000.

Accordingly, the present invention is to solve the above problems, and to provide a unidirectional charge pump phase locked loop having a sample-and-hold capacitor and a feed-forward loop filter controlled to an output signal of a voltage-controlled oscillator in order to reduce the reference signal pseudo-noise. .

In the present invention for achieving the above object, in a phase-locked loop having a unidirectional charge pump in which a resistor is removed from a secondary RC loop filter and a switch and a capacitor are added, a divider for dividing and lowering the frequency of an output signal at a certain ratio (100); a phase frequency detector 200 connected to the divider 100; a voltage-controlled oscillator (300) connected to the divider (100) and generating an output oscillation frequency according to a change in an input control voltage; a loop filter 400 for removing high-frequency components; The signal of the phase frequency detector 200 is connected to the output of the switch 1a 500 and the phase frequency detector 200 connected to the loop filter 400 to open and close the circuit to transfer the charge by the UP / DN signal. and a charge pump 600 for flowing a current according to the , and the loop filter 400 is connected to the charge pump 600 through the switch 1a 500 to receive the output of the charge pump 600 as an input. a capacitor 2 (700) that receives and removes a high-frequency component, forms a node between the charge pump (600) and the switch 1a (500), and is connected to a ground terminal; an OR gate 800 connected to the phase frequency detector 200; a NOR gate 900 connected to the phase frequency detector 200; a switch 2 (1000) connected to the output of the NOR gate (900), operating on and off, and connected to the divider (100) in parallel with the voltage-controlled oscillator (300); a reset switch 1100 that is connected to the output of the OR gate 800 and operates on and off, forms a node between the charge pump 600 and the switch 1a (500), is connected and has an end grounded; The input terminal is connected to the output of the OR gate 800, and the output terminal forms a node with the switch 2 (1000) and the loop filter 400, and further includes an NMOS (1200) that turns on and off the switch 1a (500). characterized by including.

The structure of the phase-locked loop proposed in the present invention can reduce the chip area compared to the conventional RC secondary loop filter structure, as well as the amount of change in ΔVLPF that affects the phase noise of the voltage-controlled oscillator, and the reference signal pseudo-noise. It has the effect of improving the phase noise characteristic and the reference signal pseudo-noise characteristic by reducing the amount of change of ΔΔ VLPF that affects .

1 is a diagram for explaining a phase lock circuit.
2 is a circuit diagram of a phase locked loop according to the present invention.
3 is a block diagram of a phase locked loop according to the present invention.
4 is a circuit diagram of a conventional loop filter and an output waveform thereof.
5 is a circuit diagram of a conventional half-duty sampled feedforward loop filter and an output waveform thereof.
6 is a circuit diagram of a loop filter including a capacitor and a switch proposed in the present invention and an output waveform thereof.
7 is an output waveform showing the timing of a signal for controlling switches by the UP/DN signal of the PFD of the phase locked loop according to the present invention.
8 is a voltage change output waveform according to the switch operation of the phase locked loop according to the present invention.
9 is a circuit diagram showing the structure of the charge pump according to the present invention.
10 is a simulation result of a phase locked loop having a conventional secondary loop filter.
11 is an output waveform when the value of Icp/Ireset is 5 as an embodiment of the phase locked loop according to the present invention.
12 is an output waveform when the value of Icp/Ireset is 50 as an embodiment of the phase locked loop according to the present invention.

Hereinafter, although described with reference to the drawings according to an embodiment of the present invention, this is for easier understanding of the present invention, and the scope of the present invention is not limited thereto.

When a part "includes" a certain element throughout the specification, this means that other elements may be further included, rather than excluding other elements, unless otherwise stated. In addition, terms such as "... unit" and "module" described in the specification mean a unit that processes at least one function or operation, which may be implemented as hardware or software, or a combination of hardware and software. .

Throughout the specification, when a part is "connected" with another part, this includes not only the case of being "directly connected" but also the case of being "electrically connected" with another element interposed therebetween. .

In the present specification, when one component 'transmits' data or signal to another component, the component may directly transmit the data or signal to another component, and through at least one other component This means that data or signals can be transmitted to other components.

And, in this specification, a module may mean a functional and structural combination of hardware for carrying out the technical idea of the present invention and software for driving the hardware. For example, the module may mean a logical unit of a predetermined code and a hardware resource for executing the predetermined code, and does not necessarily mean physically connected code or a single type of hardware. It can be easily inferred to an average expert in the technical field of

Prior to the description, a number of aspects and embodiments are described herein, which are merely illustrative and not limiting.

After reading this specification, those skilled in the art will understand that other aspects and embodiments are possible without departing from the scope of the invention.

Before proceeding with the details of the embodiments described below, some terms are defined or clarified.

PLL is an abbreviation of Phase Locked Loop and means a phase locked circuit. It is a circuit that synchronizes to the input frequency and phase while reducing phase fluctuations rather than amplitude. It has the same configuration as FIG. 1, and consists of a phase comparator (PD), a loop filter (LF), a voltage controlled oscillator (VCO), and a divider.

DIV is an abbreviation of divider and refers to a divider, that is, a dividing device that lowers the frequency at a user's arbitrary ratio.

TCXO is an abbreviation of Temperature Compensated X-tal Oscillator. It means a crystal oscillator that can extract a very stable frequency without fluctuations in response to temperature changes. Using this unchanging frequency as a reference frequency, compare whether the output frequency is correct or not.

PFD is an abbreviation of Phase Frequency Detector and means a phase frequency detector. It compares the reference frequency of TCXO with the output frequency divided through the divider and sends out the pulse train corresponding to the difference.

VCO is an abbreviation of Voltage Controlled Oscillator and means a voltage controlled oscillator. It is a circuit that generates a sine wave or square wave signal of a frequency that varies according to the frequency control input voltage, and is one of the core blocks of a phase locked loop (PLL) that is generally used for frequency synthesis or clock restoration.

A charge pump (CP) is a device that supplies a current according to the output of a phase frequency detector. A bidirectional charge pump outputs a positive current pulse and a negative current pulse, and a unidirectional charge pump outputs a unidirectional current pulse. circuit,

To explain the operation principle of the PLL in detail, the phase difference detected by the phase comparator is converted into a low-frequency control voltage through a low-pass filter (LPF) and input to the VCO. At this time, the high frequency component of the input jitter (phase shake) is suppressed and low Only the frequency component is passed through. The control voltage is changed in a direction to reduce the phase difference between the input and the VCO at the VCO frequency. In the VCO, there is an oscillation circuit including a varator, and as a low-frequency control voltage to reduce the phase difference is input, the capacitor capacitance of the varactor changes, causing a change in the oscillation frequency by the LC resonance circuit. In other words, phase locked means that the control voltage locks the VCO average frequency to exactly match the input average frequency.

Next, a phase locked loop having a sample-and-hold capacitor and a unidirectional charge pump having a feedforward loop filter operating on a voltage controlled oscillator signal according to the present invention will be described in detail with reference to FIGS. 2 to 12 .

The present invention is a phase-locked loop having a unidirectional charge pump in which the resistance is removed from the secondary RC loop filter and a switch and a capacitor are added, the frequency divider 100 dividing and lowering the frequency of the output signal at a certain ratio; a phase frequency detector 200 connected to the divider 100; a voltage-controlled oscillator (300) connected to the divider (100) and generating an output oscillation frequency according to a change in an input control voltage; a loop filter 400 for removing high-frequency components; The signal of the phase frequency detector 200 is connected to the output of the switch 1a 500 and the phase frequency detector 200 connected to the loop filter 400 to open and close the circuit to transfer the charge by the UP / DN signal. and a charge pump 600 for flowing a current according to the , and the loop filter 400 is connected to the charge pump 600 through the switch 1a 500 to receive the output of the charge pump 600 as an input. a capacitor 2 (700) that receives and removes a high-frequency component, forms a node between the charge pump (600) and the switch 1a (500), and is connected to a ground terminal; an OR gate 800 connected to the phase frequency detector 200; a NOR gate 900 connected to the phase frequency detector 200; a switch 2 (1000) connected to the output of the NOR gate (900), operating on and off, and connected to the divider (100) in parallel with the voltage-controlled oscillator (300); a reset switch 1100 that is connected to the output of the OR gate 800 and operates on and off, forms a node between the charge pump 600 and the switch 1a (500), is connected and has an end grounded; The input terminal is connected to the output of the OR gate 800, and the output terminal forms a node with the switch 2 (1000) and the loop filter 400, and further includes an NMOS (1200) that turns on and off the switch 1a (500). characterized by including.

In this case, in "the frequency divider 100 for dividing and lowering the frequency of the output signal at a predetermined ratio," the predetermined ratio may be an arbitrary ratio previously designated by the user according to the purpose of the user.

And "the input terminal is connected to the output of the OR gate 800, and the output terminal forms a node with the switch 2 1000 and the loop filter 400, and the NMOS 1200 controls the switch 1a 500 on and off. In the NMOS of ", the output stage means Drain among Source, Gate, and Drain in a general N-type MOSFET, and the input stage, which is the part connected to the output, will be the Gate.

In addition, the loop filter 400, the capacitor 1 (410); capacitor z (420); When the switch 1a (400) is opened and closed, it is characterized in that it includes a switch 1b (430) that performs the reverse operation of closing and opening, and serves as a resistance.

In addition, the charge pump 600 is characterized in that it is a unidirectional charge pump.

Next, with reference to FIGS. 4 to 6 , a phase locked loop according to the present invention will be described in detail by comparing it with a conventional loop filter and by way of an embodiment.

In the phase-locked loop, the loop filter voltage controls the output frequency of the voltage-controlled oscillator according to the current phase/frequency error. Therefore, it is possible to know the characteristics of the phase-locked loop by observing the change in the loop filter voltage. The change in the loop filter voltage showing the characteristics of the phase-locked loop can be divided into three types: ΔVLPF, ΔΔVLPF, and ΔΔΔVLPF. ΔVLPF is the amount of change in the loop filter voltage that occurs after the phase of the phase-locked loop is fixed, and the magnitude of ΔVLPF is directly related to the stability of the phase-locked loop and the characteristics of phase noise. ΔΔVLPF is the amount of change in the loop filter voltage that occurs during one period of the reference signal by the UP or DN (DOWN) signal corresponding to the phase difference between the reference signal and the output of the voltage control oscillator, and represents the magnitude of the phase error currently occurring. ΔΔVLPF occurs every reference signal period, and as a result, determines the magnitude of the reference signal pseudo-noise. ΔΔΔVLPF means the final voltage of the loop filter capacitor due to the current flowing into the loop filter by the UP or DN signal.

The following equations show ΔVLPF and ΔΔVLPF, phase noise characteristics, and reference signal pseudo-noise characteristics.

<Equation 1. Equation for pseudo-noise>

<Equation 2. Expression for output frequency of VCO>

As shown in Equation (1) for the pseudo noise (P _spur ), the magnitude of the pseudo noise is proportional to the magnitude of ΔΔVLPF. Therefore, in order to reduce the size of the reference signal pseudo-noise, the size of ΔΔVLPF should be reduced. Also, as shown in Equation (2), if the amount of change (ΔVLPF) of the loop filter voltage (VLPF) included in the integrand is small, the amount of change of the VCO output frequency FVCO becomes smaller. Since the phase noise is reduced when the amount of change of the VCO output frequency FVCO is small, the size of ΔVLPF must also be reduced to obtain good phase noise characteristics.

where A is amplitude, ω is angular frequency [rad/s] ω=2πf, f is frequency [Hz] = [1/s], ωFR is output angular frequency of VCO when input voltage is 0 (zero), KVCO is It is the gain of the VCO and means the ratio of the output frequency of the VCO according to the change of the input voltage.

The voltage change occurring in each period of the reference signal is caused by mismatch of the current of the charge pump and timing errors of the UP and DN signals, even after the loop is fixed. In the related art, various loop filter structures have been studied for suppressing unnecessary frequency components of the output of the voltage controlled oscillator by reducing the voltage change of the loop filter as much as possible.

In general, in the secondary RC loop filter of FIG. 4 used in a phase-locked loop, when an UP/DN signal is generated from the phase frequency detector (PFD), a current flows from the charge pump (CP) to the loop filter. This current charges Cp first and raises (falls) the loop filter voltage VLPF. When the UP/DN signal is terminated, the charge in Cp flows to Rz and Cz, and the VLPF falls (rising) again. The operation of the secondary RC loop filter is repeated according to the phase-locked loop reference signal period, so that the reference signal pseudo noise is generated.

Another type of loop filter structure is shown in FIG. 5 . Although the area of the chip was reduced by replacing the resistance of the secondary RC loop filter with a switch, it was not possible to reduce the magnitude of the pseudo noise by causing a large phase change as the loop filter voltage was maintained for half a cycle. Therefore, performance improvement of the phase-locked loop cannot be expected.

In the present invention, in order to reduce ΔVLPF and ΔΔVLPF affecting the reference signal pseudo-noise, the loop filter voltage VLPF is maintained only during the half cycle of the VCO output signal, which is much shorter than the half cycle of the reference signal, so that it is maintained only for a much shorter time. was proposed as shown in FIG. 6 .

To explain the nonlinearity of the conventional phase detector-charge pump in more detail, the phase-locked loop using the conventional PFD and the secondary RC loop has the non-ideal characteristics of the PFD-CP (dead zone, slope mismatch) when it is in a steady state after phase locking. ), so it operates in the non-linear zero-crossing region. In addition, the problem of amplification value mismatch requires various correction techniques even when using the PFD that has solved the dead zone and the improved divider. In addition, the limited and non-uniform output impedance of the charge pump current source and the intrinsic asymmetry of the charge transfer versus phase error characteristics of the PFD-CP based on the second-order phase-locked loop create non-linearities. Nonlinearity increases the magnitude of in-band noise, causing intermodulation and aliasing of high-frequency noise. The nonlinearity of the existing PFD-CP can be improved by allowing only the UP(DN) path of the charge pump to operate alone and fixing the loop at the corrected phase offset away from the nonlinear region.

In the phase-locked loop, the loop filter voltage controls the output frequency of the voltage-controlled oscillator according to the current phase/frequency error. Therefore, it is possible to know the characteristics of the phase-locked loop by observing the change in the loop filter voltage.

The proposed PLL circuit proposed in the present invention removes the resistance to the existing secondary RC loop filter as shown in FIG. 2, adds a switch and a capacitor, and places a switch SW1a between the loop filter and the capacitor to transfer the charge by the UP/DN signal. It has a structure in which the lower end of the charge pump (CP) is used as a switch. Switch SW1b operates in the opposite way to switch SW1a and acts as a resistor.

7 shows the timing of a signal controlling the switches by the UP/DN signal of the PFD. When the UP/DN signal is generated, the output of the OR gate 800 becomes “High” and the NMOS becomes “On”, so “Node A” is grounded, the switch SW1a is “Off,” and the NOR gate 900 becomes “Low”. ” and the switch SW2 (1000) is “Off”. That is, when the UP/DN signal is generated, the switch SW1a (500) and the switch SW2 (1000) are “Off” and the current from the charge pump charges Cp2 (700). After the UP/DN signal is turned off, the switch SW2 (1000) is “On”, and the switch SW1a (500) and the switch SWb (430) repeat “On” and “Off” according to the signal of the voltage-controlled oscillator 300 . .

8 shows the timing of the signals controlling the switches by the UP/DN signal and the loop filter voltage VLPF in consideration of the switch operation by the voltage controlled oscillator 300 signal. The SWreset signal is “On” only for a very short time after the UP signal is generated, and Cp2 (700) is initialized. When the UP/DN signal is generated, the switches SW1a (500) and SW2 (1000) are “Off” so that the VCO output cannot be applied to the loop filter 400 when the UP/DN signal is generated, and the loop filter from the charge pump Since no charge is supplied to 400, the loop filter voltage VLPF remains constant. After the UP/DN signal is turned off, switch SW2 is turned “On” and the switch SW1a (500) and switch SW1b (430) repeat “On” and “Off” according to the signal of the voltage control oscillator, and the voltage of the loop filter slowly decreases. change

Next, the charge pump 600 of the phase locked loop according to the present invention will be described in detail.

The unidirectional charge pump of FIG. 9 serves to control the flow of current according to the UP/DN signal from the frequency detector.

As shown in FIG. 9, the charge pump used in the present invention recommends using a cascode structure. By controlling the MN2 transistor of the charge pump to operate with the SWreset (1100) signal, the charge/discharge current ratio of the unidirectional charge pump is controlled according to the size of MP2 and MN2. This structure controls the generation time of the UP signal.

Next, the effect of a phase locked loop having a sample-and-hold capacitor and a unidirectional charge pump having a feedforward loop filter operating on a voltage-controlled oscillator signal according to the present invention will be described in detail by way of example compared to the prior art. .

For comparison with the proposed structure, a phase-locked loop of the existing structure with a bidirectional charge pump and a secondary loop filter was simulated. It has a reference frequency of 15.625 MHz, an output frequency of 1 GHz, and a division ratio of 64. The variable values of this circuit are Icp=200μA, Cp=100pF, Rz=1.5KΩ, Cz=1nF, KVCO=330MHz/V, and it was simulated by HSPICE with 0.18μm CMOS process. 10 shows a simulation result of a phase-locked loop having a conventional secondary loop filter. Fig. 10 (a) shows that the phase is fixed at 18 μs, Fig. 10 (b) shows that the amount of change in the loop filter voltage ΔVLPF that occurs after the phase is fixed has a value of 1.2 mV, and Fig. 10 (c) shows It shows that the magnitude of ΔΔVLPF that occurs every reference signal period is 190 μV.

The proposed phase-locked loop also has the same reference frequency of 15.625 MHz, output frequency of 1 GHz, KVCO of 330 MHz/V, and division ratio of 64 as in the existing structure. The proposed structure has a different charge pump and loop filter structure, so the charge pump current values are Icp=200μA, Ireset=1mA, and the loop filter has Cp1=400pF, Cp2=50pF, Cz=50pF, values.

The proposed structure with almost similar values was simulated with HSPICE in 0.18 μm CMOS process as in the previous case.

11 and 12 are simulation results of the proposed phase locked loop when the values of Icp/Ireset are 5 and 50. (a), (b), and (c) are respectively (a) VLPF waveform after phase lock (b) Expanded loop filter voltage change after phase lock (ΔVLPF) (c) Expanded loop filter voltage change after phase lock ( ΔΔVLPF).

11 (c) and 12 (c), during the period in which the UP signal is generated, no charge is supplied from the charge pump 600 to the loop filter 400, and through the switch SW1b (430) in Cp1 (410). Current flows to Cz (420) and the loop output voltage decreases. It can be seen that the switch SW1b 430 used for the loop filter operates according to the output signal of the voltage controlled oscillator 300 .

11 is a simulation result when the value of Icp/Ireset is 5; As shown in Fig. 11(a), the phase is fixed at 27 μs, similar to the existing phase-locked loop. 11(b) and (c) show that ΔVLPF and ΔΔVLPF are 223 μV and 29 μV, respectively, which are significantly reduced in size compared to the existing structure.

12 is a simulation result when the value of Icp/Ireset is 50; As Fig. 12(a) shows, the phase is fixed at 25 μs. As shown in FIGS. 12(b) and 12(c), ΔVLPF and ΔΔVLPF are 402 μV and 55.3 μV, respectively.

When the value of Icp/Ireset is 5, the simulation results show that the ΔΔVLPF and ΔVLPF sizes of the structure proposed in the present invention were reduced to 1/5 and 1/6, respectively, compared to the existing structure, and the values of Icp/Ireset At 50, both the VLPF and ΔVLPF sizes were reduced to 1/3 of the size of the conventional structure.

When the values of Icp/Ireset are 5 and 50, it can be seen that the characteristics of the reference signal pseudo noise and phase noise are greatly improved, and the phase fixing time is increased by about 50%.

A unidirectional charge pump phase-locked loop with a sample-and-hold capacitor and a feed-forward loop filter that operates on VCO signals can significantly improve noise characteristics compared to conventional structures when Icp/Ireset is small. And since a simple switch control circuit is added to the existing structure, the chip size and power consumption hardly increase. By switching controlled by the voltage-controlled oscillator output signal, pseudo noise is generated at a frequency that is as far away from the carrier frequency as the voltage-controlled oscillator output signal frequency.

Because this pseudo noise is far from the carrier used by the system, it is easily removed by the filter, so it does not affect other channel signals within the bandwidth desired by the user.

In the present invention, a phase-locked loop having a unidirectional charge pump with a sample-and-hold capacitor and a feed-forward loop filter operating on a voltage controlled oscillator signal is proposed. Compared to the conventional RC secondary loop filter structure, the proposed structure can reduce the chip area, as well as the amount of change in ΔVLPF that affects the phase noise of the voltage-controlled oscillator, and the ΔΔVLPF that affects the pseudo-noise of the reference signal. It is possible to improve the phase noise characteristic and the reference signal pseudo-noise characteristic by reducing the amount of change of , to 1/5 and 1/6, respectively.

The predetermined numerical values described above are described to help the understanding of the present invention, which may vary according to an operator's setting, and it is natural that the above-described numerical values are not limited to the present invention.

As described above with reference to the drawings according to the embodiment of the present invention, those of ordinary skill in the art to which the present invention pertains will be able to make various applications and modifications within the scope of the present invention based on the above content.

100: divider (DIV)
200: phase frequency detector (PFD)
300: voltage controlled oscillator (VCO)
400: loop filter
410: capacitor 1
420: capacitor z
430: switch 1b
500: switch 1a
600: charge pump
700: capacitor 2
800: OR gate
900: NOR gate
1000: switch 2
1100: reset switch
1200: NMOS

Claims (3)

In a phase locked loop having a unidirectional charge pump in which a resistor is removed from the secondary RC loop filter and a switch and a capacitor are added,
a divider 100 for dividing and lowering the frequency of the output signal by a predetermined ratio;
a phase frequency detector 200 connected to the divider 100;
a voltage-controlled oscillator (300) connected to the divider (100) and generating an output oscillation frequency according to a change in an input control voltage;
a loop filter 400 for removing high-frequency components;
A switch 1a (500) connected to the loop filter 400 to open and close the circuit to transfer the charge by the UP/DN signal, and
and a charge pump 600 connected to the output of the phase frequency detector 200 and flowing a current according to the signal of the phase frequency detector 200,
The loop filter 400 is connected to the charge pump 600 through the switch 1a 500 and receives the output of the charge pump 600 as an input to remove high-frequency components,
a capacitor 2 (700) which forms a node between the charge pump (600) and the switch 1a (500) and is connected to a ground terminal;
an OR gate 800 connected to the phase frequency detector 200;
a NOR gate 900 connected to the phase frequency detector 200;
a switch 2 (1000) connected to the output of the NOR gate (900) to operate on-off, and connected to the divider (100) in parallel with the voltage-controlled oscillator (300);
a reset switch 1100 that is connected to the output of the OR gate 800 and operates on and off, forms a node between the charge pump 600 and the switch 1a (500) and is connected to a ground terminal;
The NMOS (1200) transistor is controlled by the output of the OR gate (800), and the switch 1a (500) and the switch 1b (430) in the loop filter 400 are turned on/off.
The method according to claim 1,
The loop filter 400,
capacitor 1 (410);
capacitor z (420);
and a switch 1b (430) configured to act as a resistor by performing the reverse operation of closing and opening when the switch 1a (500) is opened and closed.

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