KR101892076B1 - Integrated circuit with different voltage domain circuits - Google Patents

Abstract

The present invention is directed to an integrated circuit including circuits driven into different voltage domains. The integrated circuit includes a first circuit region driven by a first power supply voltage and a second circuit region driven by a second power supply voltage higher than the first power supply voltage. In the second circuit region, the interface circuit interfaced with the first circuit region and receiving at least one signal from the first circuit region is powered by a second power supply voltage level in response to an output signal of the second circuit region, And level-shifts at least one signal to a second power supply voltage level. The first power supply voltage corresponds to the first voltage domain and the second power supply voltage corresponds to the second voltage domain.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to integrated circuits with different voltage domains,

The present invention relates to integrated circuits, and more particularly to integrated circuits including circuits driven with different voltage domains.

The power consumption in the integrated circuit is related to the power supply voltage applied to the integrated circuit. The power consumed in the integrated circuit depends on the magnitude of the supply voltage relative to the ground voltage. Generally, power consumption can be reduced by lowering the power supply voltage level. However, there is a limit to reducing the power supply voltage level. For example, with respect to the robustness of a memory device such as an SRAM included in an integrated circuit, if the power supply voltage is reduced below a certain voltage level, the performance of the memory device's reading and / or writing operations may be degraded. Therefore, even if the power supply voltage level of the integrated circuit is set to be lower than the operation voltage level of the memory device in order to reduce power consumption, an integrated circuit capable of ensuring the performance of the memory device is needed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an integrated circuit including circuits driven with different voltage domains.

An integrated circuit according to an aspect of the present invention includes a first circuit region driven by a first power supply voltage and a second circuit region driven by a second power supply voltage different from the first power supply voltage and receiving at least one signal received from the first circuit region And a second circuit area including an interface circuit. The interface circuit is powered to the second power supply voltage level in response to an output signal of the second circuit region and generates an output signal of a second circuit region level shifted to a second power supply voltage level.

An interface circuit connected between the first and second voltage domains according to another aspect of the present invention includes a first power supply voltage and a second power supply voltage that are connected to a second power supply voltage different from the first power supply voltage, A second PMOS transistor connected between the first transistor and the first node and controlled by an input signal of a first power supply voltage level, a third PMOS transistor connected to the second power supply voltage and controlled by a clock signal, A first and a second NMOS transistor serially connected between a first node and a ground voltage and controlled by an input signal and a clock signal, respectively, and a second NMOS transistor connected to the first node and outputting an output signal according to a signal of the first node Inverter. The first power supply voltage corresponds to the first voltage domain and the second power supply voltage corresponds to the second voltage domain.

An integrated circuit according to another aspect of the present invention includes at least one logic circuit driven by a first power supply voltage and one or more circuits driven by a second power supply voltage different from the first power supply voltage and interfaced with a logic circuit And at least one memory circuit. Each of the one or more circuits is powered to a second power supply voltage level in response to its output signal and level shifts at least one signal of a first power supply voltage level received at the logic circuit to a second power supply voltage level .

A method according to another aspect of the present invention includes the steps of driving a first circuit region with a first power supply voltage, driving a second circuit region with a second power supply voltage different from the first power supply voltage, Generating at least one signal having one power supply voltage level and shifting at least one signal to a second power supply voltage level in response to at least one signal in a second circuit region and generating an output signal, . The second circuit region is powered by a second power supply voltage level in response to the output signal.

According to the above-described integrated circuit of the present invention, the interface circuit of the second circuit region, which is interfaced with the first circuit region, is supplied with power by the output signal of the second circuit region. The second circuit region level-shifts the signal of the first power supply voltage level outputted from the first circuit region to the second power supply voltage level. As the first power supply voltage of the first circuit region sufficiently lowers the level of the first power supply voltage by the interface circuit, the power consumption of the integrated circuit can be reduced.

1 is a block diagram illustrating an integrated circuit in accordance with various embodiments of the present invention.
2 is a diagram illustrating the interface of logic circuits and memory circuits in accordance with various embodiments of the present invention.
3 is a diagram illustrating a clock signal generation circuit according to various embodiments of the present invention.
Figure 4 is a circuit diagram illustrating the interface circuit of Figure 2 in accordance with various embodiments of the present invention.
5 is a diagram illustrating a memory circuit included in an integrated circuit according to various embodiments of the present invention.
Figure 6 is a diagram illustrating the third interface circuit of Figure 5 in accordance with various embodiments of the present invention.
Figure 7 is a flow chart illustrating the method of operation of Figure 5 in accordance with various embodiments of the present invention.
8 is a diagram illustrating a first example of a system including an interface circuit according to various embodiments of the present invention.
9 is a diagram illustrating a second example of a system including an interface circuit according to various embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

As the number of transistors in an integrated circuit increases and the operating frequency of the integrated circuit increases, the amount of power consumed by the integrated circuit is increasing. If power consumption is not managed, it may be too costly to meet the thermal requirements of the integrated circuit, or the integrated circuit may not be realized. The thermal requirement of an integrated circuit is to provide components that allow the integrated circuit in operation to cool properly to keep the integrated circuit within thermal limits. In addition, in applications such as battery power devices, power management of integrated circuits is also an important factor in providing adequate battery life.

The power consumption of the integrated circuit is related to the supply voltage supplied to the integrated circuit. The power consumed in the integrated circuit depends on the magnitude of the supply voltage relative to the ground voltage. Generally, power consumption can be reduced by lowering the power supply voltage level.

1 is a block diagram illustrating an integrated circuit in accordance with various embodiments of the present invention.

Referring to FIG. 1, an integrated circuit 10 includes a plurality of logic circuits 12 and a plurality of memory circuits 14. The logic circuits 12 are connected to the memory circuits 14. The logic circuits 12 are included in a first circuit region 11 driven by a first power supply voltage VDDL and the memory circuits 14 are driven by a second power supply voltage VDDS, Area 13 as shown in FIG. The first power supply voltage VDDL and the second power supply voltage VDDS may be provided outside the integrated circuit 10. In addition, the first power supply voltage VDDL and the second power supply voltage VDDS may be provided in the voltage generating unit in the integrated circuit 10. [ The second power supply voltage VDDS may be set higher than the first power supply voltage VDDL. The integrated circuit 10 may consist of logic circuits 12 and memory circuits 14 integrated on one semiconductor substrate.

The logic circuits 12 may represent the logic states of binary 1 and binary 0 with the first power supply voltage VDDL and the ground voltage VSS, respectively. The logic circuits 12 can be evaluated as a logic signal that transitions from the first power supply voltage VDDL to the ground voltage VSS during operation or from the ground voltage VSS to the first power supply voltage VDDL completely evaluate). The power consumption of the logic circuits 12 depends on the relative voltage magnitude of the first voltage VDDL relative to the ground voltage VSS. The power consumption of the logic circuits 12 can be lowered by lowering the first power supply voltage VDDL. The first power supply voltage VDDL can be lowered to a voltage level at which the operation of the logic circuits 12 can be properly performed.

The logic circuits 12 may perform operations according to the purpose for which the integrated circuit 10 is designed. Logic circuits 12 may generate and store various data values during operation in memory circuits 14. In addition, the logic circuits 12 may read various data values from the memory circuits 14. Memory circuits 14 may include memory used, for example, as caches, registers, and the like. The memory circuits 14 may be implemented as a read / write type of memory.

Logic circuits 12 may generate various control signals CTL to access memory circuits 14. The control signals CTL may include an address signal indicating a memory location to be accessed in the memory circuits 14, a read enable signal for instructing a read operation, and a write enable signal for instructing a write operation. In a read operation, the memory circuits 14 output data to the logic circuits 12. In a write operation, logic circuits 12 provide data for storage to memory circuits 14. The control signals CTL provided in the logic circuits 12 are signals operating with the first power supply voltage VDDL and the ground voltage VSS.

2 is a diagram illustrating the interface of logic circuits and memory circuits in accordance with various embodiments of the present invention.

2, the logic circuit 12a may be one of the logic circuits 12 of FIG. The memory circuit 14a may be one of the memory circuits 14 of Fig. The logic circuit 12a is described as a domain driven with the first power supply voltage VDDL and the memory circuit 14a can be described as a domain driven with the second power supply voltage VDDS. That is, the logic circuit 12a and the memory circuit 14a are circuits driven with different voltage domains.

The logic circuit 12a may include a plurality of inverters 21, 22, The first to third inverters 21, 22 and 23 are supplied with the first power supply voltage VDDL. The first inverter 21 receives the input signal IN and outputs the output signal OUT1 in response to the first clock signals CLK and CLKB. For example, the first inverter 21 is a clocked inverter that inverts the input signal IN in response to the falling edge of the first clock signal CLK. The second and third inverters 22 and 23 are cross-connected to each other to constitute the latch 24. The output of the first inverter 21 is connected to the latch 24.

The latch 24 inverts and latches the output signal OUT1 of the received first inverter 21 to output the first control signal CTL1. The second inverter 22 receives and inverts the output signal OUT1 of the first inverter 21 to output the first control signal CTL1. The third inverter 23 receives the first control signal CTL1 in response to the first clock signals CLK and CLKB and the output of the third inverter 23 to the input of the second inverter 22 do. For example, the third inverter 23 is a clocked tri-state inverter that inverts the first control signal CTL1 in response to the logic high level of the first clock signal CLK.

In the logic circuit 12a, the input signal IN, the first clock signals CLK and CLKB, the output signal OUT1 and the first control signal CTL1 operate between the first power supply voltage VDDL and the ground voltage . The logic circuit 12a generates a first control signal CTL1 having the same logic level as the input signal IN. The control signal CTL1 may be one of the control signals CTL of FIG.

The memory circuit 14a is connected to the logic circuit 12a via the interface circuit 25. [ The interface circuit 25 may include a clocked gate 26 and a fourth inverter 27. And the second power supply voltage VDDS is supplied to the clocked gate 26 and the fourth inverter 27. [ The clocked gate 26 may be composed of a NAND gate receiving the control signals CTL1 and CTL2 and the second clock signal CLKP. According to various embodiments, the clocked gate 26 may be implemented with a different logic gate instead of a NAND gate.

The first control signal CTL1 is provided from the logic circuit 12a. Similarly, a second control signal CTL2 may also be provided from the logic circuit 12a. The first and second control signals CTL1 and CTL2 are signals operating at the first power supply voltage VDDL and the ground voltage VSS level.

The second clock signal CLKP may be a signal provided in the second power supply voltage VDDS domain. The second clock signal CLKP is a signal that operates at the second power supply voltage VDDS and the ground voltage VSS level. The clocked gate 26 receives the control signals CTL1 and CTL2 and the second clock signal CLKP and outputs the second output signal OUT2. The second output signal OUT2 is provided to the fourth inverter 27 and the fourth inverter 27 outputs the third output signal OUT3.

3 is a diagram illustrating a clock signal generation circuit according to various embodiments of the present invention.

Referring to FIG. 3, the clock signal generating circuit 15 may receive the external clock signal CLK_EXT to generate the first clock signals CLK and CLKB and the second clock signal CLKP. The clock signal generating circuit 15 includes a clock receiving unit 16 for receiving the external clock signal CLK_EXT and first and second inverters 17 and 18 connected in series to the output of the clock receiving unit 16 can do.

The clock receiving unit 16 is driven by the second power supply voltage VDDS and can receive the external clock signal CLK_EXT and generate the second clock signal CLKP of the second power supply voltage VDDS level. The clock receiving unit 16 may include a clock generating unit of a differential cross-coupled latch type. The clock generator 16 may function as a level shifter and a buffer function. The external clock signal CLK_EXT may have a first power supply voltage VDDL or a second power supply voltage VDDS level. The second internal clock signal CLKP is input to the first inverter 17 and the first inverter 17 can generate the inverted first clock signal CLKB. The inverted first clock signal CLKB is input to the second inverter 18 and the second inverter 18 can generate the first clock signal CLK. The first and second inverters 17 and 18 are driven to the first power supply voltage VDDL so that the first clock signals CLK and CLKB have the first power supply voltage VDDL level.

The clock signal generating circuit 15 receives the external clock signal CLK_EXT and can generate a first clock signal CLK and a second clock signal CLKP which are synchronized with each other. At this time, the first clock signal CLK has a first power supply voltage VDDL level and the second clock signal CLKP has a second power supply voltage VDDS.

Figure 4 is a circuit diagram illustrating the interface circuit 25 of Figure 2 in accordance with various embodiments of the present invention.

Referring to FIG. 4, the interface circuit 25 includes a clocked gate 26 and an inverter 27. The clocked gate 26 is driven by the second power supply voltage VDDS and includes the first to third circuit portions 31-33. The first circuit unit 31 is powered by a second power supply voltage VDDS level by the output signal OUT3 of the inverter 27 and includes a plurality of PMOS transistors P2, P3 and P4. The P4 PMOS transistor has its source connected to the second power supply voltage VDDS and its gate connected to the output signal OUT3 of the inverter 27. [ The first control signal CTL1 is connected to the gate of the P3-PMOS transistor, and the drain of the P4-PMOS transistor is connected to the source thereof. The second control signal CTL2 is connected to the gate of the P2-PMOS transistor, and the drain of the P4-PMOS transistor is connected to the source thereof. The drains of the P2 and P3 PMOS transistors are connected to each other and to the output signal OUT2 of the clocked gate 26. [

The second circuit portion 32 has a source connected to the second power supply voltage VDDS and a gate connected to the second clock signal CLKP and a drain connected to the output signal OUT2 of the clocked gate 26, Respectively. The third circuit portion 33 includes the NMOS transistors N1 to N3 connected in series between the output signal OUT2 of the clocked gate 26 and the ground voltage VSS. The output signal OUT2 of the clocked gate 26 is connected to the drain of the N3-NMOS transistor, and the first control signal CTL1 is connected to the gate thereof. The source of the N3-NMOS transistor is connected to the drain of the N2-NMOS transistor, and the second control signal CTL2 is connected to the gate of the N3-NMOS transistor. The source of the N2-NMOS transistor is connected to the drain of the N1-NMOS transistor, the second clock signal (CLKP) is connected to the gate of the N1-NMOS transistor, and the ground voltage (VSS) is connected to the source thereof.

The inverter 27 is connected to the output signal OUT2 of the clocked gate 26 and is driven to the second power supply voltage VDDS. The inverter 27 inverts the logic level of the output signal OUT2 of the clocked gate 26 and outputs the output signal OUT3. The output signal OUT3 of the inverter 27 acts as a signal for supplying power to the first circuit portion 31 at the second power supply voltage VDDS level. That is, the P4 PMOS transistor is turned on by the output signal OUT3 of the inverter 27 of the logic low level, and the second power supply voltage VDDS operates as the power supply of the first circuit unit 31. [

The interface circuit 25 operates in a precharge mode when the second clock signal CLKP is at a logic low level. The P1 PMOS transistor is turned on so that the output signal OUT2 of the clocked gate 26 becomes the second power supply voltage VDDS and the output signal OUT3 of the inverter 27 is generated at the logic low level.

When the second clock signal CLKP is at a logic high level, the interface circuit 25 operates in this evaluation mode. If either of the first and second control signals CTL1 and CTL2 is at a logic low level, the output signal OUT2 of the clocked gate 26 still maintains the second power supply voltage VDDS. If both the first and second control signals CTL1 and CTL2 are at a logic high level, the N1 to N3 NMOS transistors are turned on and the output signal OUT2 of the clocked gate 26 starts discharging . The output signal OUT2 of the clocked gate 26 is discriminated to the ground voltage VSS level and the output signal OUT3 of the inverter 27 becomes a logic high level. The output signal OUT3 of the inverter 27 of the logic high level is fed back to the first circuit portion 31 so that the P4 PMOS transistor is turned off. The output signal OUT2 of the clocked gate 26 is ultimately completely de-asserted to the ground voltage VSS. In order to completely turn off the P1 PMOS transistor during this valuation mode, the second clock signal CLKP is provided at the second power supply voltage level VDDS.

4, the first circuit unit 31 is supplied with power by the output signal OUT3 of the inverter 27 to the second power supply voltage VDDS level and outputs the first and second control signals CTL1 and CTL2, May be referred to as a weak keeper device. The second circuit portion 32 is called a strong precharge device responding to the second clock signal CLKP and the third circuit portion 33 is connected to the first and second control signals CTL1 and CTL2, Strong responding to the second clock signal CLKP may be referred to as a strong evaluation device.

The interface circuit 25 receives the first and second control signals CTL1 and CTL2 of the first power supply voltage level and shifts the output OUT3 thereof to the second power supply voltage VDDS level . When the first and second control signals CTL1 and CTL2 are address signals, the interface circuit 25 simultaneously performs the addressing decoding operation and the level shifting operation. Accordingly, since the interface circuit 25 can hide the addressing decoding time and the level shifting time, it can be called a kind of zero-delay level shifter. In addition, since the interface circuit 25 has the same type of slave latch connected to the master latch of the preceding stage, it takes charge of a part of the master-slave latch type function, There is an effect of circuit reduction.

5 is a diagram illustrating a memory circuit included in an integrated circuit according to various embodiments of the present invention.

Referring to Fig. 5, the logic circuit 12b may be one of the logic circuits 12 of Fig. The memory circuit 14b may be one of the memory circuits 14 of Fig. The memory circuit 14b is connected to the logic circuit 12b and receives the address signals ADR1 and ADR2 output from the logic circuit 12b and the read enable signal RDEN. The logic circuit 12b operates in the first power supply voltage VDDL domain and the address signals ADR1 and ADR2 and the read enable signal RDEN operate as the first power supply voltage VDDL, Level and the ground voltage (VSS) level.

The memory circuit 14b operates in the second power supply voltage (VDDS) domain and includes an address decoder 41, a control signal generator 42, a word line driver 43 and a memory array 45. [ The address decoder 41 includes a plurality of interface circuits 25a and 25b for inputting the address signals ADR1 and ADR2 and the internal clock signal CLK_INT. The interface circuits 25a and 25b include the clocked gates 26a and 26b and the inverters 27a and 27b. Each of the interface circuits 25a and 25b may be configured the same as the interface circuit 25 described in Fig.

The interface circuits 25a and 25b are connected between the logic circuit 12b and the memory circuit 14b. The first interface circuit 25a operates in the second power supply voltage VDDS domain and receives the address signals ADR1 and ADR2 and the internal clock signal CLK_INT and outputs the address latch signal ADR_LAT. The address signals ADR1 and ADR2 are provided at a first power supply voltage VDDL level and the internal clock signal CLK_INT is provided at a second power supply voltage VDDS level. The first interface circuit 25a is supplied with power at the second power supply voltage VDDS level by the address latch signal ADR_LAT which is the output of the first interface circuit 25a. Similarly, the second interface circuit 25b is also supplied with power at the second power supply voltage (VDDS) level by the output of the second interface circuit 25b.

The control signal generating unit 42 includes a third interface circuit 25c for inputting a read enable signal and an internal clock signal CLK_INT. The third interface circuit 25c may be configured as shown in FIG.

Figure 6 is a diagram illustrating the third interface circuit of Figure 5 in accordance with various embodiments of the present invention.

6, the third interface circuit 25c is driven by the second power supply voltage VDDS and receives the read enable signal RDEN and the internal clock signal CLK_INT and outputs the read signal READ . The third interface circuit 25c inputs a 2-input clocked gate 26c for inputting the read enable signal RDEN and the internal clock signal CLK_INT and an output of the 2-input clocked gate 26c And an inverter 27c for outputting a read signal READ. The 2-input clocked gate 26c includes the PMOS transistors P11, P21 and P41 and the NMOS transistors N11 and N21.

P41 and P21 PMOS transistors are connected in series. The P41 PMOS transistor is connected to the second power supply voltage VDDS and is gated to the read signal READ to supply the second power supply voltage VDDS to the P21 PMOS transistor. A read enable signal RDEN is connected to the gate of the PMOS transistor P21. The P11 PMOS transistor is connected to the second power supply voltage VDDS, and the internal clock signal CLK_INT is connected to the gate thereof. The drains of the P11 and P21 PMOS transistors are connected to each other and become the output of the 2-input clocked gate 26c. The N21 and N11 NMOS transistors are connected in series between the output of the 2-input clocked gate 26c and the ground voltage VSS. The read enable signal RDEN is connected to the gate of the N21-NMOS transistor, and the internal clock signal CLK_INT is connected to the gate of the N11-NMOS transistor.

The inverter 27c receives the output of the 2-input clocked gate 26c and outputs the read signal READ. The read signal READ acts as a power supply signal for supplying the second power supply voltage VDDS to the P21 PMOS transistor. That is, the P41 PMOS transistor is turned on by the read signal READ of a logic low level, and the second power supply voltage VDDS is supplied to the P21 PMOS transistor.

When the internal clock signal CLK_INT is at a logic low level, the third interface circuit 25c turns on the P11 PMOS transistor so that the output of the 2-input clocked gate 26c becomes the second power supply voltage VDDS, The signal READ is generated at a logic low level. When the internal clock signal CLK_INT is at a logic high level, if the read enable signal RDEN is at a logic low level, the output of the 2-input clocked gate 26c still maintains the second power supply voltage VDDS. When the read enable signal RDEN is at a logic high level, the N11 and N21 emitter transistors are turned on so that the output of the 2-input clocked gate 26c is discriminated to the ground voltage VSS level, Becomes a logic high level. A read signal READ of a logic high level is fed back to the gate of the P41 PMOS transistor and the P41 PMOS transistor is turned off. The output of the 2-input clocked gate 26c is ultimately completely negated to the ground voltage VSS. In order to completely turn off the P11 PMOS transistor, the internal clock signal CLK_INT is provided at the second power supply voltage level VDDS.

5, the read signal READ output from the third interface circuit 25c of the control signal generating unit 42 in the memory circuit 14b is supplied to the delay logic unit 46 (FIG. 5) for generating the sensing enable signal SAEN ). The delay logic portion 46 receives the read signal READ and generates a sense enable signal SAEN after a delay sufficient to sense the memory cell data of the memory array 45. [

The word line driver 43 receives the address latch signal ADR-LAT output from the address decoder 41 and drives the word line WL. The memory array 45 includes memory cells 47, bit line selectors 48, and sense amplifier units 49. One memory cell 47 includes a typical CMOS SRAM cell comprised of cross-coupled inverters 47A, 47B connected to bit line pairs BL, BLB through T1, T2 emmos transistors. The gates of the T1 and T2 emmos transistors are connected to the word line WL. When the word line WL is enabled to a logic high level, the T1 and T2 NMOS transistors provide a conduction path between the inverters 47A and 47B and the bit line pair BL and BLB.

The bit line selection unit 48 connects the bit lines BL and BLB with the sense amplifier unit 49 in response to the bit line selection signal CS. The sense amplifier unit 49 senses and amplifies the voltage level of the bit line pair BL and BLB in response to the sensing enable signal SAEN and outputs a differential signal pair.

In the present embodiment, the address signals ADR1 and ADR2 and the read enable signal RDEN provided to the logic circuit 12b are signals operating at the first power supply voltage (VDDL) level. The interface circuits 25a, 25b and 25c of the memory circuit 14b receiving the address signals ADR1 and ADR2 of the first power supply voltage VDDL level and the read enable signal RDEN are connected to the second power supply voltage VDDS) level address latch signal ADR-LAT and a read signal READ. That is, each of the interface circuits 25a, 25b and 25c is supplied with power at the second power supply voltage VDDS level by the address latch signal ADR-LAT and the read signal READ, And level-shifts the read signals ADR1 and ADR2 and the read signal READ to the second power supply voltage VDDS level.

The first power supply voltage VDDL level driving the logic circuit 12b can reduce the power consumption of the integrated circuit as the level of the first power supply voltage is sufficiently lowered by the interface circuit.

Figure 7 is a flow chart illustrating the method of operation of Figure 5 in accordance with various embodiments of the present invention.

7, the logic circuit 12b generates (61) control signals of a first power supply voltage (VDDL) level that controls the memory circuit 14b. The control signals read and write the memory circuit 14b Address signals ADR1 and ADR2, a read enable signal RDEN, and the like. The memory circuit 14b receives the control signals of the first power supply voltage (VDDL) level and level-shifts it to the second power supply voltage (VDDS) level (62). The memory circuit 14b performs a write and write operation in response to the control signals level-shifted to the second power supply voltage VDDS level (63).

8 is a diagram illustrating a first example of a system including an interface circuit according to various embodiments of the present invention.

Referring to FIG. 8, the system 70 is a mobile terminal having a wireless network communication function, and may be implemented as various types of devices such as a mobile phone, a mobile PC, and a personal portable terminal. The mobile terminal system 70 performs a call function to enable a call between the caller and the called party. The calls performed by the mobile terminal system 70 include voice calls as well as video calls that enable video calls and voice calls while enabling communication.

The communication system that the mobile terminal system 70 performs may be, for example, W-CDMA (Wideband Code Division Multiple Access), EDGE (Enhanced Data Rates for GSM Evolution), LTE (Long Term Evolution), WiMAX (Worldwide Interoperability for Microwave Access) And so on. The wireless network includes a base station transmission system for transmitting and receiving wireless communication signals to and from each of the mobile terminal systems 70, a base station controller for controlling and managing a plurality of base stations, And an exchange for performing call switching between the base stations 70.

The mobile terminal system 70 includes a camera unit 71, a voice input unit 72, a wireless communication unit 73, a display unit 74, a voice output unit 75, a user input unit 76, and a control unit 78 .

The camera unit 71 performs photographing to generate an image. The camera unit 71 may include an optical unit including at least one lens to which light is incident, and an image sensor that converts the light incident through the lens into electrical data to generate an image. The image sensor of the camera section 71 may be of the RAW-Bayer and / or CMOS type operated by the image processing unit via the sensor interface. The image sensor of the camera section 71 may comprise a plurality of optical detectors configured to convert the light detected by the image sensor into an electrical signal. The image sensor may further comprise a color filter array that filters the light captured by the image sensor to capture color information.

The voice input unit 72 includes a voice sensor such as a microphone, for example, and inputs voice necessary for voice communication.

The wireless communication unit 73 is connected to the wireless network and performs communication with the partner terminal through a predetermined wireless communication scheme. The wireless communication unit 73 transmits the video call data including the video generated by the camera unit 71 and / or the audio input by the audio input unit 72 under the control of the control unit 78, And receives video call data including video and / or audio from the other terminal.

The display unit 74 displays a screen and may include a display device such as an LCD or the like. The display unit 74 can display an image generated by the camera unit 71 under the control of the control unit 78. [

The voice output unit 75 outputs voice, and may include a voice output device such as an internal speaker or the like. The audio output unit 75 may further include a connector for connection to an external audio output device such as an earphone, a headset, an external speaker, and the like, and may output audio to a connected external audio output device. The voice output unit 75 can output voice from the other party's terminal under the control of the control unit 78 during a voice call or a video call.

The user input 76 receives user input for manipulation of the mobile terminal system 70. The user input unit 76 may include a keypad having a plurality of keys for inputting numbers, characters, and the like. The keypad may be implemented in the form of a touchpad. The user input unit 76 may further include a detection sensor for detecting the motion or gesture of the user on the display unit 74 as a user input. The sensing sensor of the user input unit 76 may be implemented as a so-called touch screen provided to overlap with a display device of a panel form of a display unit 74 such as an LCD.

The control unit 78 performs overall control of the mobile terminal system 70. When the call function is selected by the user through the user input unit 76, the control unit 78 refers to the input phone number and requests the call connection to the partner terminal through the wireless communication unit 73. [ When the call connection is established, the control unit 78 transmits the call data including the image generated by the camera unit 71 and / or the voice input by the voice input unit 72 to the other party's terminal through the wireless communication unit 73 And controls the display 74 and / or the voice output unit 75 so that the video and / or voice included in the call data received from the other party's terminal through the wireless communication unit 73 is output to the display 74 and / or the voice output unit 75.

The control unit 78 performs a plurality of image processing operations on the image data captured by the image sensor of the camera unit 71 through the image processing pipeline. The processed resultant image can be displayed on the display unit 74. [ As the resolution and frame rate of image data to be processed are increased, a corresponding image signal processing system is required.

The control unit 78 may include a predetermined memory area for storing the data to be processed. The memory area in the control unit 78 may be implemented as an SRAM including the interface circuits 25a, 25b, and 25c as shown in FIG.

In the mobile terminal system 70, the camera unit 71, the voice input unit 72, the wireless communication unit 73, the display unit 74, the voice output unit 75, the user input unit 76 and the control unit 78 For example, driven to a first power supply voltage VDDL or to a second power supply voltage VDDS higher than the first power supply voltage VDDL, i.e., driven to different voltage domains. The control unit 78 of the mobile terminal system 70 includes a camera unit 71 driven by a first power voltage VDDL and driven by a second power voltage VDDS, a voice input unit 72, a wireless communication unit 73, The display unit 74, the audio output unit 75, and the user input unit 76 with the first power supply voltage (VDDL) level control signal. The control unit 78 includes a camera unit 71 driven by the second power supply voltage VDDS and driven by the first power supply voltage VDDL, an audio input unit 72, a wireless communication unit 73, a display unit 74 ), The audio output unit 75, and the user input unit 76. In this case,

The camera unit 71, the voice input unit 72, the wireless communication unit 73, the display unit 74, the voice output unit 75, the user input unit 76 and the control unit 78 of the mobile terminal system 70 And an interface circuit IF receiving the control signal of the first power supply voltage (VDDL) level and level-shifting the output signal of the second power supply voltage (VDDS) level. The interface circuit IF is supplied with the second power supply voltage VDDS by its output and receives the control signal of the first power supply voltage VDDL level in response to the clock signal, VDDS) level.

9 is a diagram illustrating a second example of a system including an interface circuit according to various embodiments of the present invention.

Referring to Fig. 9, the system 80 may be an image processing system included in the control unit 78 of Fig. The image processing system 80 includes a CPU 81, an ISP 82, an image codec unit 83, first and second memory controllers 84 and 85, an image input / output unit 86, and an interface 87 ). The image processing system 80 may further include a third memory controller 101 for controlling a memory area 102 existing therein. The memory region 102 may be implemented as an SRAM or DRAM including the interface circuits 25a, 25b, and 25c as shown in FIG. 5

The ISP (Image Signal Processor) 82 may include a Bayer processing unit, an RGB processing unit, a Scaling / Rotating / Affine-Transform processing unit, and the like. ISP 82 may be configured to control the processing of each unit such as image size, color depth, Dead Pixel Alive, Lens Shading Compensation, Adaptive Color Interpolation, Color Correction, Gamma Control, Hue / Gain Control, Image Effect, Auto Exposure, Auto White Balance, and so on. Can be controlled. The image data processed by the ISP 82 may be transmitted to the image codec unit 83 via the bus 88. [

The image codec unit 83 can perform image encoding and decoding in a form that is easy to transmit and store image data. The image codec unit 83 is configured with a JPEG codec unit (JPEG CODEC) to generate a high-resolution JPEG image. JPEG (Joint Photographic Expert Group) compresses image data on a block-by-block basis, scans the block data compressed stream at a position to be decoded from the beginning of the file,

Baseline JPEG, which is the minimum specification of JPEG compression, converts image data from RGB to YIQ, divides the image of each color component (Y, I, G) into macroblocks of 8x8 block units, performs DCT (Discrete Cosine Transform) And the resulting DCT coefficients are linearly quantized with different step sizes for each coefficient using a quantization table to separate the visually significant portions into less important portions and to save the important portions and lose the less important portions Reduce. The 8x8 block data is the minimum encoding unit. If the minimum block unit is changed, the size of the block data can be changed.

The DCT coefficients that are blocked and quantized in macroblock units are represented by one DC component (DC) and 63 AC components (AC), and the DC component is encoded by considering the correlation between adjacent signals DPCM (Differential Pulse Code Modulation), and AC components are arranged in a line by zigzag scan for each block and then subjected to run-length coding.

A JPEG image compressed by the JPEG compression method is bounded by a plurality of macroblock units, and each macro block is composed of one DC component and an EOB code indicating the end of the block. Each macroblock that constitutes a JPEG image has a DC value that is mutually dependent.

The ISP 82 corrects the image to improve the noise of the JPEG image data. ISP 82 may adjust the DC / AC coefficients of 8x8 block data. The ISP 82 separates the image area according to the DC / AC threshold value in the block data and adjusts or controls the DC / AC coefficient to reduce the noise (Noise reduction) . ISP 82 adjusts the AC coefficient to reduce blocky noise (Blocky effect reduction). In addition, the ISP 82 may apply the brightness enhancement to the block data by adjusting the DC / AC coefficient.

The CPU 81 is a microprocessor including hardware, software, and / or firmware necessary to implement the method of processing the image data described above. The CPU 81 may include a graphics processing unit (GPU), which may be referred to as a video processing unit (VPU), in handling a series of complex processes related to processing image data.

The CPU 81 can manipulate and render graphics images of interest in various electronic games and other applications. The CPU 81 may receive instruction and image data from a host, such as a software application. The instructions are used to modify the image data to specify the calculations and operations necessary to generate the rendered image.

The CPU 81 can control an additional process function such as camera function, multimedia data reproduction, and the like. The CPU 81 reduces, enlarges or crops the image data to fit the size of the display unit 74 (FIG. 7), and converts the image data to fit the color specification of the image data displayed on the display unit 74 .

The instructions or image data to be processed by the CPU 81 may be stored in the memory device 91. [ The memory device 91 may be an external memory device external to the image processing system 80. The image processing system 80 may control the memory device 91 via the first memory controller 84. The memory device 91 may be a volatile memory such as Synchronous Dynamic Random Access Memory (SDRAM). The first memory controller 84 may be an SDRAM controller for controlling the operation of the SDRAM. The memory device 91 may store a firmware of a basic input / output system (BIOS), an operating system, various programs, applications, or user interface functions.

The memory device 91 may store original image data received from the image sensor of the camera unit 611 (Fig. 8). The original image data stored in the memory device 91 may be provided to the ISP 82. [

The memory device 91 may be used for buffering or caching during operation of the image processing system 80. For example, the memory device 91 may include one or more frame buffers for buffering image data as it is output to the display portion 614 (FIG. 8). That is, the memory device 91 may store the data prior to the processing of the image data, during the processing of the image data, and after the processing of the image data.

In addition to the memory device 91, the image processing system 80 may be connected to the non-volatile storage 92 for permanent storage of image data and / or instructions. The image processing system 80 is coupled to the non-volatile storage 92 via a second memory controller 85. The non-volatile storage 92 is controlled by the second memory controller 85. Non-volatile storage 92 may be an external storage device external to image processing system 80.

Non-volatile storage 92 may include flash memory, a hard drive, or any other optical, magnetic and / or solid state storage media, or some combination thereof. The second memory controller 85 may be a flash memory controller for controlling the flash memory. Although non-volatile memory device 92 is shown as a single device in Fig. 8, non-volatile storage device 92 may include a combination of one or more of the above-described storage devices operating in conjunction with image processing system 80 .

Non-volatile storage 92 may be used to store firmware, data files, image data, software programs and applications, wireless access information, personal information, user preferences, and any other suitable data. Image data stored in the non-volatile storage 92 and / or the memory device 91 may be processed by the image processing system 80 before being output on the display.

Through the image processing system 80, the memory device 91 stores original image data captured through the image sensor of the camera unit 71 (FIG. 7), but also stores image data stored in an electronic device such as a computer have. The memory device 91 can transmit original image data or JPEG image data stored in the memory device 91 to the display unit 74 (Fig. 7) and display the same. The display portion 74 (FIG. 7) may display image data or display menus and commands as part of the user interface.

The multimedia such as the camera unit 71 (FIG. 7), the computer and / or the display unit 74 (FIG. 7) may be a multimedia processor, MMP) or an application processor (AP). The operation mode of the camera function performed by the MMP can be divided into a preview mode and a multimedia operation mode. The preview mode is for previewing before camera shooting, and the multimedia operation mode is a shooting operation performing mode by inputting camera shooting command.

The image processing system 80 may be referred to as a front-end processor for image data, and the MMP and / or AP corresponds to a subsequent processor and may be referred to as a back-end processor 93. The back-end processor 93 may be coupled to the camera portion 71 (FIG. 7), the computer, and / or the display portion 74 (FIG. 7). The image processing system 80 transmits the image data stored in the memory device 91 to the back-end processor 93 via the image input / output unit 86.

The image input / output unit 86 can transmit raw image data output from the image sensor of the camera unit 71 (FIG. 7) to the back-end processor 93. The image input / output unit 86 may transmit the adjusted image data to the size of the display unit 74 (FIG. 7) connected to the back-end processor 93. Also, the image input / output unit 86 can output the converted image data according to the color specification of the image data displayed on the display unit 74 (Fig. 7). An interface unit 87 for exchanging image data may be connected between the image input / output unit 86 and the beck-end processor 93.

The interface unit 87 may include a MIPI and / or a parallel interface for transmitting frames that are image data transmission units. The frame may contain the address and the essential protocol control information in addition to the actual image information. The frame is transmitted bit by bit, and may include a head field and a trailer field in front of and behind the data. The parallel interface is used when the image data has a low resolution and a low frame rate. The high-speed serial interface, MIPI, is used to transmit image data with high resolution and frame rate.

The CPU 81, the ISP 82, the image codec unit 83, the first and second memory controllers 84 and 85, the image input / output unit 86, and the interface unit 87 in the control unit 78 May be driven in different voltage domains, for example driven to a first power supply voltage VDDL or to a second power supply voltage VDDS higher than the first power supply voltage VDDL. The CPU 81 is connected to the ISP 82 driven by the first power source voltage VDDL and the second power source voltage VDDS, the image codec unit 83, the first and second memory controllers 84 and 85 ) And provide the first control signal of the first power supply voltage (VDDL) level to the image input / output unit 86. The CPU 81 is connected to the ISP 82 driven by the second power supply voltage VDDL and the first power supply voltage VDDL, the image codec unit 83, the first and second memory controllers 84 85), and a control signal of the second power supply voltage (VDDS) level to the image input / output unit 86.

The CPU 81, the ISP 82, the image codec unit 83, the first and second memory controllers 84 and 85, and the image input / output unit 86 respectively receive the control signal of the first power supply voltage VDDL level And an interface circuit IF for level shifting the output signal of the second power supply voltage VDDS level. The interface circuit IF is supplied with the second power supply voltage VDDS by its output and receives the control signal of the first power supply voltage VDDL level in response to the clock signal, VDDS) level.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (20)

A first circuit region driven by a first power supply voltage having a first power supply voltage level; And
And a second circuit region including an interface circuit driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level and receiving first and second control signals from the first circuit region and,
The interface circuit comprising:
A first PMOS transistor whose source is connected to the second power supply voltage and whose gate is connected to an output signal of the interface circuit;
A second PMOS transistor which is connected between a drain of the first PMOS transistor and a first node and whose gate is connected to the first control signal;
A third PMOS transistor connected between a drain of the first PMOS transistor and a first node, and having a gate connected to the second control signal;
A fourth PMOS transistor connected between the second power supply voltage and the first node and having a gate connected to the clock signal;
First to third NMOS transistors serially connected between the first node and a ground voltage and each having its gate connected to the first control signal, the second control signal and the clock signal; And
And an inverter coupled to the first node for outputting the output signal according to a signal of the first node. delete The method according to claim 1,
Wherein the first power supply voltage level is set to be lower than the second power supply voltage level. The method according to claim 1,
Wherein the clock signal is a signal that operates at a level of the second power supply voltage level and the ground voltage. delete delete delete delete delete delete delete delete delete delete delete delete delete A logic circuit driven by a first power supply voltage having a first power supply voltage level; And
And an address decoder driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level and receiving first and second address signals from the logic circuit and outputting an address latch signal, / RTI >
Wherein the address decoder comprises:
A first PMOS transistor whose source is connected to the second power supply voltage and whose gate is connected to the address latch signal;
A second PMOS transistor connected between a drain and a first node of the first PMOS transistor and having a gate connected to the first address signal;
A third PMOS transistor connected between a drain of the first PMOS transistor and a first node, and having a gate connected to the second address signal;
A fourth PMOS transistor connected between the second power supply voltage and the first node and having a gate connected to the clock signal;
First to third NMOS transistors serially connected between the first node and a ground voltage, the first to third NMOS transistors being connected to the first address signal, the second address signal and the clock signal, respectively; And
And an inverter coupled to the first node for outputting the address latch signal in accordance with a signal of the first node. 19. The method of claim 18,
Wherein the first power supply voltage level is set to be lower than the second power supply voltage level. 19. The method of claim 18,
Wherein the clock signal is a signal that operates at a level of the second power supply voltage level and the ground voltage.

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