KR101777873B1 - Stereoscopic image display - Google Patents

Abstract

A three-dimensional image display apparatus includes a first substrate of a liquid crystal display panel including a top plate common electrode to which a top plate common voltage is supplied; A first TFT formed at an intersection of any one of the data lines and the first gate line, and a second TFT formed at an intersection of the first gate line and the data line, wherein the data line is supplied with a data voltage, gate lines sequentially supplied with gate pulses synchronized with the data voltage, 1 TFT, a first storage electrode which forms a first storage capacitor together with the first pixel electrode and is supplied with a first lower plate common voltage, a second storage electrode which is connected to one of the data lines A second TFT formed at a crossing portion of the second gate line, a second pixel electrode supplied with the data voltage through the second TFT, and a second storage capacitor formed together with the second pixel electrode, A second substrate of the liquid crystal display panel including a second storage electrode to which a voltage is supplied; A first common electrode driving circuit for supplying the top plate common voltage and the first bottom plate common voltage and supplying substantially the same DC voltage in a 2D mode and a 3D mode, In the 3D mode, an AC voltage swinging from a voltage equal to the first lower plate common voltage to a voltage capable of boosting the voltage of the second pixel electrode to the black gradation voltage in the 3D mode, And a second common electrode driving circuit for supplying the second common electrode driving circuit.

Description

[0001] STEREOSCOPIC IMAGE DISPLAY [0002]

The present invention relates to a stereoscopic image display device.

The stereoscopic image display device implements a stereoscopic or 3D image using a stereoscopic technique or an autostereoscopic technique. The binocular parallax method uses parallax images of right and left eyes with large stereoscopic effect, and both glasses and non-glasses are used, and both methods are practically used. The spectacle method realizes a stereoscopic image by using polarizing glasses or liquid crystal shutter glasses to display the right and left parallax images in a direct view type display device or a projector by changing the polarization directions of the parallax images in a time division manner. In the non-eyeglass system, an optical plate such as a parallax barrier for separating the optical axis of left and right parallax images is installed in front of the display screen.

The stereoscopic image display apparatus of the glasses type is a polarizing glasses system and a shutter glasses system. In polarizing glasses, a polarization separator such as a pattern retarder should be attached to the display panel. The pattern retarder separates the polarized light of the left eye image and the right eye image displayed on the display panel. When a viewer views a stereoscopic image in a polarizing glasses type stereoscopic image display apparatus, polarized glasses are worn to observe the polarization of the left eye image through the left eye filter of the polarized glasses, and the polarization of the right eye image is viewed through the right eye filter of the polarized glasses So you can feel the three-dimensional feeling.

In a conventional stereoscopic image display apparatus using polarizing glasses, the display panel can be applied as a liquid crystal display panel. Due to the parallax between the pixel array of the liquid crystal display panel and the pattern retarder due to the thickness of the upper glass substrate of the liquid crystal display panel and the thickness of the upper polarizer, the upper and lower viewing angles are poor. In this case, when a viewer views a stereoscopic image displayed on the stereoscopic image display device of the polarizing glasses system at a vertical viewing angle higher or lower than the front of the liquid crystal display panel, the stereoscopic image displayed in the 3D Crosstalk can be felt.

Japanese Laid-Open Patent Publication No. 2002-185983 and the like propose a method of forming a black stripe on a pattern retarder of a stereoscopic image display device in order to solve the problem of 3D cross talk of a vertical viewing angle in a stereoscopic image display device of polarizing glasses have. Alternatively, the width of the black matrix formed on the liquid crystal display panel can be increased. However, if a black stripe is formed on the pattern retarder, not only the luminance of the 2D / 3D image is lowered but also the moire can be caused due to the interaction between the black matrix and the black stripe. The method of increasing the width of the black matrix lowers the aperture ratio and lowers the luminance in the 2D / 3D image.

The present invention provides a stereoscopic image display device capable of increasing a vertical viewing angle, increasing a luminance in a 2D image, and increasing an aperture ratio.

A three-dimensional image display apparatus includes a first substrate of a liquid crystal display panel including a top plate common electrode to which a top plate common voltage is supplied; A first TFT formed at an intersection of any one of the data lines and the first gate line, and a second TFT formed at an intersection of the first gate line and the data line, wherein the data line is supplied with a data voltage, gate lines sequentially supplied with gate pulses synchronized with the data voltage, 1 TFT, a first storage electrode which forms a first storage capacitor together with the first pixel electrode and is supplied with a first lower plate common voltage, a second storage electrode which is connected to one of the data lines A second TFT formed at a crossing portion of the second gate line, a second pixel electrode supplied with the data voltage through the second TFT, and a second storage capacitor formed together with the second pixel electrode, A second substrate of the liquid crystal display panel including a second storage electrode to which a voltage is supplied; A first common electrode driving circuit for supplying the top plate common voltage and the first bottom plate common voltage and supplying substantially the same DC voltage in a 2D mode and a 3D mode, In the 3D mode, an AC voltage swinging from a voltage equal to the first lower plate common voltage to a voltage capable of boosting the voltage of the second pixel electrode to the black gradation voltage in the 3D mode, And a second common electrode driving circuit for supplying the second common electrode driving circuit.

The present invention can implement an active black stripe displaying a video image in a 2D mode and a black gradation in a 3D mode in a liquid crystal display panel, thereby increasing the upper and lower viewing angles, increasing the luminance in the 2D image, and increasing the aperture ratio. Further, the present invention can drive and sequentially shift the active black stripes of the liquid crystal display panel in a line-inversion mode to reduce the flicker and the afterglow. Furthermore, the present invention can simplify the structure and manufacturing method of the common electrode driving circuit and the display panel for supplying the AC common voltage to the power consumption and active black stripes.

1 is a schematic view illustrating a stereoscopic image display apparatus according to an exemplary embodiment of the present invention.
2 is a block diagram showing driving circuits of the stereoscopic image display apparatus shown in FIG.
3 is a cross-sectional view illustrating a vertical cross-sectional structure of the liquid crystal display panel shown in FIG.
4 is an equivalent circuit diagram of a subpixel according to an embodiment of the present invention.
5 is a plan view showing an embodiment of the subpixel shown in FIG.
6 is a waveform diagram illustrating a principle of driving a 2D mode of pixels in a stereoscopic image display apparatus according to an exemplary embodiment of the present invention.
7A and 7B are waveform diagrams illustrating a principle of driving a 3D mode of pixels in a stereoscopic image display apparatus according to an embodiment of the present invention.
8 is a waveform diagram showing a method of driving an active black stripe according to the first embodiment of the present invention.
9 is a waveform diagram showing a method of driving an active black stripe according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 to 3, the stereoscopic image display apparatus according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a pattern retarder 300, polarizing glasses 310, and the like.

The liquid crystal display panel 100 displays the 2D image and the 3D image data. The liquid crystal display panel 100 includes a liquid crystal layer formed between two glass substrates. The liquid crystal display panel 100 includes pixels arranged in a matrix form by an intersection structure of the data lines DL and the gate lines GL. Each of the pixels includes a liquid crystal cell, and may be divided into R subpixel, G subpixel, and B subpixel. The subpixels are not limited to RGB subpixels and may include subpixels of white, cyan, magenta, and the like.

The TFT array substrate SUBS2 of the liquid crystal display panel 100 is provided with data lines DL, gate lines GL, thin film transistors (TFT) (PIX1, PIX2), a storage capacitor (Cst), and the like are formed. The TFT supplies the data voltage from the data line DL to the pixel electrode PIX in response to the gate pulse from the gate line GL. To this end, the drain electrode DE of the TFT is connected to the data line DL, and the source electrode SE thereof is connected to the pixel electrode PIX. The gate electrode GE of the TFT is connected to the gate line GL. 3, "GI" is a gate insulating film covering the gate metal patterns including the gate electrode GE, the gate line GL, the storage electrodes STRG1 and STRG2 and the like of the TFT. The storage capacitor Cst includes a dielectric (GI, PASSI) formed between the pixel electrodes PIX1 and PIX2, the storage electrodes STRG1 and STRG2, and the pixel electrodes PIX1 and PIX2 and the storage electrodes STRG1 and STRG2 . "SEMI" is a semiconductor channel between the drain electrode and the source electrode of the TFTs (TFT1 and TFT2), and includes an active layer and an ohmic contact layer. Quot; PASSI "is a passivation layer covering the TFTs (TFT1 and TFT2) and covering the source / drain metal including the source / drain electrodes SE and DE of the TFTs TFT1 and TFT2 and the data line DL, . The pixel electrodes PIX1 and PIX2 are formed of a transparent conductive material which is connected to the source electrode SE of the TFT through a contact hole penetrating the passivation layer PASSI. The transparent conductive material may be selected from indium tin oxide (ITO).

On the color filter array substrate SUBS1 of the liquid crystal display panel 100, a black matrix BM, a color filter CF, a top plate common electrode COM, and the like are formed. The top plate common electrode COM is formed as a single layer of the transparent conductive material without being divided over the entire pixel region.

Each of the RGB subpixels includes a main pixel portion (MP1, MP2 in Fig. 4) and an active black stripe (AB1, AB2 in Fig. 4). The main pixel units MP1 and MP2 display the video data of the 2D image in the 2D mode and the video data of the 3D image in the 3D mode. On the other hand, the active black stripes AB1 and AB2 serve as pixels for displaying video data of a 2D image in the 2D mode, while displaying black gradations in the 3D mode. Therefore, the active black stripes AB1 and AB2 increase the aperture ratio and brightness of the 2D image in the 2D mode and enlarge the vertical angle of view of the 3D image in the 3D mode. The size and shape of the main pixel unit MP1 and MP2 and the active black stripe AB1 and AB2 within one subpixel are suitably designed in consideration of the panel driving characteristic, the luminance of the display image, the viewing angle of the 3D image, .

Polarizing plates POL1 and POL2 are adhered to the TFT array substrate SUBS2 and the color filter array substrate SUBS1 of the liquid crystal display panel 100 and an alignment film for setting the pre- ALM1, and ALM2 are formed. A column spacer CS for maintaining a cell gap of the liquid crystal layer may be formed between the TFT array substrate SUBS2 and the color filter array substrate SUBS1.

The liquid crystal cells are driven by the vertical electric field between the pixel electrodes PIX1 and PIX2 formed on the TFT array substrate SUBS2 and the top plate common electrode COM formed on the color filter array substrate SUBS1 to form the color filter array substrate SUBS1, And controls the light amount of light passing through the upper polarizer POL1 formed on the upper polarizer POL1. Each of the pixels displays an image using a liquid crystal cell driven according to a video data voltage applied to the pixel electrode.

The liquid crystal display panel 100 may be implemented by a vertical electric field driving method such as a TN (Twisted Nematic) mode or VA (Vertical Alignment) mode. The liquid crystal display panel 100 may be driven in a normally white mode. The light transmittance of the liquid crystal cell becomes lower as the potential difference between the pixel electrodes PIX1 and PIX2 and the top plate common electrode COM becomes larger and the potential difference between the pixel electrodes PIX1 and PIX2 and the top plate common electrode COM becomes At the minimum, it becomes the maximum.

A backlight unit may be disposed on the back surface of the liquid crystal display panel 100. The backlight unit is implemented as an edge type or direct type backlight unit and irradiates the liquid crystal display panel 100 with light.

The pattern retarder 300 is bonded to the upper polarizer plate of the liquid crystal display panel 100. The pattern retarder 300 includes a first pattern 300a opposed to the odd-numbered line in the pixel array of the liquid crystal display panel 100 and a second pattern 300b opposed to the odd-numbered line in the pixel array of the liquid crystal display panel 100. [ (300b). The optical axes of the first pattern 300a and the second pattern 300b are different from each other. The first pattern 300a and the second pattern 300b may be implemented as a birefringent medium which delays the phase of the incident light by a quarter wavelength. The pattern retarder 300 may be implemented with a glass patterned retarder (GPR) based on a glass substrate or a film patterned retarder (FPR) based on a film substrate.

On the display screen of the liquid crystal display panel 100, the odd-numbered line can display the left-eye image and the even-numbered line can display the right-eye image. In this case, the light of the left eye image displayed on the odd-numbered line of the pixel array is incident on the first pattern 300a as linearly polarized light through the upper polarizer POL1, and the light of the right- And is incident on the second pattern 300b as linearly polarized light through the polarizing plate POL1. The linearly polarized light having passed through the upper polarizer in the odd-numbered line and the linearly polarized light having passed through the upper polarizer in the even-numbered line are linearly polarized light having the same optical axis. In the pattern retarder 300, the first pattern 300a converts the linearly polarized light of the left eye image input through the upper polarizer POL1 into the left circularly polarized light. The second pattern 300b converts linearly polarized light of the right-eye image passed through the upper polarizer POL1 into right-handed circularly polarized light.

The left eye polarizing filter of the polarizing glasses 310 passes only the left circularly polarized light and the right eye polarizing filter passes only the right circularly polarized light. When the viewer wears the polarizing glasses 310, the viewer can see only the pixels of the odd-numbered lines of the pixel array in which the left-eye image is displayed, and only the pixels of the odd-numbered lines of the pixel array in which the right- The stereoscopic effect due to the binocular disparity is felt.

The stereoscopic image display apparatus of the present invention includes a data driving circuit 102, a gate driving circuit 103, a first common electrode driving circuit 106, a second common electrode driving circuit 107, a data formatter 105, (101), a backlight driving circuit, and the like. The backlight driving circuit drives the light source of the backlight unit and performs global dimming and local dimming according to the input image under the control of the timing controller 101 to adjust the backlight brightness. The backlight driving circuit is omitted from the drawing.

Each of the source drive ICs of the data driving circuit 102 includes a shift register, a latch, a digital to analog converter (DAC), an output buffer, and the like. The source driver IC latches the digital video data (RGB) of the 2D / 3D image under the control of the timing controller 101. The source driver IC inverts the polarity of the data voltage by converting the digital video data (RGB) into an analog positive gamma compensation voltage and a negative gamma compensation voltage in response to the polarity control signal POL. The gamma compensation voltages are generated by a gamma voltage generating circuit (not shown) and supplied to the source drive ICs. The source drive ICs output the positive / negative polarity data voltages to the data lines DL in response to the source output enable signal SOE. The source driver ICs output the data voltages of the 2D image without distinguishing the left eye image and the right eye image in the 2D mode. The source drive ICs supply the data voltages of the left eye image and the right eye image to the data lines DL in the 3D mode. The source drive ICs may be connected to the data lines DL of the liquid crystal display panel 100 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driving circuit 103 includes a shift register, a level shifter, and the like. The gate drive circuit 103 applies a gate pulse (or a scan pulse) synchronized with the data voltage supplied to the data lines DL to the gate lines GL under the control of the timing controller 101 as shown in FIGS. 7 and 8, . The IC of the gate driving circuit 103 is connected to the gate lines GL of the liquid crystal display panel 100 through a TAB process or directly connected to the TFT array substrate of the liquid crystal display panel 100 by a GIP .

The first common electrode driving circuit 106 supplies a common voltage Vcom to the top plate common electrode COM and the first bottom electrode Pl to be supplied to the first storage electrode STRG1 formed in the main pixel portions MP1 and MP2, Thereby generating the common voltage Vcom1. The upper plate common voltage Vcom and the first lower plate common voltage Vcom1 are DC voltages whose voltages are constant in the 2D mode and the 3D mode. The first lower plate common voltage Vcom1 is generated with the same DC voltage as the upper plate common voltage Vcom or similar to the upper plate common voltage Vcom.

The second common electrode driving circuit 107 generates a second lower plate common voltage Vcom2 supplied to the second storage electrode STRG2 formed in the active black stripes AB1 and AB2. The second common electrode driving circuit 107 generates the voltage of the lower plate common voltage Vcom2 in all the display lines of the liquid crystal display panel 100 in the 2D mode as a DC voltage of the same potential as the first lower plate common voltage Vcom1 . The second common electrode driving circuit 107 generates the second lower plate common voltage Vcom2 in the 3D mode in two steps or in three steps of the AC voltage waveform and outputs the second lower plate common voltage Vcom2 in one display line unit of the liquid crystal display panel 100 And sequentially shifts the AC voltage waveform. The second common electrode driving circuit 107 may include a shift register and a level shifter similar to the gate driving circuit 103.

When the second lower plate common voltage Vcom2 is generated in the 3D mode by the AC voltage waveform shown in Fig. 9, the second common electrode driving circuit 107 can be realized with substantially the same circuit configuration as the gate driving circuit 103 . In this case, the gate drive circuit 103 and the second common electrode drive circuit 107 can be shared by the same IC.

The data formatter 105 receives the 3D image data from the host system 104 and separates the left eye image data and the right eye image data line by line and transmits them to the timing controller 101. The data formatter 105 transfers the 2D image data from the host system 104 in the 2D mode to the timing controller 101 as it is.

The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the host system 104, Timing control signals for controlling the operation timings of the driving circuit 102, the gate driving circuit 103, and the second common electrode driving circuit 107 are generated.

The timing control signals include a gate timing control signal for controlling the operation time of the gate driving circuit 103, a second common voltage timing control signal for controlling the operation time of the second common electrode driving circuit 107, And a data timing control signal for controlling the operation timing of the data signal line 102 and the polarity of the data voltage. The timing controller 101 receives a mode signal from the host system 104 and can generate a mode switching signal 2D / 3D for switching the operation state of the 2D / 3D mode.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP controls the start operation timing of the gate drive circuit 103. [ The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive circuit 103. The gate timing control signal is generated in the 2D mode and the 3D mode.

The second common voltage timing control signal includes a start pulse iGSP, a shift clock iGSC, an output enable signal iGOE, and the like. The start pulse iGSP controls the start operation timing of the second common electrode driving circuit 107 in the 3D mode. The shift clock (iGSC) is a clock signal for shifting the start pulse (GSP) in the 3D mode. The output enable signal iGOE controls the output timing of the gate drive circuit 103. The start pulse (iGSP) and the shift clock (iGSC) are generated in 3D mode. The output enable signal iGOE is generated as a DC signal holding a specific logic value in the 2D mode and is generated as an AC signal in the 3D mode to switch the potential of the second lower plate common voltage Vcom2 to two or three steps .

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the data sampling start timing of the data driving circuit 102. The source sampling clock SSC is a clock signal for shifting the source start pulse SSP, and controls sampling timing of data. The polarity control signal POL controls the polarity inversion timing of the data voltage output from the data driving circuit 102. [ The source output enable signal SOE controls the data voltage output timing and the charge sharing timing of the data driving circuit 102. The source start pulse SSP and the source sampling clock SSC may be omitted if the digital video data to be input to the data driving circuit 102 is transmitted in the mini LVDS (Low Voltage Differential Signaling) interface standard.

The timing controller 101 can control the operation timing of the drive circuits 102, 103, and 106 with a frame frequency of the input frame frequency xi (i is a positive integer) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The host system 104 transmits the 2D / 3D image data and the timing signals Vsync, Hsync, DE, and CLK to a timing controller (not shown) via an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling 101). The host system 104 supplies the timing controller 101 with a mode signal (Mode) indicating the 2D mode and the 3D mode. The host system 104 supplies the 2D / 3D image data and the timing signals to the timing controller 101 through the data formatter 105.

The user can select the 2D mode and the 3D mode through the user input device 110. The user input device 110 includes a touch screen, an on screen display (OSD), a keyboard, a mouse, a remote controller, and the like, which are glued or embedded on the liquid crystal display panel 100.

The host system 104 switches the 2D mode operation and the 3D mode operation in response to the user data input through the user input device 110. [ The host system 104 transmits a 2D / 3D identification code, for example, an EPG (Electronic Program Guide) of a digital broadcasting standard or an ESG (Electronic Service Guide) It is possible to distinguish the 2D mode from the 3D mode.

4 is an equivalent circuit diagram of a subpixel according to an embodiment of the present invention. 5 is a plan view showing an embodiment of the subpixel shown in FIG. Figs. 4 and 5 show two sub pixels vertically adjacent to two display lines of a liquid crystal display panel. 4 and 5, a subpixel existing in the first display line LINE # 1 is referred to as a first pixel and a subpixel present in the second display line LINE # 2 is referred to as a second pixel .

Referring to FIGS. 4 and 5, each of the first and second pixels includes a main pixel portion MP1, MP2, and active black stripes AB1, AB2.

The main pixel portion MP1 of the first pixel includes a first liquid crystal cell Clc1, a first storage capacitor Cst1, a first TFT (TFT1), and the like. The liquid crystal molecules of the first liquid crystal cell Clc1 are driven by the voltage difference between the top plate common voltage Vcom applied to the top plate common electrode COM and the data voltage supplied to the first pixel electrode PIX1, 300). The first storage capacitor Cst1 is formed between the first pixel electrode PIX1 and the first storage electrode STRG1. The first lower plate common voltage Vcom1 is supplied to the first storage electrode STRG1. The first TFT TFT1 supplies a data voltage from the data line D1 to the first pixel electrode PIX1 in response to a gate pulse supplied from n (n is a positive integer) gate line Gn. The gate electrode of the first TFT (TFT1) is connected to the n-th gate line Gn. The drain electrode of the first TFT (TFT1) is connected to the data line D1, and the source electrode thereof is connected to the first pixel electrode PIX1.

The active black stripe AB1 of the first pixel includes a second liquid crystal cell Clc2, a second storage capacitor Cst2, a second TFT (TFT2), and the like. The liquid crystal molecules of the second liquid crystal cell Clc2 are driven by the voltage difference between the common electrode voltage Vcom applied to the top plate common electrode COM and the data voltage supplied to the second pixel electrode PIX2, 300). The second storage capacitor Cst2 is formed between the second pixel electrode PIX2 and the second storage electrode STRG2. And the second lower plate common voltage Vcom2 is supplied to the second storage electrode STRG2. The second TFT (TFT2) supplies the data voltage from the data line D1 to the second pixel electrode PIX2 in response to the gate pulse supplied from the n-th gate line Gn. And the gate electrode of the second TFT (TFT2) is connected to the n-th gate line Gn. The drain electrode of the second TFT (TFT2) is connected to the data line D1, and the source electrode thereof is connected to the second pixel electrode PIX2.

The first and second TFTs TFT1 and TFT2 of the second pixel are turned on in response to the gate pulse supplied to the (n + 1) th gate line Gn + 1. The gate electrodes of the first and second TFTs TFT1 and TFT2 in the second pixel are connected to the (n + 1) th gate line Gn + 1, which is different from the first pixel. Other circuit configurations of the second pixel are substantially the same as those of the first pixel except for the gate electrode connection relationship of the first and second TFTs, and a detailed description thereof will be omitted.

6 is a waveform diagram illustrating a principle of driving a 2D mode of pixels in a stereoscopic image display apparatus according to an exemplary embodiment of the present invention.

Referring to FIG. 6, in the 2D mode, the first and second lower plate common voltages Vcom1 and Vcom2 are DC voltages substantially equal to the upper plate common voltage Vcom. In the example of FIG. 6, the top plate common voltage Vcom and the bottom plate common voltages Vcom1 and Vcom2 are illustrated at 5V for easy understanding, but the voltage applied to the liquid crystal display panel may be different from 5V. 6, Vdata is a data voltage supplied to the pixel electrodes PIX1 and PIX2 through the data line DL and the TFTs TFT1 and TFT2 and "Vg" is a gate voltage of the gate pulse supplied to the gate line GL Voltage.

When a data voltage of about 5 V set as the white gradation data voltage is supplied to the pixel electrodes PIX1 and PIX2 of the main pixel units MP1 and MP2 and the active black stripes AB1 and AB2, Clc1 and Clc2 represent the white gradation because the voltage difference between the top plate common voltage Vcom and the pixel electrodes PIX1 and PIX2 is minimum. 6, "Vclc1" is a voltage difference between the voltage of the first liquid crystal cell Clc1, that is, the voltage of the first pixel electrode PIX1, and the voltage of the top plate common electrode COM. Quot; Vclc2 "is approximately 0 V as the voltage of the second liquid crystal cell Clc2.

7A and 7B are waveform diagrams illustrating a principle of driving a 3D mode of pixels in a stereoscopic image display apparatus according to an embodiment of the present invention.

Referring to FIG. 7, in the 3D mode, the first lower plate common voltage Vcom1 is a DC voltage of approximately 5 V which is substantially equal to the upper plate common voltage Vcom. On the other hand, the second lower plate common voltage Vcom2 changes to approximately 10 V higher than the top plate common voltage Vcom immediately after the gate pulse Vg or to approximately 0 V lower than the top plate common voltage Vcom.

The first pixel electrode PIX1 of the first liquid crystal cell Clc1 is coupled to the first storage electrode STRG1 through the first storage capacitor Cst1 as shown in FIG. Since the voltage of the first storage electrode STRG1 is the first lower plate common voltage Vcom1 constant at about 5 V in the 3D mode, the voltage of the first pixel electrode PIX1 is hardly changed. The voltage Vclc1 of the first liquid crystal cell Clc1 is 0V which is the minimum voltage when the data voltage Vdata supplied to the first pixel electrode Clc1 is approximately 5V set to the white gradation voltage. Therefore, the first liquid crystal cell Clc1 expresses the white gradation when the white data voltage Vdata is supplied.

The second pixel electrode PIX2 of the second liquid crystal cell Clc2 is coupled to the second storage electrode STRG2 through the second storage capacitor Cst2 as shown in FIG. The voltage of the second storage electrode STRG2 rises to approximately 10 V or decreases to approximately 0 V immediately after the gate pulse Vg in the 3D mode. As a result, the voltage of the second pixel electrode PIX2 is boosted along the variation direction of the second lower plate common voltage Vcom2.

The data voltages are supplied to the pixel electrodes PIX1 and PIX2 of the first and second liquid crystal cells Clc1 and Clc2 in the same subpixel through the same TFT and the same data line. Accordingly, when the data voltage Vdata of 5V is supplied to the first pixel electrode PIX1 in the 3D mode, the data voltage Vdata of 5V is supplied to the second pixel electrode PIX2. In the 3D mode, the voltage of the first pixel electrode PIX1 is maintained at about 5 V, but the voltage of the second pixel electrode PIX1 is changed along the second lower plate common voltage Vcom2.

When the second lower panel common voltage Vcom2 supplied to the second storage electrode STRG2 rises to 10V, the voltage of the second pixel electrode PIX2 is boosted to a voltage close to 10V and the second storage electrode The voltage of the second pixel electrode PIX2 is boosted to a voltage close to 0V when the second lower panel common voltage Vcom2 supplied to the second pixel electrode STRG2 is lowered to 0V. Therefore, the voltage of the second liquid crystal cell Clc2 is boosted to approximately 5V, which is the black gradation voltage due to the influence of the second lower plate common voltage Vcom2 even if the white gradation data voltage Vdata is supplied. As a result, the first liquid crystal cell Clc1 expresses the white gradation while the data voltage of the white gradation is simultaneously supplied to the first and second liquid crystal cells Clc1 and Clc2, while the second liquid crystal cell Clc2 expresses the white And the black stripe is expressed by expressing the grayscale.

Since the first and second liquid crystal cells Clc1 and Clc2 are connected to the TFTs TFT1 and TFT2 which are simultaneously turned on in response to the same gate pulse Vg. The data voltage Vdata is simultaneously applied to the first and second liquid crystal cells Clc1 and Clc2 so that the gate voltage Vg is maintained at the gate high voltage VGH, When the common voltage Vcom2 is changed, the data voltage charged in the first liquid crystal cell can be changed. Therefore, in the 3D mode, the second lower plate common voltage Vcom2 must change after the gate pulse Vg so that only the data voltage charged in the second liquid crystal cells of the active black stripes AB1 and AB2 can be boosted.

8 is a waveform diagram showing a method of driving the active black stripes AB1 and AB2 according to the first embodiment of the present invention. 9 is a waveform diagram showing a method of driving the active black stripes AB1 and AB2 according to the second embodiment of the present invention.

8 and 9, "1FR" is one frame period and "1H" means one horizontal period. One frame period 1FR is one screen driving time required for data voltages to be written and maintained in the pixels of all the display lines in the liquid crystal display panel 100. [ One horizontal period (1H) is a time in which the data voltage can be written to the pixels of one display period in the liquid crystal display panel 100, and is a time obtained by dividing approximately one frame period by the number of display lines. Vgn represents the gate pulse of one horizontal period (1H) supplied to the nth gate line, and Vgn + 1 represents the gate pulse of one horizontal period (1H) supplied to the (n + 1) th gate line.

8, the second lower plate common voltage Vcom2 supplied to the second storage electrodes STRG2 of the active black stripes AB1 and AB2 in the 2D mode is the sum of the upper plate common voltage Vcom and the first lower plate common voltage Vcom2 Vcom1). As a result, the second liquid crystal cells Clc2 of the active black stripes AB1 and AB2 represent the gradation of the 2D image supplied through the data lines DL during the 2D mode period.

The second lower plate common voltage Vcom2 supplied to the second storage electrode STRG2 of the active black stripes AB1 and AB2 in the 3D mode is generated with an AC voltage of three steps.

The second lower plate common voltage Vcom2 is generated with substantially the same voltage as the top plate common voltage Vcom and the first lower plate common voltage Vcom1 during the A period overlapping with the gate pulse for every frame period in the 3D mode. Since the A period has to be overlapped with the gate pulse, it can be set to a time within one horizontal period to less than a half frame period. The A period can be appropriately adjusted according to the panel characteristics of the liquid crystal display panel 100. [

The second lower plate common voltage Vcom2 is lower than the upper plate common voltage Vcom and the first lower plate common voltage Vcom1 during the B period in which the A period is subtracted in the N (N is a positive integer) frame period in the 3D mode . During the period B, the second lower panel common voltage Vcom2 is set to a voltage capable of boosting the voltage of the second pixel electrode PIX2 to the negative black gradation voltage.

The second lower plate common voltage Vcom2 is generated at a voltage higher than the top plate common voltage Vcom and the first lower plate common voltage Vcom1 during the B period in which the A period is subtracted in the (N + 1) th frame period in the 3D mode. During the period B, the second lower panel common voltage Vcom2 is set to a voltage capable of boosting the voltage of the second pixel electrode PIX2 to the positive black gradation voltage.

The embodiment of FIG. 8 controls the polarity of the active black stripes AB1 and AB2 in mutually opposite line versions between neighboring display lines. The embodiment of FIG. 8 inverts the polarities of the active black stripes AB1 and AB2 every display line, thereby shortening the polarity inversion period of the active black stripes AB1 and AB2 to about one display line. Therefore, the embodiment of FIG. 8 can reduce the flicker between the active black stripes AB1 and AB2 that the user feels and generate the second lower plate common voltage Vcom2 by AC to reduce the DC residual image.

9, the second lower plate common voltage Vcom2 supplied to the second storage electrode STRG2 of the active black stripes AB1 and AB2 in the 2D mode is applied to the upper plate common voltage Vcom and the first lower plate common voltage Vcom1). As a result, the second liquid crystal cells Clc2 of the active black stripes AB1 and AB2 represent the gradation of the 2D image supplied through the data lines DL during the 2D mode period.

The second lower plate common voltage Vcom2 supplied to the second storage electrode STRG2 of the active black stripes AB1 and AB2 in the 3D mode is generated with an AC voltage of two steps.

The second lower plate common voltage Vcom2 is generated with substantially the same voltage as the top plate common voltage Vcom and the first lower plate common voltage Vcom1 during the A period overlapping with the gate pulse for every frame period in the 3D mode. The A period overlaps with the gate pulse as a period longer than one horizontal period and less than a half frame period. The A period can be appropriately adjusted according to the panel characteristics of the liquid crystal display panel 100. [

The second lower plate common voltage Vcom2 is generated at a voltage lower than the top plate common voltage Vcom and the first lower plate common voltage Vcom1 during the B period in which the A period is subtracted in every frame period in the 3D mode. During the period B, the second lower panel common voltage Vcom2 is set to a voltage capable of boosting the voltage of the second pixel electrode PIX2 to the negative black gradation voltage.

Since the swing width of the second lower plate common voltage Vcom2 can be reduced in the embodiment of FIG. 9, the current of the second storage electrode can be reduced, so that the power consumption and heat generation of the second common electrode driving circuit 107 can be reduced, DC residual image can be reduced. In the embodiment of Fig. 9, the second lower plate common voltage Vcom2 is generated in a two-step AC waveform similar to the gate pulse, and the voltage difference and the swing width are within a range allowed by the IC operation of the gate driving circuit 103 to be. 9, the second common electrode driving circuit 107 can be implemented by an IC of the gate driving circuit 103, and the panel of the display panel on which the GIP gate driving circuit is mounted The structure and the manufacturing method can be simplified.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

100: liquid crystal display panel 101: timing controller
102: Data driving circuit 103: Gate driving circuit
104: host system 105: data formatter
106: first common electrode driving circuit 107: second common electrode driving circuit
300: pattern retarder 310: polarizing glasses

Claims (6)

A pattern retarder for converting light incident from the liquid crystal display panel into a first polarized light through a first pattern and converting light incident from the liquid crystal display panel through a second pattern into second polarized light through a first pattern, A stereoscopic image display apparatus comprising a left eye filter through which a first polarized light passes and a polarizing eyeglass including a right eye filter through which the second polarized light passes,
A first substrate of the liquid crystal display panel including a top plate common electrode to which a top plate common voltage is supplied;
A first TFT formed at an intersection of any one of the data lines and the first gate line, and a second TFT formed at an intersection of the first gate line and the data line, wherein the data line is supplied with a data voltage, gate lines sequentially supplied with gate pulses synchronized with the data voltage, 1 TFT, a first storage electrode which forms a first storage capacitor together with the first pixel electrode and is supplied with a first lower plate common voltage, a second storage electrode which is connected to one of the data lines A second TFT formed at a crossing portion of the second gate line, a second pixel electrode supplied with the data voltage through the second TFT, and a second storage capacitor formed together with the second pixel electrode, A second substrate of the liquid crystal display panel including a second storage electrode to which a voltage is supplied; And
A first common electrode driving circuit for supplying the top plate common voltage and the first bottom plate common voltage while supplying substantially the same DC voltage in the 2D mode and the 3D mode,
In the 3D mode, the voltage of the second pixel electrode is changed from the same voltage as the first lower plate common voltage to the black gradation voltage of the second lower plate common voltage, And a second common electrode driving circuit for supplying an AC voltage swinging to a voltage capable of boosting up to a voltage.
The method according to claim 1,
Wherein the upper plate common voltage and the first lower plate common voltage,
A DC voltage generated in the 2D mode and the 3D mode to maintain a constant potential,
Wherein the first voltage is substantially the same as the first voltage.
The method according to claim 1,
And the second lower plate common voltage is generated in an AC waveform of three steps in the 3D mode.
The method of claim 3,
And the second lower plate common voltage is a voltage
Wherein the first lower plate common voltage is generated at the same voltage as the first lower plate common voltage during the first period every frame period in the 3D mode,
(N is a positive integer) frame period in the 3D mode, a voltage lower than the first lower plate common voltage during a second period that is less than the first period,
A third lower period common voltage is generated in the (N + 1) th frame period in the 3D mode for a third period minus the first period,
Wherein the first period is set to a time that is overlapped with the gate pulse and is shorter than one horizontal period and one half frame period.
The method according to claim 1,
And the second lower plate common voltage is generated in an AC waveform of two steps in the 3D mode.
6. The method of claim 5,
And the second lower plate common voltage is a voltage
Wherein the first lower plate common voltage is generated at the same voltage as the first lower plate common voltage during the first period every frame period in the 3D mode,
Wherein the first lower plate common voltage is generated at a voltage lower than the first lower plate common voltage during a second period obtained by subtracting the first period for every frame period in the 3D mode,
Wherein the first period is set to a time that is overlapped with the gate pulse and is shorter than one horizontal period and one half frame period.

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