KR101136973B1 - device and method for offering integrated security - Google Patents

Abstract

PURPOSE: An integration protective device and an integration security method are provided to simultaneously perform a device authentication and a stream encryption by changing an action mode in a process using communally a device overlapped with of a PUF(Physical Unclonable Function) circuit and a FSR(Feedback Shift Register) circuit. CONSTITUTION: An action mode control part(110) decides an authentication mode performing a device authentication and an encryption mode performing a stream encryption. An authentication part performs the device authentication using a difference of data route divided by an input data in the authentication mode. An encryption part stream-encrypts an input value through a calculation in the encryption mode. The authentication part include a plurality of operators performing a bit calculation and unit route sets including a second multiplexor with selecting one of an output of the buffers and a plurality of buffers having different route delay properties.

Description

Device and method for offering integrated security

An embodiment of the present invention relates to an integrated security device and method capable of simultaneously performing device authentication and LFSR-based data encryption through PUF.

The present invention is derived from the research conducted as part of the IT growth engine technology development project of the Ministry of Knowledge Economy and the Ministry of Information and Communication Research and Development. [Task management number: 2005-S-088-04, Task name: Information for secure RFID / USN Protection technology development].

PUF (Physical Unclonable Function) is a function that is implemented in physical structures that are easy to calculate but difficult to characterize, and the characteristics of each process, wire delay, gate delay, etc. in hardware implementation of digital logic It is a technique to find out whether a copy is made by using the effect on the copy.

The PUF circuit is a kind of random number generation circuit that uses the unpredictable delay component of the integrated circuit. Since the variation of the delay component of the integrated circuit is random and it is almost impossible to measure the integrated circuit, it has been spotlighted as a technique for blocking the replication of the integrated circuit.

PUF only allows access to genuine integrated circuits primarily through a challenge-response authentication mechanism. When a physical stimulus is applied to an electronic device including a PUF, the PUF reacts in an unpredictable manner by a random function. The applied stimulus is called a challenge, and the response of the PUF is called a response. .

On the other hand, a technique for encrypting a plain text converted to a binary string using an infinite random binary string or an infinite random number is called a stream cipher. The stream cipher is implemented through hardware such as a Linear Feedback ShiftRegister (LFSR) or a Non-linear Feedback ShiftRegister (nLFSR).

As described above, the PUF circuit plays a role as a fingerprint of a digital circuit and thus is mainly used for authenticating an electronic device. However, even after the electronic device is authenticated, in order to protect the data of the electronic device, it is necessary to apply a separate encryption algorithm, and for this, separate hardware must be provided.

An embodiment of the present invention is to provide an integrated security device and method for simultaneously performing device authentication through PUF and data security through stream encryption.

An integrated security device according to an aspect of the present invention, which achieves the above object, includes an operation mode control unit for determining an authentication mode for performing device authentication and an encryption mode for performing stream encryption, and in the authentication mode, by input data. An authentication unit performs device authentication using the determined difference in the data path, and in the encryption mode, an encryption unit configured to stream-encrypt the input value through a feedback transition operation.

Here, the authenticator performs a bit operation to implement a plurality of unit path sets and random characteristics including a plurality of buffers having different path delay characteristics and a second multiplexer for selecting any one of outputs of the buffers. It may include a plurality of operators, and the output of the last unit path set of the authentication unit may be connected to the input of the first unit path set via the calculator.

In addition, the encryption unit may include a plurality of registers for storing each bit value of the secret key for the stream cipher during the feedback transition process and the operator for performing a bit operation in the feedback transition process, the last of the encryption unit The output of the register can be connected to the input of the first register via the operator.

The operation mode controller may determine an authentication mode or an encryption mode by controlling a first multiplexer that selects one of an output of the authentication unit and an output of the encryption unit.

Further, as a lower mode of the authentication mode, a challenge mode for determining one of a plurality of paths by controlling the second multiplexer with each bit value of input data, and an authentication mode control unit for determining a random mode operating by a random function. It may further include.

The apparatus may further include a clock controller configured to control a clock signal by a signal input from the register.

According to another aspect of the present invention, there is provided a device including receiving a selection of an authentication mode for performing device authentication and an encryption mode for performing stream encryption, and in the authentication mode, using a difference in a data path determined by input data. Performing authentication and in the encryption mode, stream encrypting the input value through a feedback transition operation.

The device authentication step may include determining any one of a plurality of data paths by using each bit value of the challenge information and a second predetermined value for the input data based on a first result value according to the determined data path. The method may include performing device authentication in comparison with the result value.

According to an exemplary embodiment of the present invention, since both the device and the encryption of the stream can be performed by using only the overlapping elements of the PUF circuit and the FSR circuit, the operation mode can be changed, thereby reducing the manufacturing cost of the electronic device and miniaturizing the security module. have.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise. In addition, the terms “… unit”, “… unit”, “module”, etc. described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware or software or a combination of hardware and software. have.

1 is a block diagram schematically illustrating a configuration of an integrated security device 100 according to an embodiment of the present invention. Integrated security device according to an embodiment of the present invention, the operation mode control unit 110, authentication mode control unit 120, authentication unit 130, encryption unit 140, storage unit 150 and the clock control unit 160 Include.

The operation mode control unit 110 controls the integrated security device to operate in one of an authentication mode for performing device authentication and an encryption mode for performing stream encryption.

The authentication mode controller 120 controls the integrated security device to operate in one of a challenge mode for performing device authentication and a random mode for outputting random values by a challenge-response mechanism. Challenge mode and random mode are sub-modes of the authentication mode.

The authentication unit 130 performs device authentication by using a difference in the data path determined by the input data when the integrated security device operates in the authentication mode.

The authentication unit 130 performs device authentication using a challenge-response authentication mechanism of a physical unclonable function (hereinafter, referred to as 'PUF') in the challenge mode. Therefore, when the challenge data is input, the authentication unit 130 retrieves a challenge-response pair stored in advance from the storage unit 150 and compares the retrieved response value with the processing result value for the challenge data. If the two values are the same, the electronic device attempting to access the integrated security device is authenticated as genuine.

In the encryption mode, the encryption unit 140 performs stream encryption on the original data through a feedback transition operation. A linear feedback shift register (LFSR) or a non-linear feedback shift register (nLFSR) may be used for the feedback transition operation.

The configuration of the integrated security device in more detail is as follows. FIG. 2 is a block diagram illustrating the configuration of the integrated security device in more detail. FIG. 3 is a circuit diagram schematically illustrating each block of FIG.

The operation mode controller 110 may control the first multiplexer 150 to select an authentication mode or an encryption mode by applying one of an output of the authentication unit 130 and an output of the encryption unit 140.

The authentication unit 130 may include a plurality of buffers 131 and 132 having different path delay characteristics, a second multiplexer 133 for selecting any one of outputs of the buffers 131 and 132, and random PUF. An operator (one of 300-1 through 300-n) that performs bit operations to implement the characteristic.

When the plurality of buffers 131 and 132 and the second multiplexer 133 are defined as one path determining unit, the authentication unit 130 may include the plurality of path determining units 230-1 to 230-n and an operator. (One of 300-1 to 300-n). In this case, the output of the last path determining unit 230-n may have a feedback structure input to the first path determining unit 230-1 through the calculators 300-1 to 300-n.

In addition, when the plurality of path determining units 230-1 to 230-n and the calculators (one of 300-1 to 300-n) are combined to be one unit path set, the authentication unit 130 may include a plurality of unit path sets. (Not shown in the drawings).

In FIG. 3, since the path delay characteristics of the buffers 131 and 132 connected to the second multiplexer 133 are different from each other, the time that passes through each of the buffers 131 and 132 even when the same signal is input (this is referred to as a path delay Are also different. The authentication mode controller 120 determines the data path by controlling the second multiplexer 133 with each bit value of the challenge data in the challenge mode among the lower modes of the authentication mode.

One data path is determined for each unit path set, and one PUF result bit (for example, PUF_L1) is determined accordingly. Accordingly, the combination of the result bits PUF_L1 to PUF_Lm of the entire unit path set may determine response data for the challenge data.

The encryption unit 140 includes a plurality of registers 240-1 to 240-n and an operator (not shown in the drawing) that performs bit operations for feedback stream encryption. In the present embodiment, it is assumed that the encryption unit 140 performs encryption using LFSR.

The calculator (not shown in the figure) of the encryption unit 140 and the calculator (one of 300-1 to 300-n) of the authentication unit are preferably shared. The output of the last register 240-n of the encryption unit 140 may have a feedback structure that is input to the first register 240-1 through an operator 300-1 to 300-n.

When defining the plurality of registers 240-1 to 240-n as one stream set, the encryption unit 140 may include a plurality of stream sets (not shown). At this time, the encryption unit 140 performs an XOR operation on the bit stream (or an XOR operation of the bit streams output from the plurality of stream sets) output from one stream set selected by the clock controller 160 and the input original data. Generate encrypted data. Here, the bit stream becomes a secret key for stream encryption.

In the authentication mode, the calculators 300-1 to 300-n display the output value of the predetermined path determining unit among the plurality of path determining units 230-1 to 230- (n-1) (indicated by dotted lines in FIG. 3). And a predetermined bit operation on the output value of the last path determination unit 230-n. The result of the bit operation is fed back to the first path determination unit 230-1.

Also, in the encryption mode, the operator 300-1 to 300-n may output an output value of a predetermined register among the plurality of registers 230-1 to 230-(n-1) (indicated by a dotted line in FIG. 3). And a predetermined bit operation on the output value of the last register 230-n. As the result of the bit operation is fed back to the first register 230-1, the stored values of each register 132 are shifted by one bit (or by predetermined bit) in the feedback direction. This bit operation method is called a feedback transition operation. As the above bit operation, any one of AND, OR, and XOR may be used, and at least two or more thereof may be used in combination. The operation of the calculation unit is determined by the minimum polynomial function applied to the integrated security device.

The clock controller 160 determines which of a plurality of unit path sets or a plurality of stream sets to apply a clock to.

The clock control unit 160 preferably controls clock application according to a predetermined polynomial function that causes the LFSR to have the maximum period when the encryption unit 140 performs stream encryption. In particular, in the random mode of the lower mode of the authentication mode, the clock controller 160 controls the clock application according to a random function so that a random value is generated.

A method of performing device authentication and data encryption through the integrated security device described above is as follows.

4 is a flowchart illustrating sequentially each step of the integrated security method according to an embodiment of the present invention.

After the challenge mode is selected among the lower modes of the authentication mode (S101), and when challenge data for device authentication is input (S102), the integrated security device determines one of the plurality of data paths by using each bit value of the challenge data. (S103). Since a plurality of unit path sets exist, a plurality of determined data paths also exist.

The integrated security device retrieves a challenge-response pair corresponding to the received challenge data from a table of challenge-response pairs stored in advance from a database (S104). The response data of the challenge-response pair is then compared with the combined data of the output bit values PUF_L1 to PUF_Lm according to the determined data path (S105). If the two data are the same, the device is genuinely authenticated.

If the device authentication is successfully completed through the above process (S106), it is switched to the encryption mode for performing encryption on the data subsequently input (S107). In the encryption mode, the integrated security device generates a secret key through the feedback transition operation described above (S108), and generates encrypted data by performing an XOR operation on the generated secret key with an input value (S109).

On the other hand, if the random mode is selected from among the lower modes of the authentication mode (S110), the clock controller randomly selects a predetermined number of unit path sets from among the plurality of unit path sets (S111) so that the clock is applied only to the corresponding unit path set. . Through this, the integrated security device operates as a random function (S112).

The embodiments of the present invention described above are not implemented only through the apparatus and the method, but may be implemented through a program for realizing a function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded. The implementation can be easily implemented from the description of the above-described embodiments.

In addition, although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

1 is a block diagram briefly illustrating a configuration of an integrated security device according to an embodiment of the present invention.

2 is a block diagram showing the configuration of an integrated security device in more detail.

FIG. 3 is a circuit diagram schematically illustrating each block of FIG. 2 as electronic elements.

4 is a flowchart illustrating sequentially each step of the integrated security method according to an embodiment of the present invention.

Claims (10)

An operation mode controller configured to determine an authentication mode and an encryption mode; A plurality of output bit generators for generating a plurality of output bits, respectively; And A secret key generation unit for generating a secret key using the plurality of output bits in the encryption mode, Each of the plurality of output bit generators includes a plurality of registers, In the authentication mode, the operation mode controller controls the plurality of output bit generators to generate a challenge response including the plurality of output bits according to a path delay characteristic corresponding to a data path determined according to input data, and the challenge response. Storing an initial value obtained according to a path delay characteristic corresponding to the determined data path at the time of generation in the plurality of registers, And the operation mode controller in the encryption mode controls the plurality of output bit generators to generate the plurality of output bits based on the initial values of the plurality of registers. The method of claim 1, Each of the plurality of output bit generators, A plurality of unit path sets for generating output values according to path delay characteristics; And A plurality of first multiplexers respectively corresponding to the plurality of unit path sets and the plurality of registers and selecting one of an output value of a corresponding unit path set and an output value of a corresponding register; The plurality of unit path sets form a chain by the plurality of first multiplexers in the authentication mode, Wherein the plurality of registers form a chain by the plurality of first multiplexers in the encryption mode. Integrated security device. 3. The method of claim 2, Each of the plurality of unit path sets, A plurality of buffers having different path delay characteristics, A second multiplexer for selecting any one of the outputs of the buffers Integrated security device. The method of claim 3, Each of the plurality of output bit generators And one or more calculators configured to calculate some or all of the output values of the plurality of first multiplexers and provide the calculated values to the first unit path set and the first register. Integrated security device. 5. The method of claim 4, Wherein said at least one operator corresponds to an XOR operator. delete The method of claim 3, And an authentication mode controller for providing challenge data to the second multiplexer as a control signal for controlling the second multiplexer in a challenge mode. The method of claim 3, And a clock controller configured to generate a plurality of clock signals based on values of some of the plurality of registers of the plurality of output bit generators. The plurality of clock signals correspond to the plurality of output bit generators, respectively. Each of the plurality of clock signals corresponds to a clock signal for a plurality of registers of a corresponding output bit generator. In the integrated security method performed by the integrated security device, Outputting a challenge response to a plurality of output ports according to a path delay characteristic corresponding to a data path determined according to input data in the authentication mode; Storing an initial value obtained according to a path delay characteristic corresponding to the determined data path when outputting the challenge response in the authentication mode in a plurality of registers; Changing a mode from the authentication mode to an encryption mode; Outputting a plurality of output bits to the plurality of output ports based on the initial values of the plurality of registers in the encryption mode; Generating a secret key by operating the plurality of output bits in the encryption mode. 10. The method of claim 9, Generating a clock signal for the plurality of registers based on a value stored in some of the plurality of registers in the encryption mode.

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