KR100650729B1 - Method for forming 3-dimension package - Google Patents

Abstract

The present invention discloses a method of manufacturing a three-dimensional stack package, the present invention is a first step of providing a wafer having a plurality of bonding pads in the cell region and a plurality of first via holes in the peripheral region; Forming a first photoresist pattern exposing a first via hole on a first surface on which the device of the wafer is formed; Attaching a dummy wafer onto a wafer including the first photoresist pattern; A fourth step of exposing the first via hole by grinding a second surface of the wafer while holding the dummy wafer; A fifth step of forming a metal film covering the first via hole by performing a sputtering process on the entire surface of the second surface of the wafer where the first via hole is exposed; Forming a second photoresist pattern exposing a portion corresponding to the first via hole on the metal layer; A seventh step of forming a first via pattern by plating the first via hole; An eighth step of removing the second photoresist pattern; A ninth step of patterning the metal film to form a metal trace; A tenth step of etching the dummy wafer to form a second via hole in a portion corresponding to the first via hole; An eleventh step of forming a single package by plating the second via hole to form a second via pattern in contact with the first via pattern; A twelfth step of stacking single-piece packages obtained by sequentially performing the first to eleventh steps on a substrate in a Z-axis direction; And a thirteenth step of attaching solder balls to the lower portion of the substrate.

Description

Manufacturing method of three-dimensional stack package {METHOD FOR FORMING 3-DIMENSION PACKAGE}

1A to 1I are cross-sectional views illustrating a method of manufacturing a three-dimensional stack package according to the present invention.

The present invention relates to a method for manufacturing a package, and more particularly, to a method for manufacturing a three-dimensional stack package that can protect the surface of the wafer active region by applying a dummy wafer.

As the demand for miniaturization, light weight, and high performance of electronic products increases, the technology of the package is also progressing accordingly. A lot of research is going on to stack a wafer as a next generation package to implement a system on package. This system-on-package technology uses dummy wafers to protect semiconductor chips and active area surfaces when stacking wafers in three-dimensional packages.

In order to reduce the thickness of the wafer in the three-dimensional package process, the back surface of the wafer is back ground with a tape attached to the active surface of the wafer, and a metal trace is wired on the back of the wafer. The photoresist is coated.

However, in the related art, when the backgrinding process is performed with the tape attached to the surface of the active region of the wafer, when the photoresist is applied on the backside of the wafer, when the sputtering or plating process is performed, the wafer is fixed. The wafer active area surface comes into contact with the wafer chuck, thereby causing damage to the active area surface of the wafer or the wafer chuck. In addition, when the wafer is too thin, the wafer is broken during the process.

Accordingly, the present invention has been made to solve the conventional problems as described above, by applying a dummy wafer to protect the surface of the wafer active area, it is possible to prevent the phenomenon of damage to the active area of the wafer and the breakage of the wafer The purpose is to provide a method of manufacturing a three-dimensional stack package.

In order to achieve the above object, the present invention, a first step of providing a wafer having a plurality of bonding pads in the cell region, a plurality of first via holes in the peripheral region; A second step of forming a first photoresist pattern exposing the first via hole on a first surface on which the device of the wafer is formed; Attaching a dummy wafer onto a wafer including the first photoresist pattern; A fourth step of grinding the second surface of the wafer while the dummy wafer is fixed to expose the first via hole; A fifth step of forming a metal film covering the first via hole by performing a sputtering process on the entire surface of the second surface of the wafer where the first via hole is exposed; Forming a second photoresist pattern on the metal layer to expose a portion corresponding to the first via hole; A seventh step of forming a first via pattern by plating the first via hole; An eighth step of removing the second photoresist pattern; A ninth step of patterning the metal film to form a metal trace; Etching the dummy wafer to form a second via hole in a portion corresponding to the first via hole; An eleventh step of forming a single package by plating the second via hole to form a second via pattern in contact with the first via pattern; A twelfth step of stacking single-piece packages obtained by sequentially performing the first to eleventh steps on a substrate in a Z-axis direction; And a thirteenth step of attaching solder balls to the lower portion of the substrate.

After attaching the dummy wafer, the step of carrying out curing is added.

In the fixing of the dummy wafer, the dummy wafer is placed on a vacuum chuck and fixed by vacuum suction.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1I are cross-sectional views illustrating a method of manufacturing a 3D stack package according to the present invention.

In the method of manufacturing a 3D stack package according to the present invention, as shown in FIG. 1A, first, a plurality of bonding pads 1a are provided in a cell area and a plurality of first via holes 2 are provided in a peripheral area. The wafer 1 is provided. Reference numeral 3 not described in FIG. 1A corresponds to a protective film.

As shown in FIG. 1B, a first photoresist film (not shown) is coated on the first surface on which the device of the wafer 1 is formed, and then exposed and developed to expose the first via hole 2. The resist pattern 5 is formed.

As shown in Fig. 1C, the dummy wafer 7 is attached to the first surface of the wafer including the first photoresist pattern 5, and then cured.

As shown in FIG. 1D, in the state where the dummy wafer 7 is fixed by the vacuum suction method using the vacuum chuck 21, the back grinding process 31 is performed on the second surface of the wafer to form the first via hole ( 2) is exposed.

As shown in FIG. 1E, after the vacuum is released to the vacuum chuck, the backgrinded wafer is transferred into a separate sputtering apparatus to perform a sputtering process to form a metal film 9 covering the first via hole 2. .

As shown in FIG. 1F, a first photoresist film (not shown) is coated on the first surface of the wafer including the metal film 9, and exposed and developed to expose a portion corresponding to the first via hole 2. The resist pattern 11 is formed. At this time, in the second photoresist film coating step, the wafer including the metal film 9 is placed on the vacuum chuck 21, and the photoresist is supplied while rotating while being fixed by the vacuum suction method.

As shown in FIG. 1G, a first via pattern 13 is formed by gap filling the first via hole region exposed by the second photoresist pattern using plating. Thereafter, the second photoresist pattern is removed. Subsequently, the metal film is patterned to form a metal trace 9a.

As shown in FIG. 1H, the dummy wafer 7 is etched to form a second via hole 8 in a portion corresponding to the first via hole 2. Subsequently, the metal film 15 is deposited on the dummy wafer 7 including the second via hole 8, and then the gap vias of the second via hole 8 are contacted with the first via pattern 13 as described above. The second via pattern 17 is formed to complete the production of the single piece package A.

As shown in FIG. 1I, the single-packages obtained by sequentially performing the above-described processes of FIGS. 1A to 1H on the substrate 19 are stacked in the Z-axis direction, and then solder balls 21 are disposed on the lower portion of the substrate. Attach to complete 3D stack package manufacturing.

In FIG. 1I, three individual packages are stacked, but one or more packages may be manufactured by stacking more than one.

As described above, the present invention proceeds to a three-dimensional package process. When backgrinding, photoresist coating, and sputtering are performed, the surface of the active region of the wafer, which is sensitive to the wafer chuck, can be touched to prevent damage.

According to the present invention, the grinding process is performed in a state in which the dummy wafer is attached to the back side of the wafer, so that the wafer is maintained at a predetermined thickness, thereby preventing the wafer from being broken due to the backside grinding process.

Claims (3)

A first step of providing a wafer having a plurality of bonding pads in the cell region, the wafer having a plurality of first via holes in the peripheral region; A second step of forming a first photoresist pattern exposing the first via hole on a first surface on which the device of the wafer is formed; Attaching a dummy wafer onto a wafer including the first photoresist pattern; A fourth step of grinding the second surface of the wafer while the dummy wafer is fixed to expose the first via hole; A fifth step of forming a metal film covering the first via hole by performing a sputtering process on the entire surface of the second surface of the wafer where the first via hole is exposed; Forming a second photoresist pattern on the metal layer to expose a portion corresponding to the first via hole; A seventh step of forming a first via pattern by plating the first via hole; An eighth step of removing the second photoresist pattern; A ninth step of patterning the metal film to form a metal trace; Etching the dummy wafer to form a second via hole in a portion corresponding to the first via hole; An eleventh step of forming a single package by plating the second via hole to form a second via pattern in contact with the first via pattern; A twelfth step of stacking single-piece packages obtained by sequentially performing the first to eleventh steps on a substrate in a Z-axis direction; And Attaching a solder ball to a lower portion of the substrate; 3D stack package manufacturing method comprising a. The method of claim 1, further comprising the step of attaching the dummy wafer and then curing. The method of claim 1, wherein the fixing of the dummy wafer comprises placing the dummy wafer on a vacuum chuck and fixing the dummy wafer by a vacuum suction method.

Images