KR100435924B1 - Single-electron memory cell arrangement - Google Patents

Abstract

Each memory cell of an array has a single-electron transistor and a single-electron memory element. The single-electron transistor is driven by a charge stored in the memory element. When a read voltage is applied, a current flows through the single-electron transistor which is dependent on the stored charge, but the stored charge in not changed. When a write voltage is applied, the magnitude of which is greater than the read voltage, then the stored charge is changed. The memory cells of the array are each connected between first lines and transverse second lines of a memory cell configuration.

Description

[0001] SINGLE-ELECTRON MEMORY CELL ARRANGEMENT [0002]

DRAM (DRAM) cell devices are mainly made using CMOS technology. The DRAM includes a memory cell having a read transistor and a capacitor. The information to be stored is stored in the capacitor in the form of a charge. The signal charge is about 50 fC, or 300,000 electrons. The capacitances of the capacitors are 20 to 30 fF in modern memory cells. In future memory devices with increased packing density, the area per memory cell decreases. This makes it more difficult and ultimately impossible to make a capacitor having a relatively high storage capacitance of 20 to 30 fF on an area available on the memory cell. The size of the transistor to be read can not be reduced unlimitedly.

From the viewpoint of miniaturization, so-called single-selection components, in which the switching process is affected by a single electron, are limited. A study of this type of single electronic component is described in W. R. Snerner et al., Microelectronics, vol. 27, pp. 55-58. A single electronic component includes a tunnel element connected to an adjacent terminal through a tunnel contact. The charge traverses these tunnel contacts through the quantum-mechanism tunneling effect and the thermal overcoming of the potential barrier, and such charge transfer occurs occasionally. The tunnel element is made, for example, as a small conductive land surrounded by an insulating structure.

<e/(2C)을 만족하면, 그러면 상기 열 에너지가

<<

를 만족시키지 않는 한, 상기 터널 엘리먼트의 전하는 전위 상태 때문에 변할 수 없다. 이러한 경우 k는 볼트만 상수이고, T는 온도이고, e는 전자의 전하이고, C는 터널 엘리먼트의 정전용량이다.When a voltage U is applied to the two terminals, a Coulomb barrier condition is met for the voltage,

If < e / (2C) is satisfied, then the thermal energy

<<

The charge of the tunnel element can not be changed because of the potential state. In this case, k is the Boltzmann constant, T is the temperature, e is the charge of the electron, and C is the capacitance of the tunnel element.

When a higher voltage is applied, electrons can flow through one of the tunnel contacts to the tunnel element. This single electronic component operates in such a way that one electron is delivered simultaneously.

It is possible to cause a current to flow through the tunnel element by driving the tunnel element through a gate electrode which capacitively affects the tunnel element without a tunneling effect occurring in the operating voltage range. When an appropriate charge operates on the gate electrode, the single electronic component has a nearly linear current-voltage characteristic that passes through the origin. This type of gate control single electronic component is literally referred to as a single electron transistor.

K. Nakazato et al., J. Appl. Phys., Vol. 75, No. 10, 1994, pages 5123-5134 proposed a single electronic memory cell. It contains three so-called multiple tunnel elements. The term " multiple tunnel element " refers to a tunnel element of a series circuit connected to each other through a tunnel contact. The multi-tunnel element has a side gate electrode through which the current through the multiple tunnel elements can be controlled. The first multiple tunnel element and the second multiple tunnel element are connected in series between the first voltage source and ground. The two multiple tunnel elements are connected to each other through a memory node. The side gate electrode of the multiple tunnel element is connected to a second voltage source or a third voltage source.

The memory node is connected to a fourth voltage source through a capacitor. The memory node is connected through a capacitor to a third multiple tunnel element connected between a fifth voltage source and ground. The third multiple tunnel element is driven by the side gate electrode connected to the sixth voltage source.

The third multiple tunnel element acts as an information potentiometer that can know the information by considering the charge on the memory node. Measurements while a high negative voltage is applied to the side gate electrodes of the second multiple tunnel element may be made as long as the voltage applied to the multiple tunnel elements meets the Coulomb barrier condition, As shown in Fig. Depending on the voltage applied to the side gate electrode, the discrete number of electrons may be stably stored in the memory element formed by the memory node and the first multi-channel element. This means that the electrostatic energy of the memory element for a corresponding number of stored electrons is metastable. Between neighboring metastable states, the electrostatic energy has a potential barrier and the top of the potential barrier has a higher potential than the adjacent metastable state. The height of the potential barrier depends on the number of stored electrons and the number of tunnel junctions in multiple tunnel elements.

A single electronic memory cell is made of GaAs doped with a delta type. Since six voltage sources are required to operate a single electronic memory cell, driving multiple memory cells is a sophisticated operation.

It is an object of the present invention to provide a single electrode memory cell device with reduced demand for driving.

This problem is solved by a single electronic memory cell device comprising a single electronic memory element and a memory cell having a single electron transistor. Each memory cell is connected between a first line and a second line. The memory cell device includes a parallel first line and a parallel second line, wherein the first line and the second line intersect with each other. The first line and the second line correspond to word and bit lines in the latest DRAM device.

In a single electronic memory cell device according to the present invention, since each memory cell is connected between one of the first lines and one of the second lines, each memory cell has a voltage corresponding to the associated first line and the associated second line By applying a level, it can be driven in a simple form.

26kΩ 이라면,R_K는 클리칭 저항이고, h는 플랑크 상수이고, e는 전자의 전하이고, 그러면 전하 전송의 대부분은 기초적인 처리에 의해 발생한다. 상기 터널링 저항은 100kΩ보다 바람직하게 크고, 상기 기초적인 처리는 전하 전송에서 우세하다. 상기 제 1게이트 전극은 제 2라인에 접속된다. 상기 단일 전자 트랜지스터는 제 1단자를 통하여 제 1라인 및 제 2단자를 통하여 제 2라인에 접속된다. 상기 메모리 노드에 접속된 제 2게이트 전극을 통하여 용량적으로 구동될 수 있을 것이다.The single electronic memory element includes at least one tunnel element connected to the first line through the first tunnel contact and connected through a second tunnel contact to a memory node that can be capacitively driven through the first gate electrode. The charge is transferred through the tunnel contact by a quantum-mechanical tunneling effect and a sufficiently infrequent heat to overwhelm the potential barrier. If the tunneling resistance is R _T > R _K = h / e ²

If _k is 26 _k , then R _K is the clipping resistance, h is the Planck constant, and e is the charge of electrons, then most of the charge transfer is caused by the underlying process. The tunneling resistance is preferably greater than 100 k [Omega], and the basic process is dominant in charge transfer. The first gate electrode is connected to the second line. The single electron transistor is connected to the second line via a first terminal and a second terminal through a first terminal. And may be capacitively driven through a second gate electrode connected to the memory node.

The memory element and the capacitance of the single electron transistor are matched in such a way that upon application of the read voltage by a single electron transistor, the current flows in dependence on the charge stored in the memory element. The charge stored in the memory element does not change in this case. However, the charge stored in the memory element may be varied by applying a write voltage of a magnitude greater than the read voltage.

The present invention has found that a single electron transistor is a precision electrometer for the charge operating on the gate electrode of a single electron transistor. The read voltage is selected in such a way that the Coulomb barrier condition is satisfied. The current flowing through the single electron transistor depends on the charge on the memory node since the memory node is connected to the second gate electrode of the single electron transistor. At the same time, the variation in charge stored on the memory node can be prevented by the fact that the read voltage applied to the first gate electrode is not sufficient to vary the electrical charge on the memory node. In this case, the fact that the number of electrons that can be stably stored in multiple tunnel elements depends on the number of tunnel contacts in the multi-tunnel element and on the gate voltage at which the multi-tunnel element is driven.

The capacitances of a single electronic memory element and a single electronic transistor are matched to each other in such a way that the Coulomb barrier condition is met for a single electron transistor and a change in the charge state of a single electronic memory element is not possible when a read voltage is applied. However, when the magnitude of the write voltage is larger, the change in the change state of the memory node is affected.

A voltage level corresponding to the read voltage is applied between the associated first and second lines to drive a memory cell to read information. The remaining first and second lines are connected to the same potential as the selected first line so that all the cells not belonging to the selected second line have no voltage applied thereto. To write an information item to a memory cell, a voltage level corresponding to the write voltage is applied between the associated first and second lines. The remaining first and second lines are connected in such a manner that the voltage drop level across the remaining memory cells is lower and the stored charge is unchanged. For example, the remaining line may be applied with a read voltage or a voltage level corresponding to the difference between the write and read voltages.

The capacitance of the memory element and the single electron transistor is preferably made such that the magnitude of the read voltage is one-half the write voltage magnitude. When information is written to the memory cell, in this case it is possible that the remaining first and second lines have a read voltage applied to the line, and the voltage drop across any unselected memory cell is always the same Do. The remainder of the unselected memory cell does not have a voltage applied to the line.

The memory element preferably includes a plurality of tunnel elements connected in series through the tunnel contact. The reference to the first tunnel contact portion and the second tunnel contact portion also applies to such a tunnel contact portion. The first tunnel element is in this case connected to the first line through the first tunnel contact and the last tunnel element in series is connected to the memory node through the second tunnel contact. The effect of providing multiple tunnel contacts in the memory element is that the number of stable charge states of the memory element is increased for a fixed voltage at the first gate electrode.

Any structure that includes an electrically conductive region and is electrically isolated from the conductive region neighbor by the insulating structure can be observed as a tunnel element. The electrically conductive region is connected by a tunnel contact through the insulation structure. A particularly stable structure as a tunnel element is a structure comprising a conductive core and an insulating shell surrounding the conductive core. The diameter of the tunnel element is preferably between 1 and 10 nm in this case. The capacitance of the tunnel element is sufficiently small to such an extent that the memory cell device operates in the room temperature range. In particular, fullerence comprising metal clusters or metal cores with organic ligands as insulating shells, as described in German Patent No. 4212 220 Al, is particularly suitable as a tunnel element.

Moreover, the lithographically constructed thin metal layer is suitable as a tunnel element, and the tunnel contact is caused by the oxidation of such a metal layer and the deposition and structure of additional metal layers.

Within the electronic structure of the molecular form, the appropriate tunnel element is a section of an individual molecule carrying different charges according to the last order. The charge is transferred between these types of variable charge molecular sections according to chemical bonds.

~26kΩ 이고, R_K는 클리칭 저항이고, h는 플랑크 상구이고, e는 전자의 전하이고, 메모리 셀의 전기적인 응답은 터널 접촉부에 의하여 충분히 정확하게 결정되고, 제 1라인 및 제 2라인의 정전 용량 및 전압 레벨 및 라인 저항 및 AC 임피던스는 무시할 수 있고, 소정의 시간에 하나의 접촉부를 통하여 단지 하나의 터널링 만이 발생한다고 가정하면, 상기 남아있는 터널 접촉부는 상기 터널링 이벤트 동안에 캐패시터로서 간주될 수 있으며, 모든 터널 접촉부는 동일한 정전 용량을 가지며, 상기 메모리 셀 장치의 남아있는 메모리 셀의 용량적인 기여는 무시할 수 있는 조건하에서, 아래의 조건은 메모리 엘리먼트에 안정적인 전하 상태에 대하여 만족된다.Wherein a tunneling resistance of the tunnel contact portion satisfies R _T > R _K = h / e ²

And ~ 26kΩ and, R _K is a Hinckley called resistance, h is Planck's Shangqiu, e is the charge of the electron, the electrical response of the memory cell is determined sufficient exactly by the tunnel contacts, the first line and a power failure of the second line The capacity and voltage levels and line resistance and AC impedance are negligible and assuming that only one tunneling occurs through one contact at a given time, the remaining tunnel contacts can be considered as capacitors during the tunneling event , All tunnel contacts have the same capacitance, and under the condition that the capacitive contribution of the remaining memory cells of the memory cell device is negligible, the following condition is satisfied for the stable charge state in the memory element.

m = 1 + n?

=

=

C _G : capacitance of the first gate electrode

C: capacitance of the tunnel contact portion in the memory element

n: number of tunnel contacts of the memory element

V: voltage at the first gate electrode

I: Number of electrons stored in the memory element

e: charge of electrons

For memory cells assuming stable states + e and -e at the time of application of the _write voltage (± V _write ), stable charge state conditions are

The condition that the zero electron charge state is unstable when the _write voltage V _write is applied is as follows.

In particular, the charge state (+ e) must be stable when the read voltage V _read is applied. In other words,

Furthermore, the Coulomb barrier state must be satisfied for a single electron transistor.

V _read <C _Σt

C _Σt is the total capacitance of the transistor

The total capacitance of a single electron transistor is given by the sum of the capacitance of the tunnel contact forming the single electron transistor and the total capacitance of the second gate electrode.

These conditions are met for the following voltages and capacitances:

V _read =

C _Σt ≤

The present invention is not limited to such capacitance values. Selecting a different read voltage V _read , examining the entire non-identical range, defining a different and / or more stable charge state with respect to the read or write voltage, or determining whether the tunnel contact is of a stable reference having a different capacitance By assuming induction, other criteria for the capacitance can be determined in a similar fashion.

The invention will be described in more detail below with reference to figures and examples.

1 is a schematic circuit diagram of a memory cell device;

2 is a plan view of a memory cell;

Figure 3 is a corresponding circuit diagram for the memory cell shown in Figure 2;

4 is a characteristic curve of a memory cell.

[Description of Drawings]

G1: first gate electrode G2: second gate electrode

SK: memory node L1: first line

L2: second line T _1, T _2, T _3, T _4, T _5, T ₆ : tunnel element

The memory cell devices comprise a first line (L1) substantially parallel to one another and a second line (L2) substantially parallel to one another. The first line L1 intersects the second line L2 (see FIG. 1).

The memory cell device includes a memory cell (S) connected between one of the first lines (L1) and one of the second lines (L2), respectively. By driving one of the first lines L1 and the second line L2, each of the memory cells S can be apparently driven.

Each of the memory cells includes six tunnel elements T ₁ , T ₂ , T ₃ , T ₄ , T ₅ , and T ₆ connected to each other through a tunnel contact TK. The first tunnel element T ₁ is connected to one terminal of the first line L ₁ through the first tunnel contact TK ₁ . The last tunnel element T ₆ connected in series is connected to the memory node SK via the second tunnel contact TK ₂ . The memory node SK may be capacitively driven through the first gate electrode G ₁ . The first gate electrode (G ₁₎ and said memory node (SK) the Memory cell device (2 and 3), the first gate electrode (G ₁₎ and memory notes in the operating voltage intended in between (or Lt; RTI ID = 0.0 &gt; no &lt; / RTI &gt; The first gate electrode G1 is connected to one of the first lines L2.

A first gate electrode (G1), the memory node (SK) and the tunnel elements _{(T 1, T 2, T} 3, T 4, T 5, T 6) a tunnel contact disposed between _{(TK 1, TK, TK 2} ) (T ₁ , T ₂ , T ₃ , T ₄ , T ₅ , T ₆ ) having one or more memory elements form one memory element.

Furthermore, each memory cell is connected to one terminal of the first line L ₁ through the first transistor tunnel contact TK ₃ and is connected to one terminal of the second line L ₂ through the second transistor tunnel contact TK ₄ . And a transistor tunnel element T connected to one terminal. The transistor tunnel element T is driven through a second gate electrode G ₂ connected to the memory node SK. Wherein the distance between the second gate electrode G ₂ and the transistor tunnel element T capacitively drives the drive and the tunneling between the second gate electrode G ₂ and the transistor element T causes the memory cell Is sufficiently large that it does not occur at the operating voltage of the device. The transistor tunnel element T, the first transistor tunnel contact TK3, the second transistor tunnel contact TK4 and the second gate electrode G2 form one electronic transistor.

The tunnel elements T ₁ , T ₂ , T ₃ , T ₄ , T ₅ and T ₆ are made, for example, as conductive lands with circular cross-section on the insulating surface. The tunnel elements T ₁ and T ₆ are made of, for example, gold, aluminum or titanium having a diameter of 3 nm. The insulating surface on which the memory cells are aligned is the surface of the SiO ₂ layer aligned on the silicon substrate. The memory cell device may be aligned on a sapphire substrate.

The distance between the neighboring tunnel elements T ₁ , T ₂ , T ₃ , T ₄ , T ₅ and T ₆ and the size of the tunnel contacts TK ₁ , TK and TK ₂ are, for example, about 2 nm. The memory node SK and the second gate electrode G2 and the first gate electrode G1 and the lines L1 and L2 are made, for example, as metal regions on the insulating surface. They are made of gold, aluminum or titanium. The distance between the first gate electrode G1 and the memory node SK is, for example, 5 nm.

The size of the memory node SK is about 3 nm.

)의 크기는 약 2nm이다. 제 2게이트 전극(G2) 및 상기 트랜지스터 터널 엘리먼트(t) 사이의 거리는 5nm이다.The transistor tunnel element T is formed as a conductive land of gold, aluminum or titanium having a round cross section with a diameter of 3 nm. The terminals connecting the first line (L1) and the second line (L2) are made as metal interconnections of gold, aluminum and titanium. The distance from the transistor tunnel element to the terminal connecting the first line (L1) or the second line (L2) and the distance between the transistor tunnel contact

) Is about 2 nm. The distance between the second gate electrode G2 and the transistor tunnel element t is 5 nm.

The required area per memory cell is about 500 nm ² . A 1T bit memory cell device can be made on a 5 cm ² area.

The memory cells are fabricated by depositing individual metal atoms on an insulating surface with the aid of a scanning tunneling microscope or an atomic force microscope.

Alternatively, the surface width metal layer having a thickness of 3 nm may be constituted by lithography, in particular by electron spinning or synchrotron radiation, or by oxidation with a scanning probe microscope.

The non-conductive gaps between the tunnel elements can be created by using the oxidation and lithography method of the original metal layer and reactive ion etching.

By way of example, the tunneling resistances of the tunnel contacts TK ₁ , TK, TK ₂ are 100 kΩ in each case and the associated capacitance is 1aF in each case. The capacitance of the first gate electrode (C _G ) is 1aF. The capacitance of the transistor tunnel contacts TK3 and TK4 is 1aF in each case. The capacitance of the second gate electrode G2 is 0.3 aF in each case. The total capacitance of a single electronic memory transistor is

_{C Σt = 2 · C t +} C tg = 0.5 aF

The memory cell is operated with a read voltage (V _read ) of 0.32 volts and a write voltage of 0.64 volts.

The operation of the memory cell will be described below with reference to the memory cell characteristic curve shown in Fig. Fig. 4 shows the first characteristic curve K1 and the second characteristic curve K2. The first characteristic curve K1 relates to the case when the charged state (+ e) is stored in the memory element. The second characteristic curve K2 relates to the case when the charged state (-e) is stored in the memory element. If a voltage (+ V _read ) is applied between the first line (L1) and the second line (L2) and the charged state (+ e) is stored in the memory element, then a current of about 0.8 [ Flows through the transistor. However, if the charged state (-e) is stored in the memory element, then no current flows through the transistor when a voltage of + V _read is applied.

When a voltage of -V _read is applied, if a charged state (+ e) is stored in the memory element, no current flows through the transistor, and if the charged state (-e) is stored in the memory element , - a current of 0.8 μA flows.

If the charged state (+ e) is stored, when the write voltage (+ V _write ) is applied, the current increases and when the level (+ V _write ) is reached, the unstable zero charge state is passed, The charge state (-e) is written to the memory element. If a charged level (-e) is stored when a voltage level (-V _write ) is applied to record in the charged state (+ e), an unstable zero state is passed and the stable zero state passes , The charged state (+ e) is written to the memory element. The read voltage V _read is maintained in such a manner that the charge change of the stable charge state (-e and + e) is prevented, although a clear distinction between the charged state (-e and + e) Is selected.

SUMMARY OF THE INVENTION The present invention provides a single electrode memory cell device that is less susceptible to damage to the drive.

Claims (7)

In a single electronic memory cell device, A parallel first line and a parallel second line traversing the first line are provided, - a memory cell is provided which is respectively connected between one of the first lines and one of the second lines, Each of said memory cells having a single electronic memory element and a single electron transistor, The single electronic memory element includes at least one tunnel element connected to a first line through a first tunnel contact and connected to a memory node that can be capacitively driven through a first gate electrode through a second tunnel contact In addition, The first gate electrode is connected to the second line, Said single electron transistor being connected to a first line through a first terminal, to a second line through a second terminal, to be capacitively driven through a second gate electrode, The second gate electrode is connected to a memory node, and Wherein the capacitance of the memory element and the single electron transistor is such that when applying a read voltage having a magnitude less than the write voltage between the first line and the second line by a single electron transistor the current dependent on the charge stored in the memory element Characterized in that the charge stored in the memory element is formed in such a way that the charge stored in the memory element flows unvariably and the charge stored in the memory element is variable when applying a write voltage between the first line and the second line. Cell device. The method according to claim 1, Wherein the capacitance of the memory element and the single electron transistor is such that the magnitude of the read voltage is one-half the magnitude of the write voltage. 3. The method according to claim 1 or 2, Wherein the memory elements comprise a plurality of tunnel elements each connected in series through a tunnel contact, Wherein the first tunnel element is connected to the first line through the first tunnel contact and the last tunnel element is connected in series to the memory node through the second tunnel contact. The method of claim 3, Wherein each of the tunnel elements has substantially the same capacitance. 5. The method of claim 4, The capacitance of the memory element and the single electron transistor is determined by the following conditions:

V _read =

C _Σt ≤

Lt; / RTI &gt; Where C is the capacitance of the tunnel contact of the memory element, C _G : capacitance of the first gate electrode, C _Σt is the total capacitance of a single electron transistor, n is the number of tunnel contacts of the memory element, V _read : read voltage, And V _{write is a} write voltage. 3. The method according to claim 1 or 2, Wherein each of the tunnel elements comprises a conductive core and an insulating shell surrounding the conductive core, Wherein the conductive core and the insulating shell have a diameter between 0.1 nm and 10 nm. 3. The method according to claim 1 or 2, Wherein each of the tunnel elements comprises a sub-region of the original surface-width metal layer and a non-conductive gap.

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