KR100431102B1 - method of making ladder diagram for programmable logic controller using discrete event model and an apparatus thereof - Google Patents

Abstract

The operational characteristics of the programmable logic controller are modeled using a discrete event model to create a state diagram. The state for drawing the state diagram is defined as the internal output state, timer output state, counter output state and external output state of the programmable logic controller, and each state except the external output state is set and It is divided into reset status for stopping. On the other hand, the input signal is defined as the logical product of the input state and the input event, and the transition to its own state is defined when the event continues to maintain its current state even after the input. The action of transitioning to the next state by arc alone indicates the state of simultaneous occurrence. Based on the state diagram created in this way, it is converted into a Brianian equation. First, the input signal to each state is processed for each output, and whether the input state is included or not, and then the input signal of each state is reconstructed. Arrange and convert to Brian equations. The logical product of the converted blion equation is connected in series, and the logical sum is connected in parallel.The general type of input signal is converted into contact point a, which is normally open contact, and the complementary input signal is converted into contact point b, which is normally closed contact. Ladder diagrams can be completed by placing input events on the left and output states on the right.

Description

Method for making ladder diagram for programmable logic controller using discrete event model and an apparatus

The present invention relates to a method for generating a process control algorithm in a process automation system, and more particularly, to a method for generating a ladder diagram automatic transformation for designing a programmable logic controller based on a discrete event model.

A programmable logic controller (PLC) is a sequence control device that performs a computer-like function with input, output, memory, and operation control units. Programmable logic controller is a device used in industrial control business. It has high reliability, simple maintenance, and low price. Therefore, it has been developed steadily while replacing the existing hardwire type sequential control device. It is used for automation in almost all factories such as chemical plants and manufacturing plants, monitoring control of oil pipelines, and various sequence controls for the purpose of instructing the order and controlling the operation of unit machines.

In order to control the process with such a programmable logic controller, a user program according to the control object, that is, a control algorithm, must be written. General-purpose languages such as C ++, Pascal, etc. may be used to write control algorithms, but these high-level languages are too general and complicated to be handled by field users, and the details of hardware to run the configured hardware. There is a difficulty to keep track of.

In order to solve this problem, in the programmable logic controller, ladder diagram, instruction list, function block diagram, sequential function chart, structured text, etc. Program language is used, and ladder diagram, which is a graphic control language, is commonly used. However, in order to control the system by creating a ladder diagram, the user must decide how to control the system sequentially and prepare a ladder diagram considering the simultaneous and asynchronous nature of each process. However, existing ladder diagrams require skilled programmers, and even experienced programmers can rely on experience and methods to create ladder diagrams through trial and error. There is a lack of flexibility in modifying the created ladder diagram.

The present invention has been made in order to solve the above-mentioned disadvantages, and shows the operating characteristics of the system in each state and event, and uses a discrete event model to describe the operation specifications of the system by the occurrence and transition of the state. It is an object of the present invention to provide a method for automatically converting from a discrete event model to a ladder diagram so that even an inexperienced person can easily create a ladder diagram.

Another object of the present invention is to provide a method for automatically generating a ladder diagram by easily changing and modifying a system even if its operating specifications change.

It is still another object of the present invention to provide a method for automatically generating a ladder diagram that can easily detect an error when an error occurs in a programmable logic controller and to easily identify and correct the cause of the error.

1 is a block diagram illustrating a system for implementing and testing a ladder diagram automatic conversion method according to the present invention.

2 is a schematic block diagram showing the overall configuration of the present invention.

3A is a flow diagram conceptually illustrating a Brianian equation transformation algorithm for obtaining the Brianian equation from a state diagram of the method of the present invention.

FIG. 3B is a flow diagram illustrating a ladder diagram generation algorithm for creating a ladder diagram from a Brianian equation in the method of the present invention. FIG.

4 is a flowchart specifically illustrating the flowchart of FIG. 3A.

5 is a configuration diagram of a work system according to a first embodiment of the present invention.

6 is a discrete event model for a work system according to a first embodiment of the present invention.

7 is a diagram illustrating a ladder diagram which is the final output according to the first embodiment of the present invention.

8 is a configuration diagram of a work system according to a second embodiment of the present invention.

9 is a discrete event model for a work system according to a second embodiment of the present invention.

10 is a diagram illustrating a ladder diagram which is the final output according to the second embodiment of the present invention.

11 is a view showing a correspondence between components of a state diagram and a ladder diagram according to the method of the present invention.

* Description of the symbols in the drawings *

110: design system 120: programmable logic controller

130: work system 140: RS-232C communication cable

210: state diagram 215: Brian equation transformation algorithm

220: Brian equation 225: ladder diagram generation algorithm

230: ladder diagram 510: conveyor belt

520: SEN1 (product lower limit detection sensor) 530: SEN2 (product upper limit detection sensor)

540: cylinder (defective product discharge) 550: counter (number of finished products)

810: robot 811: chuck 820: product

830: point A plate 840: point B plate

In order to achieve the above object, in the automatic ladder diagram generation method of the present invention, a system is modeled using a discrete event model, and a blion equation is derived from each state using a conversion algorithm, and then automatically converted into a ladder diagram.

That is, the method for automatically generating a ladder diagram for a programmable logic controller according to the present invention includes providing a discrete event model expressing an operating characteristic of the programmable logic controller as a computer input, each state of the discrete event model from the discrete event model. Or obtaining a brian equation representing the event, converting the brian equation into a ladder diagram and outputting a ladder diagram.

Here, the discrete event model is preferably a state diagram, wherein each state constituting the state diagram includes an internal output state, a timer output state, a counter output state, and an external output state of the programmable logic controller. Each state in the group, except the external output state, is divided into set state for operation and reset state for stop, and the input signal is defined by the logical product of the input state and the input event. If the user wants to maintain the operation of the current state, it is displayed to transition to his own state, and the state occurring at the same time is written in such a manner that the transition to the next state occurs without occurrence of an event.

In addition, the step of obtaining the brian equations, for each output state of the state diagram, processing an input signal for each state, processing whether or not to include the input state, rearranging the input signal of each state And converting the rearranged input signals into a blian equation. Here, in the input signal processing step, the input signal for each state is stored by dividing the set state and the reset state for each state, and in the step of processing whether the input state is included or not, when the corresponding state is the set internal output state, If the input signal has the set input state and the input event, the input product and the logical product of the input event are stored again.If the input signal has the reset input state and the input event, only the input event is saved again, and the state is reset. If the input signal has both an input state and an input event, only the input event is stored again. If only the input state has an input state, the input state is stored again. If the corresponding state is a counter output state or timer output state, the set state and If the input signal has both the input state and the input event for each reset state, only the input event is saved again. If it has only the input state is stored again, if the state is the external output state, the input signal is stored, and in the step of rearranging the input signal of each state, if the state is the internal output state, the set internal output state And OR of each stored input state and event for each of the reset internal output states and the reset internal output states, and then logically calculates the complement type of the reset internal output state and the set internal output state, and if the corresponding state is a counter output state or a timer output state. In the step of ORing the stored input states and events by the set state and the reset state, and when the state is the external output state, the OR operation is performed on the stored input states and events, and the input signal is converted into a brian equation. Converts the set input state and the reset input state of the input into an input state with no distinction between the set state and the reset state. The.

In addition, the state diagram may be provided as a computer input by processing each state and event constituting the state diagram into a table form including an input state and an input event and an output state according to the input state and the input event.

On the other hand, the step of converting the Brianian equation into the ladder diagram again, the logical product is converted into a series connection, the logical sum is converted into a parallel connection in the Briann equation, the usual input signal in the Brianian equation is always open contact, the complement form It is preferable to generate a ladder diagram so that the input signal of is converted into a normally closed contact, and the input signal is arranged to the left and the output state to the right.

Another example of a method for automatically generating a ladder diagram for a programmable logic controller according to the present invention includes operating characteristics of the programmable logic controller, and each state includes an internal output state, a timer output state, a counter output state, and an external state of the programmable logic controller. The states are divided into states in the group including the output states, and the states are divided into set states for operation and reset states for stop, respectively, and the input signal is defined as the logical product of the input state and the input event, and the event is inputted. If the user wants to maintain the current state even after the operation is completed, the state transition to one's own state is indicated, and at the same time, the state diagram indicating the transition to the next state without occurrence of an event is provided as the input of the computer. For each state constituting the state diagram, if the state is the set internal output state, After the input signal inputted as the state is stored in the set internal output state storage space of the corresponding array type, and the stored input signal has the set input state and the input event, the logical product of the input state and the input event is set to the set internal output state. If the input signal has a reset input state and an input event, only the input event is stored in the set internal output state storage space again, and each input stored in the set internal output state storage space of the array type. When the signal is ORed and the state is the reset internal output state, the input signal inputted to the state is stored in the reset internal output state storage space of the corresponding array type, and then the input signal stores both the input state and the input event. If so, only the input event is saved in the reset internal output state storage space. And storing the input state again in the corresponding reset internal output state storage space, and performing an OR operation on each input signal stored in the reset internal output state storage space of the array type, and performing the OR operation on the set internal output state input signal; Computing the complement form of the reset internal output state input signal, which is the OR operation, generates a blun equation of the internal output state, and when the state is a counter output state, respectively, the input signal of the set state and the reset state is respectively corresponded. If the stored input signal has both an input state and an input event after storing in an array type set counter output state storage space and a reset counter output state storage space, only the input event is set counter output state storage space or reset counter output state. Save it back to the storage space and set the input state if it has only input state. And re-storing the input output state storage space or the reset counter output state storage space, and performing an OR operation on each input signal stored in the array type set counter output state storage space and the reset counter output state storage space. Generates a blon equation of a reset counter output state, and when the state is a timer output state, an array type set timer output state storage space and a reset timer output state storage space corresponding to input signals of the set state and the reset state, respectively If the stored input signal has both an input state and an input event, the input event is stored in the set timer output state storage space or the reset timer output state storage space again, and the input state corresponds to the input state. Set timer output state storage or reset timer output state storage And then blob equations of the set timer output state and the reset timer output state are generated by performing an OR operation on each of the input signals stored in the array type set counter output state storage space and the reset counter output state storage space. When the state is an external output state, each input signal stored in the external output state storage space of the array type after storing the set state and the reset state in an external output state storage space of a corresponding array type without being distinguished. Generates a Boolean equation of the external output state by performing a logical OR operation, converts the generated set input signal and reset input signal of each of the brian equations into input signals without distinction between the set state and the reset state. Generating a Ryanian equation, wherein the logical product is a series connection in the final Brianian equation; And converting the conventional input signal into a constant open contact and converting a complementary input signal into a normally closed contact, generating a ladder diagram so that the input signal is placed to the left and the output state is to the right. It is made, including.

On the other hand, the apparatus for automatically generating a ladder diagram for a programmable logic controller according to the present invention includes a storage device and a processing device connected to the storage device, and the storage device stores a program for controlling the processing device. The processing apparatus operates together with the program, receives a discrete event model representing an operating characteristic of a programmable logic controller, and converts the discrete event model into a brian equation representing each state or event of the discrete event model. And convert the Brianion equation into a ladder diagram.

Another apparatus according to the present invention includes at least one storage device and a processing device connected to the storage device, wherein the storage device stores a program capable of controlling the processing device, and the processing device includes the processing device. Operating with the program, the operational characteristics of the programmable logic controller are divided into states in a group including the internal output state, timer output state, counter output state and external output state of the programmable logic controller, The states are divided into a set state for operation and a reset state for stop, respectively, and the input signal is defined as the logical product of the input state and the input event, and if the user wants to maintain the current state after the event is entered, It is indicated to transition to its own state, and at the same time, the transition occurs to the next state without the occurrence of an event. When the state is set internal output state for each state constituting the state diagram, the input signal inputted in the state is set internal output in a corresponding array form in the storage device. After storing in the state storage space, if the stored input signal has a set input state and an input event, the logical product of the input state and the input event is stored again in the set internal output state storage space, and the input signal is reset with the reset input state and input. If there is an event, only the input event is stored in the set internal output state storage space again, and an OR operation is performed on each input signal stored in the set internal output state storage space of the array type, and the state is a reset internal output state. Storing the reset internal output state in the form of a corresponding array in the storage device; If the input signal has both an input state and an input event, only the input event is stored in the reset internal output state storage space. If the input signal only has the input state, the input state is stored in the reset internal output state storage space. And performing a logical sum operation on each of the input signals stored in the reset internal output state storage space of the array type, and performing a complementary operation on the set internal output state input signal obtained by performing an OR operation and the reset internal output state input signal obtained by performing an OR operation. A logical multiplication operation to generate a brian equation of an internal output state, and when the state is a counter output state, an input signal of a set state and a reset state is respectively stored in the storage device in the form of a set counter output state in the form of a corresponding array; After the reset counter output state is stored in the storage space, the stored input signal is inputted with the input state. If you have all the events, only the input events are stored in the set counter output status storage or reset counter output status storage space. If you have only input status, the input status is saved in the corresponding set counter output status storage or reset counter output status storage space. It stores again, and generates a blion equation of the set counter output state and the reset counter output state by performing an OR operation on each of the input signals stored in the array type set counter output state storage space and the reset counter output state storage space. When the state is a timer output state, the input signals of the set state and the reset state are respectively stored in the set timer output state storage space and the reset timer output state storage space of the corresponding array type in the storage device, and then the stored input signals. Has an input status and an input event Store only the set timer output state storage space or reset timer output state storage space again, and if only the input state is stored, store the input state again in the set timer output state storage space or reset timer output state storage space, Logic sum operation is performed on each input signal stored in the set counter output state storage space and the reset counter output state storage space of to generate a blion equation for the set timer output state and the reset timer output state, respectively. In this case, the data is stored in an external output state storage space of a corresponding array type in the storage device without distinguishing between a set state and a reset state, and then the logical sum operation of each input signal stored in the external output state storage space of the array type is performed. Generates a brian equation of the external output state, and each of the generated brian Converts the set input signal and the reset input signal of the equation into an input signal having no distinction between the set state and the reset state to generate the final blun equation of each state, and in the final blun equation, the logical product is a serial connection and the logical sum is a parallel connection In the final blun equation, the input signal is converted into a normal open contact, and the complementary input signal is converted into a normally closed contact, thereby generating a ladder diagram so that the input signal is placed to the left and the output state is to the right.

According to the present invention, a control algorithm can be easily configured by a user-computer interface using a discrete event model. And by designing the ladder diagram by module, it is easy to partially modify and change the ladder diagram due to the system change, so it is more flexible, and when the error occurs in the programmable logic controller, the error can be easily detected and the cause of the error can be identified. Easy to modify Furthermore, the present invention automatically converts a control algorithm written in the form of a discrete event model into a ladder diagram, so that the user does not need to know or understand the actual code, so that the unskilled user can easily write the control algorithm. In addition, according to the present invention, it is possible to intuitively grasp the execution operation by defining an event and a state using a discrete event model, and there is no need to set input / output contacts separately.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a system for implementing and testing a ladder diagram automatic conversion method according to the present invention.

As shown in FIG. 1, the method of the present invention may be implemented using a design system 110 such as a personal computer. The design system 110 may be connected to a programmable logic controller (PLC) 120 using an RS-232C cable 140, and may be connected to a programmable controller (PLC) using a ladder diagram automatically generated by the design system 110. 120 may be operated. When the operation of the PLC 120 is confirmed through the test, the PLC 120 may be connected to the actual work system 130 and used for process automation.

The method of the present invention can be largely divided into two stages, and FIG. 2 shows a block diagram showing these two stages. That is, the process of deriving the brian equation 220 by applying the brian equation transformation algorithm 215 to the discrete event model (for example, the state diagram 210) representing the operational characteristics of the work system and the derived brian The ladder diagram generation algorithm 225 is applied to the equation 220, and the ladder diagram 230 is automatically generated.

The operating characteristics of the work system can be represented using various discrete event models, but in particular, the present invention proposes a ladder diagram generation method using a state diagram (state diagram or finite state machine or automata) 210. However, you can create ladder diagrams in a similar way for other discrete event models.

In order to prepare a state diagram 210 provided as an input for creating a ladder diagram, first, each state and events of the state diagram are defined as follows.

1) State is normally defined as internal output state, timer output state, counter output state and external output state of programmable logic controller.

2) Each state except the external output state is divided into set state for operation and reset state for stop.

3) The input signal is defined as the logical product of the input state and the input event.

4) Transition to one's own state is defined when it wants to maintain the current state after the event is input.

5) An action where a transition to the next state by arc only without occurrence of an event indicates a state that occurs at the same time.

A state diagram created according to such a definition will appear as shown in FIG. 6 or 9. In order to create such a state diagram, a software tool for creating a state diagram may be provided in the design system, and a table representing an input and an output of each state is extracted from the created state diagram, and the ladder is formed using the extracted table type input. You can also create a diagram. When using a tabular input, the input shown in Table 1 below is used. Table 1 is prepared based on the state diagram shown in FIG. 6 and shows only a part of the state diagram.

Table 1. Input table extracted from the state diagram.

In the present invention, a ladder diagram is automatically generated by inputting a state diagram or a table as shown in Table 1. 3A and 3B are flowcharts illustrating each of the two steps of the present invention in more detail. 3A is a flow diagram conceptually illustrating a Brianian equation transformation algorithm for obtaining the Brianian equation from a state diagram of the method of the present invention.

As shown in FIG. 3A, first, an input signal is processed for each output state (S310). If there is more than one input signal, all of the two or more input signals are ORed together. After processing the input signal, it is processed whether or not to include an input state (S320). In this way, the input signals of the respective states can be rearranged in a simple form (S330). The rearranged input signal is converted into a brian equation (S340).

A method for generating a ladder diagram using the transformed Brianon equation is shown in FIG. 3B. That is, first, the logical product is connected in series and the logical sum is connected in parallel (S350), and the normal input signal is converted into a normally open contact (a contact), and the input signal of the complement type is converted into a normally closed contact (b contact) (S360). This is done by creating a ladder diagram. At this time, in the ladder diagram, the input signal is on the left and the output state is on the right.

Now let's take a closer look at the process of generating the Brianion equation. 4 is a flowchart illustrating the process of FIG. 3A in more detail. On the other hand, the description of the space for storing the variable name and the associated information used in the flow chart of Figure 4 is shown in Table 2. An example of a state diagram for applying such a method is given as shown in FIG. 6 or 9, and the state diagrams shown in FIGS. 6 and 9 are described according to the states and events defined above. Details of the state diagram shown in FIGS. 6 and 9 and an operation thereof will be described later. In the flowchart of FIG. 4, the symbol “==” indicates that the values of the variables located on both sides of the symbol are the same, and the symbol “=” indicates that the value of the variable on the right side of the symbol is substituted into the variable value on the left side of the symbol.

<Internal output status>

First, it is determined whether the state is the internal output state ( Y _i == M _i ?) (S400).

If the determination result in the step S400 output state is the internal output, the internal output state in step S410M _i Is setM _{i, s} Authorization or reset statusM _{i, r} Determine authorization. Next, internal output stateM _i Is setM _{i, s} The respective internal output states in step S412.M _{i, s} Input signal input toM _{i, s} [n] To save. Step S414 is a step of determining whether to include an input state among the input signals, and the internal output state.M _{i, s} Input signal toY _jr ·P _j If it is an input event from the input signal in step S416P _j Save the bay,M _{i, s} Input signal toY _{j, r} ·P _j is notY _{j, s} ·P _j If the input signal in step S418Y _{j, s} ·P _j Save together. In step S420, an OR operation is performed on the input signals in steps S416 and S418.

On the other hand, the input signal if it is determined in step S410 as a reset condition M _{i, r} inside the output state, the output state M _i reset state at step S422 M _{i, r} is stored in the M _{i, r} [n]. Step S424 is a step of determining whether the input signal is taken together with or that the input state to the input event has only input, the input state Y _j, M in the step S426, if only have a _{s i, r} [n] input state Y in _{Only j, s} is stored, and if the input signal has both an input state and an input event, only the input event P _j is stored in M _{i, r} [ n ] in step S428. Step S430 performs an OR operation on the input signals in steps S426 and S428.

In the next step S432, the output state in step S420M _{i, s} And the output state in step S430M _{i, r} Input state in step S490 after performing the AND operation on the complement form ofY _{j, s} WowY _{j, r} ofY _j Converting to derives a Brianian equation for the internal output state.

<Counter output status>

On the other hand, if the output state is not the internal output state in step S400, it is determined in step S440 whether the output state is a counter output state. If the output state is a counter output state, in step S442, the input signal of the counter set state C _{i, s} is stored in C _{i, s} [ n ], and the input signal of the reset state C _{i, r} is C _{i, r} [ n ] Store each in. In the next step S444, it is determined whether the input signal has only the input state or the input state and the input event, and if the input signal has the input state and the input event together, the input event P _j is changed to C _{i, s} [ n ] and C _{i, r} [ n ], respectively, are stored in the input space of the corresponding output, and if only the input state is stored in the input space of the corresponding outputs of C _{i, s} [ n ] and C _{i, r} [ n ] in step S448. Store input state Y _{j, s} respectively. In step S450, the OR operation is performed on the input signals in steps S446 and S448 for the output states of the set states C _{i, s} and the reset states C _{i, r} of the counter, and then in step S450, the input states Y _j, Converting _s and Y _{j, r} to Y _j derives a bbrian equation for the counter output state.

<Timer output status>

In addition, if it is not the counter output state in step S440, it is determined whether the output state is a timer output state in step S460. If the output state is a timer output state, the set state of the timer in step S462T _{i, s} The input signal ofT _{i, s} [n] And reset statusT _{i, r} The input signal ofT _{i, r} [n] Respectively. In the next step S464, it is determined whether the input signal has the input state only or the input state and the input event together.P _j OnlyT _{i, s} [n] AndT _{i, r} [nStore each in the input space of the corresponding output, and if only the input state is present, in step S468T _{i, s} [n] AndT _{i, r} [nInput status in input space of corresponding output of]Y _{j, s} Store each of them. In step S470, the set state of the timer.T _{i, s} And reset statusT _{i, r} Input state in step S490 after performing an OR operation on the input signals in steps S466 and S468 for each output state.Y _{j, s} WowY _{j, r} ofY _j Converting to a derivation of the Brian equation for the timer output state.

<External output status>

On the other hand, if the timer output state at step S460 and stores the input signal to the external output state in step S480 to P _i [n]. In the next step S482, after performing the OR operation on the input signal of the step S480 and converting the input states Y _{j, s} and Y _{j, r} into Y _j in step S490, a bbrian equation for the external output state is derived.

This derives all of the blan equations for each state: the internal output state, the counter output state, the timer output state and the external output state.

As shown in FIG. 3B using the derived blion equation, logical products are connected in series, logical sums are connected in parallel, and the general input signals, that is, Y _j and P _j are normally open contacts a. Input signal in the form of complement, Converts to the normally closed contact b. An example of the correspondence between each output state of the state diagram and each component of the ladder diagram is shown in the table of FIG. In the ladder diagram, the input signal is placed on the left and the output state is placed on the right.

In this way, a ladder diagram which is a control algorithm of the programmable logic controller is finally generated. An example of the generated ladder diagram is shown in FIG. 7 or 10 .

Table 2. Definitions and descriptions of each variable in FIG.

The method of the present invention is expressed as pseudo code as follows.

***** Capital Code *****

＃ define

Y _j : jth input state

M _i : i-th internal output state

M _j : j th input state

P _i : i-th external output state

P _j : jth input contact (input switch, detection sensor, etc.)

C _i : i-th counter output status

C _j : jth counter input status

T _i : i-th timer output status

T _j : jth timer input status

M _{i, s} [ n ]: Input signal storage space in the set state of the _i internal output state M _i

M _{i, r} [ n ]: Input signal storage space of reset state of _i internal output state M _i

C _{i, s} [ n ]: Input signal storage space of the set state of the i th counter output state C _i

C _{i, r} [ n ]: Input signal storage space of reset state of i th counter output state C _i

T _{i, s} [ n ]: Input signal storage space of set state of i th timer output state T _i

_{T i, r [n]:} i of the reset state of the second timer output state T _i input signal storage

P _i [ n ]: Input signal storage space of i th external output state P _i

＃＃＃＃＃ Example ＃＃＃＃＃

Now, a method of automatically converting and generating a ladder diagram from the method of the present invention through two embodiments will be described in detail.

<First Embodiment>

5 shows a working system according to a first embodiment of the present invention, in which a product is moved on a conveyor belt, a part of a factory where the finished product counts and the defective product is discharged out. The operating specifications of the system will be described in detail. When the product is moved in the direction of the arrow of the conveyor belt 510 and the object is detected by the lower limit detection sensor SEN1 520, a timer is operated. When the product continues to move and the object is detected by the upper limit detection sensor SEN2 530, the timer is stopped and the number of products is counted using the counter 550. If object detection fails in the upper limit detection sensor SEN2 530, the cylinder 540 is operated after 5 seconds to be regarded as a defective product and the product is discharged out.

FIG. 6 is a diagram illustrating a discrete event model in consideration of operating characteristics of the system illustrated in FIG. 5. The definitions of the variables for the input contact point and the output state of the discrete event model of FIG. 6 used to explain the process of converting to the Brianian equation with reference to the discrete event model of FIG. 6 are described in Table 3. Referring to Figure 6 and Table 3 will be described in detail the process of deriving the Brianian equation.

Table 3. Variable definitions for the input contacts and output states of the first embodiment.

1) Starting internal output status: M _l

When deployed in accordance with the flow chart shown in Figure 4 to start the internal output state M _l In step S412 M _{l, s} [n], the set state of M _l M _{l, s} input signal P _l of the · M _{l, r} and M _{l, s} is stored respectively. In the next step S414, since the input state M _{i, r} exists in the reset state, the process proceeds to step S416, where M _{l, r} becomes 1 and M _{l, s} [ n ] = P _l . Also be a _{M l, s [n] =} M l, s saved in step S418, when a logical OR of the input signals S416 and S418 from the step S420 sets the state of the M _l M _{l, s} input signal of the M _{l, s} = P _l + M _{l, s} On the other hand, the reset state M _{l, r} of the input signal of M _l is the M _{l, s} · P ₀ in step S422. As a result of the determination in the next step S424, since the input signal in the reset state is the logical product of the input event and the input state, the input state M _{l, s} is set to 1 in step S428, and only the input event P ₀ is stored, and the reset state of M _l in step S430 M _{l, r} of the input signal is a M _{l, r} = P _0.

M _l M _l set _state, a reset state and M _{s l,} process all of the input signals _r hayeoteumeuro internal start by step S432 of the output states is Becomes In the next step S490, the input state M _{l, s} is converted into M _l . Becomes

2) Lower limit detection sensor (SEN1) internal output status: M ₂

When the internal output state M ₂ of the lower limit detection sensor is developed in accordance with the flowchart shown in FIG. 4, the input signals of the set state M _{2, s} of M ₂ in M ₂ are M _{l, s} P ₂ and M _{2, s} in step S412. Three state M _{2, s} input signal of the M ₂ do not satisfy the conditions both input signals in step S414 in step S418 becomes _{M l, s · P 2,} M 2, s, no input signal in step S416 three state M _{2, s} of the input signal of M ₂ in step S420 is stored in the M _2, M _s = _{l, s} · P ₂ + M _{2, s.} In addition, the Reset state M _2, the input signal _r of the M ₂ in step S422 is a M _3, and M _{s 4, s.} Since the input signal in the reset state is only the input state in the next step S424, M _{3, s} and M _{4, s} are stored as it is in accordance with step S426. Step S430 In Step S428 because there is no input signal in the reset state, M _2, of the input signal _r of M ₂ is a M _{2, r} = the input signal from the step S426 M _3, M ₄ + _s, is _s is stored.

Three state M _2, M _{2 s,} and a reset _state, hayeoteumeuro process all of the input signals inside the lower limit detecting sensor by a step S432 the output state of the _r M ₂ is Become the next step by Becomes

3) Upper limit detection sensor (SEN2) Internal output status: M ₃

Set state of the upper limit detection sensor ₃ when M of deployment in accordance with the flow diagram shown the inside of an output state in Fig. 4 M ₃ M ₃ in step _S412, the input signal _s is a M _{2, it s} · P _3. The input signals are three state M _{3, s} input signal of the step S414 condition M at step S418 is not satisfied ₃ a is the same M _{2, s} · P _3, because the input signal in step S416 in step S420 three state M _3, the input signal _s for the M ₃ is stored in the M _3, M _s = _2, P ₃ · _s. In addition, the Reset state M _3, the input signal _r of the M ₃ in step S422 is In the next step S424, since the input signal in the reset state exists together with the input state and the input event, in step S428 Is stored. In step S430 there is no input signal in step S426 the reset state of M ₃ M _3, an input signal of the _r Is stored.

Three state M _3, M _{3 s} and the reset _state, all processing of the input signal _r hayeoteumeuro inside upper limit detection sensor by the output state of the step S432 is M ₃ Become, by step S490 Becomes

4) Counter output status: C _l

If the counter output state C _l is developed in accordance with the flowchart shown in Fig. 4, since the output state is a counter output state in step S440, the input signal of the set state C _{l, s} of the counter becomes M _{3, s} in step S442, and the reset state C The input signal of _{l, r} becomes C _{l, s} · P ₀ . In the next step S444 is stored in C _{l, s} [n] M _{3, s} is storing input status M _{3, s} in step S448 because they do not satisfy the condition, stored in the C _{l, r} [n] C _{l, s} Since P ₀ satisfies the condition, only the input event P ₀ is stored in step S446. In step S450, a logical sum operation is performed on the input signals in steps S446 and S448, where C _{l, s} = M _{3, s} is stored as an input signal in a set state, and C _{l, r} = P as an input signal in a reset state. ₀ is stored respectively. In the next step S490, the counter output state becomes the set state C _{l, s} = M ₃ , and the reset state C _{l, r} = P ₀ .

5) Timer output status: T ₁

If the timer output state T _l is developed in accordance with the flowchart shown in Fig. 4, the output state is a timer output state in step S460. In step S462, the input signal of the timer set state T _{l, s} becomes M _{2, s} , and the reset state T The input signals of _{l and r} are M _{3, s} and M _{4, s} . In the next step S464, M ₂ , stored in T _{l, s} [ n ] and M _{3, s} and M _{4, s} stored in T _{l, r} [ n ] do not satisfy the conditions, so in step S468 T _{l, s} [ n ] = M _{2, s} and T _{l, r} [ n ] = M _{3, s} and M _{4, s} . In step S470, a logical sum operation of the input signals in steps S466 and S468 is performed. The set state T _{l, s} = M _{2, s} of the timer is stored, and the reset state T _{l, r} = M _{3, s} + M _{4 , s} is stored. By the next step S490, the timer output state becomes T _{l, s} = M ₂ and T _{l, r} = M ₃ + M ₄ .

6) Cylinder forward internal output state: M ₄

When the inner cylinder forward output state M ₄ is also expanded along with the flowchart shown in the fourth set of status M _4, M _s of the input signal of ₄ in step S412 is a T _l, and _s · M ₄ P _{5, s.} Three state M _{4, s} input signal of the step S414 M ₄ in step S418 does not satisfy the condition of the T _{l, s} · P, and the ₅ and M _{4, s,} no input signal in step S416 in step S420 three state M _4, the input signal _s of the M ₄ is stored in the M _4, T _l = _{s, s} + ₅ P · M _{4, s.} In addition, the reset state at step S422 M _4, an input signal of _r is the M _{4, s} · P _4. In step S424, P ₄ is stored in step S428 because the input signal in the reset state exists with the input state and the input event. In step S430, since there is no input signal in step S426, the input signal in the reset state is stored with M _{4, r} = P ₄ .

Three state M _4, M _{4 s} and the reset _state, all processing of the input signal _r hayeoteumeuro inner cylinder forward output in step S432 the status of the M ₄ is Becomes The cylinder output internal output state is Becomes

7) Cylinder forward external output state: P ₅₀

P ₅₀ represents the cylinder forward external output status. The external output is an output that actually controls the operation of the external device among the internal outputs. When the internal output is stopped, the external output is automatically stopped. Therefore, it is not necessary to consider the reset state. Therefore, M _{4, s} is stored in P ₅₀ [ n ] in step S480, and P ₅₀ = M _{4, s} in step S482. By the next step S490, the cylinder forward external output state becomes P ₅₀ = M ₄ .

In this way, a ladder diagram can be automatically generated based on the derived blion equation. That is, the logical product of the Brianian equation is connected in series, and the logical sum is connected in parallel (FIG. 3B: S350). In the ladder diagram, the input signal is placed on the left and the output state is placed on the right. Next, step S360 of FIG. 3B is a step of determining the contact point of the input signal. In general, the input signals Y _j and P _j are converted into the a contact point, which is the normally open contact, and the complementary input signal Is converted into contact b, which is a normally closed contact, and finally a ladder diagram is created.

FIG. 7 is a final program of the first embodiment converted from a brian equation derived from a discrete event model into a ladder diagram.

<Second Embodiment>

Figure 8 shows the configuration and operation specifications of the robot arm control system according to a second embodiment of the present invention. The operation sequence of the robot arm control system is described in detail as follows. When attempting to move box X 820 from point A plate 830 to point B plate 840, robotic arm 810 is waiting at the top of point A plate 830 and box X 820 If it is on the point A plate 830, the lowering operation is started and when the chuck 811 reaches the point A plate 830, tighten the chuck 811 (on) to pick up the box 820 (①). When the box 820 is completely picked up, the robot starts to ascend and reaches the top (②) to move the robot arm 810 forward. When the robot arm 810 reaches the top of the B plate (3) and descends and reaches the B point plate 840 (4), the chuck 811 is opened and the box is released. After placing the box on the point B plate 840, start to rise again to reach the top (⑤) to retract the robot arm 810 to return to its original state (⑥). That is, the box is moved from the point A plate 830 to the point B plate 840 through the trajectory of ① → ② → ③ → ④ → ⑤ → ⑥ in FIG. 6.

FIG. 9 is a diagram represented by a discrete event model in consideration of operating characteristics of the system configuration diagram of FIG. 8. Referring to the discrete event model of FIG. 9, the variables for the input contact point and the output state of the discrete event model of FIG. 9 are described in Table 4 to explain the process of converting to the Brianian equation. Referring to Figure 9 and Table 4 will be described in detail the process of deriving the Brianian equation.

Table 4. Variable definitions for the input contacts and output states of the second embodiment.

1) Starting internal output status: M _l

When deployed in accordance with the flow chart of the start-up inside the output state M _l to 4 in step S412 M _{l, s} [n], the set state of M _l M _{l, s} input signal of _{P l · M l, r,} M l, s Is stored. In the next step S414, since the input state M _{1, r} in the reset state exists, M _{l, r} becomes 1 in step S416, where M _{l, s} [ n ] = P _l . Also be a _{M l, s [n] =} M l, s saved in step S418, sets the state of the M _l In step S420 M _{l, s} input signal of the M _{l, s} = P _l + M _l, is the _s . Next, the reset condition M _{l, r} of the input signal to the M _l in step S422 is the M _{l, s} · P _0. Since the next step S424, the input signal on the reset state input events and the input state of the logical product from step S428 M _{l, s} is created in the first storage only P ₀ and resets the M _l In step S430 state M _{l, r} input of The signal is M _{l, r} = P ₀ .

M _l M _l set _state, a reset state and M _{s l,} process all of the input signals _r hayeoteumeuro internal start by step S432 of the output states is Becomes In the next step S490, the input state M _{l, s} is converted into M _l . Becomes

2) Internal state of cylinder lowering at point A: M ₂

Three state M _2, the input signal of the _s M ₂ at step S412 when deployed in accordance with the flow diagram of the falling cylinder internal output state M ₂ to Figure 4 at point A is Becomes In step S414 M _{2, s} of the input signal is set state of M ₂ in step S418 does not satisfy the condition M _{2, s} input signal of the _{M l, s · P 2 ·} P 4 · P 7 and M _{2, s} that is, three states of M ₂ in the no input signal in step S416 step S420 M _{2, s} input signals is _{M 2, s = M l,} s · P 2 · P 4 · P 7 + M 2, s Becomes In addition, the Reset state M _2, the input signal _r of the M ₂ in step S422 is a M _{3, s.} Because only the input state of the input signal of the reset state by a next step S424 is present in step S426 M _{3, s} is stored, step S430 in the no input signal is the reset state of M ₂ at step S428 M _{2, r} input of The signal is M _{2, r} = M _{3, s} .

Three state M _2, M _{2 s,} and a reset _state, all processing of the input signal _r hayeoteumeuro cylinder lowered by the step S432 internal output state of M ₂ is And become the next step by S490 Becomes

3) Chuck fastening Internal output state: M ₃

The set state of the chuck clamping the internal output state M ₃ to M in step S412 when deployed in accordance with the flow chart of Fig. 4 ₃ M _{3, s} is the input signal of _{M 2, s · P 3,} M 3, s. In step S414 M _{3, s} input signal is a M ₃ set in step S418 does not satisfy the condition of status M _{3, s} input signals is to be M _{2, s} · P ₃ and M _{3, s,} at step S416 of the input signal is not set state M _3, M ₃ of the input signal _s in step S420 is saved, M _3, M = _{s 2, s 3} · P + M _{3, s.} In addition, the Reset state M _3, the input signal _r of the M ₃ in step S422 is the M _{7, s.} In the next step S424, since the input signal in the reset state is only the input state, M _{7, s} is stored in step S426. In step S430 there is no input signal in step S428 the reset state M _3, the input signal _r of the M ₃ is a M _3, M _r = _{7, s.}

Three state M _3, M _{3 s} and the reset _state, all processing of the input signal _r hayeoteumeuro chuck tightening by step S432 internal output state of M ₃ is Become, and by the next step S490 Becomes

4) Cylinder output at point A internal output state: M ₄

Cylinder rises set state of the internal output state when deployed in accordance with the flow diagram of the M ₄ Figure 4 M in step S412 ₄ M _{4, s} input signals at the point A is a _{M 3, s · P 6,} M 4, s . In step S414 M _4, the three states M _{4, s} input signals in the input signal of the _s does not satisfy the condition step S418 M ₄ is a M _{3, s} · P ₆ and M _{4, s,} at step S416 of the input signal is not set state M _4, the input signal _s of M ₄ in step S420 is the M _4, M _s = _{3, s} + ₆ · P M _{4, s.} In step S422, the input signals of the reset states M _{4 and r} become M _{5 and s} . Since the input signal in the reset state exists only in the input state by the next step S424, M _{5, s} is stored in the step S426. In step S430, since there is no input signal in step S428, M _{5, s} is stored.

Three state M _4, M _s and the reset state _4, finish processing the input signal to the _r hayeoteumeuro cylinder increases by a step S432 outputs an internal state of M ₄ is And become the next step by S490

Becomes

5) Cylinder forward internal output state: M ₅

When the inner cylinder forward output state M ₅ deployed in accordance with the flowchart shown in Table 4 set conditions M _{5, s} of the input signal of M ₅ in step S412 is the _{M 4, s · P 4,} M 5, s. In step S414 M _{5, s} of the input signal does not satisfy the condition of M ₅ set in step S418 the status M _{5, s} input signals are the M _{4, it s} · P ₄ and M _{5, s,} at step S416 of the input signal is not set conditions M _{5, s} of the input signal of M in step S420 is a _{5 M 5, s = M 4,} s · P 4 + M 5, s. In step S422, the input signals of the reset states M _{5 and r} become M _{6 and s} . M is _{6, s} is stored in step S426, because the input signal of the reset state by a next step S424 there is only input. In step S430, since there is no input signal in step S428, the input signals of the reset states M _{5 and r} become M _{5, r} = M _{6, s} .

Set state of M ₅ M _5, M _s, and a reset state _5, all of the processing of the input signal _r hayeoteumeuro cylinder forward by a step S432 an internal output state Become the next step by Becomes

6) Lowering cylinder output at point B: M ₆

When deployed the cylinder falling inside the output state M ₆ at the point B in accordance with the flowchart shown in Table 4 set state M _{6, s} input signal of the M ₆ in step S412 are the M _{5, s} · P ₅ and M _{6, s} . Since the input signals of M _{6 and s} in step S414 do not satisfy the conditions, the input signals of M _{6 and s} in step S418 are M _{5, s} · P ₅ and M _{6 and s as they} are, and the input signal in step S416 is Since three states M _6, the input signal _s of the M ₆ in step S420 are the M _6, M _s = _5, P _s · ₅ + M _{6, s.} In step S422, the input signals of the reset states M _{6 and r} become M _{7, s} . In the next step S424, M _{7, s} is stored in step S426 because only the input state of the reset state exists in the input state. In step S430 there is no input signal in step S428 the reset condition M _6, the input signal of the M _{6 r} is the M _6, M _r = _{7, s.}

M ₆ set state M _6, M _{6 s,} and a reset _state, all of the processing to the input signal _r hayeoteumeuro cylinder lowered by the step S432 is a state of the internal output Become the next step by Becomes

7) Internal output state of chuck open: M ₇

When the chuck opening deployed in accordance with the flow diagram of the internal output state 4 the M ₇ M ₇ set _state, the input signal of the _s M ₇ in step S412 is the _{M 6, s · P 3,} M 7, s. In step S414 M _7, the input signal of the _s does not satisfy the condition step S418 M _{7, s} input signals are the _{M 6, s · P 3,} M 7, s, no input signal in step S416 three state M _7, the input signal of the _s M ₇ in step S420 is the M _7, M = _{s 6, s 3} · P + M _{7, s.} In step S422, the input signals of the reset states M _{7, r} become M _{8, s} . Since the input signal in the reset state exists only in the input state by the next step S424, M _{8, s} is stored in the step S426. In step S430 there is no input signal in step S428 of the reset state M ₇ M _7, the input signal _r is stored in the M _7, M ₈ = _{r, s.}

M three state M _7, M _{7 s} and the reset _state, all processing of the input signal _r hayeoteumeuro chuck opened by a step S432 an internal state of outputs ₇ Become, and by the next step S490 Becomes

8) Internal output of cylinder rising at point B: M ₈

When the cylinders rise in the output point B inside state M ₈ also developed in accordance with the flow diagram of the 4 M ₈ set in step S412 the status M _8, the input signal of the _s Becomes In step S414, the input signals of M _{8 and s} do not satisfy the condition, so in step S418 the input signals of M _{8 and s} are That is, three states in step S416 M ₈ from the input signal in step S420 because of M _{8, s} is the input signal Becomes In step S422, the input signals of the reset states M _{8 and r} become M _{9 and s} . Since the input signal in the reset state exists only in the input state by the next step S424, M _{9 and s} are stored in the step S426. In step S430 there is no input signal in step S428 the reset condition M _8, the input signal of the M _{8 r} is the M _8, M _r = _{9, s.}

Three state M _8, M _{8 s} and the reset _state, all processing of the input signal _r hayeoteumeuro cylinder increases by a step S432 outputs an internal state of M ₈ is Become, and by the next step S490 Becomes

9) Cylinder reverse internal output state: M ₉

Reversing cylinder set state of the internal output state M M ₉ in the step S412 when deployed according to a flow chart of the Figure 4 _{9 9 M, s} of the input signal is a _{M 8, s · P 2,} M 9, s. In step S414 M _9, the input signal of the _s does not satisfy the condition step S418 M _{9, s} input signal of the M _{8, s} · P _2, and the M _{9, s,} no input signal in step S416 three state M _9, M ₉ of the input signal _s at the step S420 is the _{M 9, s = M 8,} s · P 2 + M 9, s. In step S422, the input signals of the reset states M _{9 and r} become M _{9, s} · P ₄ . In the next step S424, P ₄ is stored in step S428 because the reset signal has the input state and the input event. In step S430 there is no input signal in step S426 of the M _{9 9} M reset _state, the input signals _r is the M _{9, r} = P _4.

Three state M _9, M _{9 s} and the reset _state, all processing of the input signal _r hayeoteumeuro step S432 cylinder backward by the internal state of the output is M ₉ Become the next step by Becomes

10) Counter output status: C _l

If the counter output state C _l is developed in accordance with the flowchart of Fig. 4, the output state is a counter output state in step S440. In step S442, the input signal of the set state C _{l, s} of the counter becomes M _l, sP ₇ , and is reset. The input signal of the states C _{l, r} is C _{l, s} · P ₀ . In the next step S444 is stored in _{C l, s [n] M} l, s , so satisfying the condition storing input state P ₇ in step S446, _{and, C l, r [n]} C l, s · P 0 stored in doubt Since the condition is satisfied, only the input event P ₀ is stored in step S446. In step S450, a logical sum operation is performed on the input signals in steps S446 and S448, where C _{l, s} = P ₇ is stored, and C _{l, r} = P ₀ is stored. By the next step S490, the counter output state becomes C _{l, s} = P ₇ , and C _{l, r} = P ₀ .

11) Cylinder down external output state: P ₅₁

P ₅₁ represents the cylinder down external output state. The external output is an output that actually controls the operation of the external device among the internal outputs. When the internal output is stopped, the external output is automatically stopped. Therefore, it is not necessary to consider the reset state. Therefore, M _{2, s} , M _{6, and s} are stored in P ₅₁ [ n ] in step S480, and P ₅₁ = M _{2, s} + M _{6, s} in step S482. By the next step S490, the cylinder lower external output state becomes P ₅₁ = M ₂ + M ₆ .

12) Chuck tightening External output state: P ₅₂

P ₅₂ represents the chucking external output state. M _{3, s} is stored in P ₅₂ [ n ] in step S480, and P ₅₂ = M _{3, s} in step S482. In step S490, the chucking external output state becomes P ₅₂ = M ₃ .

13) External state of cylinder forward: P ₅₃

P ₅₃ represents the cylinder forward external output status. M _{5, s} is stored in P ₅₃ [ n ] in step S480, and P ₅₃ = M _{5, s} in step S482. By the next step S490, the final cylinder forward external output state is P ₅₃ = M ₅ .

14) Cylinder lift external output state: P ₅₄

P ₅₄ represents the cylinder lift external output state. M _{4, s} , M _{8, s} are stored in P ₅₄ [ n ] in step S480, and P ₅₄ = M _{4, s} + M _{8, s} in step S482. By the next step S490, the cylinder lift external output state becomes P ₅₄ = M ₄ + M ₈ .

15) External state of cylinder reverse: P ₅₅

P ₅₅ represents the cylinder reverse external output state. In step S480, M _{9, s} is stored in P ₅₅ [ n ], and in step S482, P ₅₅ = M _{9, s} . By the next step S490, the cylinder forward external output state becomes P ₅₅ = M ₉ .

In this way, a ladder diagram can be automatically generated based on the derived blion equation. That is, the logical product of the Brianian equation is connected in series, and the logical sum is connected in parallel (FIG. 3B: S350). In the ladder diagram, the input signal is placed on the left and the output state is placed on the right. Next, step S360 of FIG. 3B is a step of determining the contact point of the input signal. In general, the input signals Y _j and P _j are converted into the a contact point, which is the normally open contact, and the complementary input signal Is converted into contact b, which is a normally closed contact, and finally a ladder diagram is created.

FIG. 10 is the final program of the second embodiment transformed from a Brianon equation derived from a discrete event model into a ladder diagram.

As seen through the above embodiment, the present invention generates a ladder diagram through the conversion process automatically through the method of the present invention when the designer creates a control algorithm in the form of a discrete event model. As a result of testing the automatically generated ladder diagram using the system shown in FIG. 1, it was confirmed that the designer faithfully fulfills the desired control objectives. The programmable logic controller used at this time is Master-K 1000S PLC.

The present invention has been described in detail with reference to preferred embodiments, but the scope of the present invention is not limited thereto, and should be interpreted by the following claims. In addition, it will be understood by those skilled in the art that various modifications or changes may be made without departing from the spirit of the present invention.

As described so far, the automatic generation of ladder diagram for the design of the programmable logic controller based on the discrete event model makes it easy to implement the control algorithm by user interaction with the computer using the discrete event model. And because the ladder diagram is designed for each module, it is easy to partially modify and change the ladder diagram due to the system change, so that the flexibility is increased, and when the error occurs in the programmable logic controller, the error can be easily detected and the cause of the error can be identified. Easy to modify In addition, the present invention automatically converts a control algorithm written in the form of a discrete event model into a ladder diagram so that a user does not need to know or understand the actual code, so that even an unskilled user can easily write a control algorithm. Furthermore, according to the present invention, the event and state can be defined using the discrete event model, so that the execution operation can be grasped at a glance, and there is no need to set input / output contacts separately.

Claims (12)

A method for automatically generating a ladder diagram for a programmable logic controller using a computer, A state diagram generation step of defining each state and operation characteristics including an internal output state, a timer output state, a counter output state, and an external output state of the program logic controller and generating a state diagram according thereto; An input step of providing the generated state diagram as an input of the computer, Processing an input signal for a corresponding output state for each output state of the input state diagram; Processing whether to include an input state after processing the input signal; Rearranging the input signals of each state after the input signal processing and the processing of whether the input state is included; Converting the rearranged input signals into set input states and reset input states of each input signal into input states without distinction between set states and reset states, and converting them into a brian equation; Generating the transformed brian equations into a ladder diagram through a ladder diagram generation algorithm, and An output step of outputting the generated ladder diagram A method for automatically generating ladder diagrams for a programmable logic controller configured with a. delete The method of claim 1, Each state and operation characteristic defined for the state diagram generation in the state diagram generation step, The internal output state, timer output state and counter output state of the program logic controller are divided into a set state for operation and a reset state for stop, respectively. The input signal is defined as the logical product of the input state and the input event, If you want to keep the current state after the event is entered, it will be displayed to transition to your own state. A method of automatically generating a ladder diagram for a programmable logic controller, characterized in that the simultaneous state is displayed so that a transition occurs to the next state without occurrence of an event. delete The method of claim 1, In the input signal processing step, the set state and the reset state are divided for each state to store an input signal for each state, Processing whether or not to include the state of the previous step, If the state is set internal output state, if the input signal has the set input state and the input event, the logical product of the input state and the input event is stored again. If the input signal has the reset input state and the input event, only the input event is restored. Save it, If the state is reset internal output state, if the input signal has both input state and input event, only the input event is saved again. If only the input state has input state, the input state is saved again. If the state is counter output or timer output, if the input signal has both input state and input event for each set state and reset state, only the input event is saved again. If only the input state has only input state, the input state is saved again. If the state is external output state, input signal is saved. Rearranging the input signal of each state, If the state is the internal output state, logical operation is performed on the stored input state and event for each of the set internal output state and the reset internal output state, and then the logical form of the complement type and the set internal output state of the reset internal output state is calculated. If the state is counter output state or timer output state, the input and events stored for each set state and reset state are ORed. A method of automatically generating a ladder diagram for a programmable logic controller, wherein when the state is an external output state, the stored input state and the event are ORed. The method of claim 1, In the input step of providing the generated state diagram as an input of a computer, Automatic ladder diagram for the programmable logic controller which extracts each state and event of the state diagram into a table form including an input state and an input event and an output state according to the input state and the input event. How to produce. The method of claim 1, Converting the Brianian equation into a ladder diagram, Converting the logical product into a series connection and the logical sum into a parallel connection in the Brianian equation; In the Brian equation, a typical input signal includes a normal open contact, and a complementary input signal is converted into a normally closed contact. A method for automatically generating ladder diagrams for a programmable logic controller that generates ladder diagrams with input signals to the left and output states to the right. delete delete An apparatus capable of automatically generating a ladder diagram for a programmable logic controller based on a discrete event model, Input means for receiving a predetermined input modeled for each operation characteristic of the programmable logic controller from the outside, A storage device in which a predetermined control program is stored, and The discrete event model, which is connected to the input means and the memory device and expresses an operating characteristic of the programmable logic controller from the outside, is input to the ladder event model by a predetermined control program stored in the memory device. Includes a processing unit for converting, The processing apparatus converts the discrete event model inputted from the input means into a brian equation representing each state or event, and converts the converted brian equation into a ladder diagram. Automatic generation device. delete delete