KR100390897B1 - Method for manufacturing chip size package - Google Patents

Method for manufacturing chip size package Download PDF

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Publication number
KR100390897B1
KR100390897B1 KR1019970076779A KR19970076779A KR100390897B1 KR 100390897 B1 KR100390897 B1 KR 100390897B1 KR 1019970076779 A KR1019970076779 A KR 1019970076779A KR 19970076779 A KR19970076779 A KR 19970076779A KR 100390897 B1 KR100390897 B1 KR 100390897B1
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South Korea
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semiconductor chips
wafer
sawing
coating solution
attached
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KR1019970076779A
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Korean (ko)
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KR19990056768A (en
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김재면
박성범
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A method for manufacturing a CSP(Chip Size Package) is provided to be capable of simplifying the manufacturing process. CONSTITUTION: Solder bumps(12) are formed on semiconductor chips(10). The first sawing is performed on a back side of a wafer(50) according to a scribe line. A heat slug is attached to the back side of the wafer. The first coating solution(50a) fills space between the semiconductor chips. The second sawing is performed from the front side of the wafer to the region filled with the first coating solution. Tap tapes(60) with circuit patterns are attached on the semiconductor chips. The second coating solution(50b) fills space between the semiconductor chips. Solder balls(70) is attached on the tap tapes. Then, the semiconductor chips are isolated to unit chip.

Description

칩 크기 패키지의 제조방법Manufacturing method of chip size package

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는, 제조공정의 단순화를 얻을 수 있는 칩 크기 패키지의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a method of manufacturing a chip size package that can simplify the manufacturing process.

최근, 각종 전기·전자 제품의 크기가 소형화되는 추세에 따라 한정된 크기의 기판에 보다 많은 수의 칩을 실장하여 소형이면서도 고용량을 달성하고자 하는 많은 연구가 전개되고 있으며, 이에 따라, 반도체 패키지의 크기 및 두께가 점차 감소되고 있다.Recently, as the size of various electric and electronic products is miniaturized, many studies have been conducted to achieve a small size and high capacity by mounting a larger number of chips on a limited sized substrate. The thickness is gradually decreasing.

한편, 공지된 반도체 소자의 제조 공정을 통해 얻어진 반도체 칩들은 칩 절단, 칩 부착, 와이어 본딩, 몰딩 및 트림/포밍 등 일련의 어셈블리(Assembly) 공정을 거쳐 패키지화되며, 이러한 반도체 패키지는 반도체 칩이 전기적 신호 전달 경로를 이루는 리드 프레임의 인너리드와 전기적으로 접속되고, 상기 반도체 칩 및 인너리드를 포함하는 공간적 영역이 에폭시 수지에 의해 봉지된 형태를 이루고 있다.Meanwhile, semiconductor chips obtained through the manufacturing process of known semiconductor devices are packaged through a series of assembly processes such as chip cutting, chip attachment, wire bonding, molding, and trim / forming. The spatial region including the semiconductor chip and the inner lead, which is electrically connected to the inner lead of the lead frame constituting the signal transmission path, is sealed by an epoxy resin.

그런데, 상기한 반도체 패키지는 그 크기를 감소시키는데 한계가 있기 때문에, 최근에는 별도의 제조공정을 통해 칩 크기 패키지(Chip Size Package : 이하, CSP)를 제조하고 있다.However, since the semiconductor package has a limitation in reducing its size, recently, a chip size package (hereinafter referred to as CSP) is manufactured through a separate manufacturing process.

이러한 CSP의 제조방법을 도 1 을 참조하여 설명하면 다음과 같다.The manufacturing method of such a CSP is described with reference to FIG. 1 as follows.

우선, 웨이퍼 상태에서 각 반도체 칩(1)의 본딩패드들(도시안됨) 상에 솔더 범프(2)를 형성하고, 이러한 반도체 칩들(1)을 개별 반도체 칩으로 소잉(Sawing)한다. 그런 다음, 상기한 반도체 칩(1) 상에 회로패턴이 구비된 탭 테이프(3)를 부착시키고, 이어서, 반도체 칩(1)의 하부면 및 탭 테이프의 하부면을 덮지 않는 범위에서 코팅 용액(4)으로 봉지한 후, 마지막으로, 탭 테이프(4)의 하부면에 외부 회로와의 전기적 접속을 위한 솔더 볼들(5)을 부착시킨다.First, solder bumps 2 are formed on the bonding pads (not shown) of each semiconductor chip 1 in the wafer state, and the semiconductor chips 1 are sawed into individual semiconductor chips. Then, the tab tape 3 provided with the circuit pattern is attached to the semiconductor chip 1, and then the coating solution (without covering the lower surface of the semiconductor chip 1 and the lower surface of the tab tape) After encapsulation with 4), finally, solder balls 5 for electrical connection with an external circuit are attached to the lower surface of the tab tape 4.

상기한 제조공정을 통해 제조된 CSP는 통상의 반도체 패키지, 즉, 반도체 칩을 에폭시 수지로 몰딩하여 구성하는 패키지에 비하여 그 두께 및 크기를 감소시킬 수 있으며, 이에 따라, 패키지의 경·박·단·소화를 달성할 수 있다.The CSP manufactured through the above-described manufacturing process can reduce the thickness and size of a conventional semiconductor package, that is, a package formed by molding a semiconductor chip with an epoxy resin. Digestion can be achieved.

또한, CSP는 솔더 볼을 이용하여 외부 회로와의 전기적 접속을 이루기 때문에 비교적 짧은 접속 경로를 제공함으로써, 패키지의 전기적 특성을 향상시킬 수 있다.In addition, since the CSP makes an electrical connection with an external circuit using solder balls, the electrical characteristics of the package can be improved by providing a relatively short connection path.

그러나, 상기와 같은 종래의 CSP 제조방법은 반도체 칩들을 개별적으로 각각 패키징하기 때문에 신뢰성에 문제가 있을 뿐만 아니라, 반도체 칩들을 개별적으로 이동시키는 운반 수단이 필요하기 때문에 전체적인 공정이 번거롭다는 문제점이 있었다.However, the conventional CSP manufacturing method as described above not only has a problem in reliability because the semiconductor chips are individually packaged, but also has a problem that the whole process is cumbersome because a transport means for moving the semiconductor chips is required. .

또한, 최근에 GaAs 재료의 반도체 칩이 개발되면서 이러한 GaAs 반도체 칩을 패키징할 경우에는, 상기 GaAs 반도체 칩이 일반적인 반도체 칩의 두께 보다 더 얇기 때문에 개별 반도체 칩들로 분리시키기 위한 소잉 공정시에 웨이퍼의 후면에서 크랙이 발생하여 제조수율이 저하되는 문제점이 있었다.In addition, in the case of packaging such GaAs semiconductor chips with the development of GaAs semiconductor chips in recent years, since the GaAs semiconductor chips are thinner than the thickness of a general semiconductor chip, the back side of the wafer during the sawing process for separating into individual semiconductor chips There was a problem that the production yield is lowered due to cracks.

게다가, 반도체 칩이 고집적화됨에 따라 전력 소모가 증가됨으로써, 열방출이 용이하지 않아 크랙이 발생하는 등의 패키지의 신뢰성이 저하되는 문제점이 있었다.In addition, as the semiconductor chip is highly integrated, power consumption increases, so that heat dissipation is not easy and there is a problem in that the reliability of the package such as cracking is lowered.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 웨이퍼 상태로 CSP 제조공정을 진행함으로써, 제조공정의 단순화 및 신뢰성을 향상시킬 수 있고, 아울러, 반도체 칩의 후면에서 크랙이 발생되는 것을 방지할 수 있는 CSP의 제조방법을 제공하는데, 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, by proceeding the CSP manufacturing process in the wafer state, it is possible to improve the simplification and reliability of the manufacturing process, and cracks are generated on the back surface of the semiconductor chip It is an object of the present invention to provide a method for manufacturing a CSP, which can be prevented.

도 1 은 종래의 칩 크기 패키지의 제조방법을 설명하기 위한 도면.1 is a view for explaining a method of manufacturing a conventional chip size package.

도 2a 내지 도 2e 는 본 발명의 실시예에 따른 칩 크기 패키지의 제조방법을 설명하기 위한 일련의 공정 단면도.2A through 2E are a series of cross-sectional views illustrating a method of manufacturing a chip size package according to an embodiment of the present invention.

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

10 : 반도체 칩 12 : 솔더 범프10 semiconductor chip 12 solder bump

20 : 접착 테이프 30 : 접착제20: adhesive tape 30: adhesive

40 : 히트 슬러그 50a : 1차 코팅 용액40: heat slug 50a: primary coating solution

50b : 2차 코팅 용액 60 : 탭 테이프50b: secondary coating solution 60: tab tape

70 : 솔더 볼70: solder ball

상기한 목적을 달성하기 위한 본 발명의 CSP의 제조방법은, 웨이퍼 상태에서 각 반도체 칩들의 본딩패드들 상에 솔더 범프를 형성하는 단계; 상기 웨이퍼의 후면을 그의 스크라이브 라인을 따라 소정 깊이만큼 1차로 소잉하는 단계; 상기 1차 소잉된 각 반도체 칩들의 후면에 히트 슬러그를 부착시키는 단계; 상기 히트 슬러그가 부착된 반도체 칩들 사이의 공간에 1차 코팅 용액을 충진시키는 단계; 상기 웨이퍼의 상부면으로부터 상기 1차 코팅 용액이 충진되어 있는 부분까지를 2차 소잉하는 단계; 상기 솔더 범프가 형성된 각각의 반도체 칩들 상에 회로패턴이 구비된 탭 테이프를 부착시키는 단계; 상기 탭 테이프가 부착된 반도체 칩들 사이의 공간에 2차 코팅 용액을 충진시키는 단계; 상기 탭 테이프 상에 솔더 볼들을 부착시키는 단계; 및 상기 1차 및 2차 코팅 용액에 의해 봉지된 반도체 칩들을 분리시키는 단계를 포함하는 것을 특징으로 한다.The CSP manufacturing method of the present invention for achieving the above object comprises the steps of forming a solder bump on the bonding pads of each semiconductor chip in the wafer state; Primary sawing the back surface of the wafer along a scribe line thereof by a predetermined depth; Attaching a heat slug to the back surface of each of the first sawed semiconductor chips; Filling a primary coating solution into a space between the semiconductor chips to which the heat slug is attached; Secondary sawing from an upper surface of the wafer to a portion where the primary coating solution is filled; Attaching a tab tape having a circuit pattern on each of the semiconductor chips having the solder bumps formed thereon; Filling a secondary coating solution into a space between the semiconductor chips to which the tab tape is attached; Attaching solder balls to the tab tape; And separating the semiconductor chips encapsulated by the first and second coating solutions.

본 발명에 따르면, 웨이퍼 상태로 CSP들을 제조하기 때문에 공정의 단순화를 얻을 수 있으며, 아울러, 반도체 칩을 봉지하기 위한 코팅 공정을 2회에 걸쳐 실시함으로써, 반도체 칩의 후면에서 크랙이 발생되는 것을 방지할 수 있다.According to the present invention, since the CSPs are manufactured in a wafer state, the process can be simplified, and the coating process for encapsulating the semiconductor chip is performed twice, thereby preventing cracks from occurring on the rear surface of the semiconductor chip. can do.

이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e 는 본 발명의 실시예에 따른 CSP의 제조방법을 설명하기 위한 일련의 공정 단면도로서, 이를 설명하면 다음과 같다.2A to 2E are a series of cross-sectional views for explaining a method for manufacturing a CSP according to an embodiment of the present invention.

도 2a 를 참조하면, 웨이퍼(50) 상태에서 각 반도체 칩들(10)의 본딩패드들(도시안됨) 상에 범핑 공정을 통하여 솔더 범프(12)를 형성한다. 그런 다음, 소잉 공정시에 웨이퍼가 유동되는 것을 방지하기 위하여 접착 테이프(20) 상에 솔더 범프들(12)이 형성되어져 있는 웨이퍼(50)의 상부면을 부착·고정시킨다.Referring to FIG. 2A, solder bumps 12 are formed on the bonding pads (not shown) of the semiconductor chips 10 through a bumping process in a wafer 50 state. Then, in order to prevent the wafer from flowing during the sawing process, the upper surface of the wafer 50 on which the solder bumps 12 are formed on the adhesive tape 20 is attached and fixed.

도 2b 를 참조하면, 스크라이브 라인(도시안됨)을 따라 웨이퍼(50)의 후면을 소정 깊이만큼 1차로 소잉한다. 여기서, 1차 소잉 공정은 웨이퍼의 후면에서 크랙이 발생되는 것을 방지하기 위함이며, 대략 웨이퍼 전체 두께에 대하여 50% 미만의 두께를 소잉한다.Referring to FIG. 2B, the backside of the wafer 50 is first sawed along a scribe line (not shown) by a predetermined depth. Here, the primary sawing process is to prevent cracks from occurring on the back side of the wafer, and sawing thickness of less than 50% of the overall thickness of the wafer.

도 2c 를 참조하면, 1차 소잉시에 웨이퍼의 유동을 방지하기 위하여 상기 웨이퍼의 상부면에 부착시킨 접착 테이프를 제거한 상태에서, 각 반도체 칩들(10)의 후면에 접착제(30)를 개재시켜 패키지의 열방출 능력을 향상시키기 위한 히트 슬러그(Heat Slug : 40)를 부착시킨다. 이때, 히트 슬러그(40)는 반도체 칩(10)의 후면은 물론 측면 일부분을 감쌀 수 있는 크기로 구비시키며, 반도체 칩(10)의 측면에 위치되는 히트 슬러그 부분은 상기 반도체 칩과 소정 간격 이격되도록 한다.Referring to FIG. 2C, the adhesive tape attached to the upper surface of the wafer is removed to prevent the flow of the wafer during the first sawing, and the package is formed by interposing the adhesive 30 on the rear surface of each semiconductor chip 10. Heat Slug (40) is attached to improve the heat dissipation ability of the. In this case, the heat slug 40 is provided to cover the rear surface of the semiconductor chip 10 as well as the size of the side portion, and the heat slug portion positioned on the side surface of the semiconductor chip 10 is spaced apart from the semiconductor chip by a predetermined distance. do.

그런 다음, 웨이퍼 상태로된 반도체 칩들을 개개의 반도체 칩으로 분리시키기 위한 소잉시에 톱날, 즉, 브레이드(Blade)와 웨이퍼간의 마찰에 기인된 웨이퍼의 유동으로 인하여 반도체 칩의 후면에서 크랙이 발생되는 것을 방지하기 위하여 히트 슬러그(40)가 부착된 반도체 칩들(10) 사이의 공간에 1차 코팅 용액(50a)을 충진시킨다. 이때, 반도체 칩(10)과 그의 측면에 위치된 히트 슬러그(40) 부분 사이에도 1차 코팅 용액(50a)이 충진되도록 함으로써, 반도체 칩의 유동을 방지함은 물론 상기 반도체 칩의 가장자리 부분에서 코팅 용액과의 박리 현상을 방지한다.Then, during sawing to separate the semiconductor chips in the wafer state into individual semiconductor chips, cracks are generated at the rear surface of the semiconductor chip due to the flow of the wafer due to the saw blade, ie, the friction between the blade and the wafer. In order to prevent the filling, the primary coating solution 50a is filled in the space between the semiconductor chips 10 to which the heat slug 40 is attached. At this time, the primary coating solution 50a is also filled between the semiconductor chip 10 and the heat slug 40 located on the side thereof, thereby preventing the flow of the semiconductor chip and coating the edge at the edge of the semiconductor chip. Prevents peeling phenomenon with the solution.

도 2d 를 참조하면, 1차 소잉시에 소잉되지 않은 반도체 칩들(10) 사이 부분을 2차 소잉하여 개별 반도체 칩들(10)로 분리시킨다. 이때, 각각의 반도체 칩들(10)은 개별 반도체 칩들로 분리는 되지만, 이전 공정에서 반도체 칩들(10) 사이의 공간에 1차 코팅 용액(50a)을 충진시켰고, 아울러, 1차 코팅 용액(50a)이 충진된 부분은 소잉하지 않기 때문에 다수의 반도체 칩들(10)은 유니트(Unit) 상태로 분리되지 않고, 스트립(Strip) 상태로 있게 된다.Referring to FIG. 2D, portions between the semiconductor chips 10 that are not sawed upon primary sawing are second sawed to separate the individual semiconductor chips 10. At this time, each of the semiconductor chips 10 are separated into individual semiconductor chips, but the primary coating solution 50a is filled in the space between the semiconductor chips 10 in the previous process, and the primary coating solution 50a Since the filled portion is not sawed, the plurality of semiconductor chips 10 are not separated into a unit state, but are in a strip state.

그런 다음, 솔더 범프들(12)이 형성되어 있는 각 반도체 칩들(10)의 상부면에 회로패턴이 구비된 탭 테이프(60)를 상기 솔더 범프(12)를 이용하여 각각 부착시킨 후, 탭 테이프(60)가 부착된 반도체 칩들(10) 사이의 공간에 2차 코팅 용액(50b)을 충진시킨다. 이때, 2차 코팅 용액(50b)은 상기 탭 테이프(60)의 하부면, 즉, 솔더 범프와 부착되지 않은 면을 덮지 않는 한도에서 충진시킨다.Then, the tab tape 60 having the circuit pattern is attached to the upper surfaces of the semiconductor chips 10 on which the solder bumps 12 are formed, respectively, using the solder bumps 12, and then the tab tapes. The secondary coating solution 50b is filled in the space between the semiconductor chips 10 to which the 60 is attached. At this time, the secondary coating solution 50b is filled to the extent that it does not cover the lower surface of the tab tape 60, that is, the surface not attached to the solder bumps.

이어서, 각 탭 테이프(60) 상에 외부 회로와의 전기적 접속을 위한 솔더 볼들(70)을 부착시킨다.Subsequently, solder balls 70 are attached to each tab tape 60 for electrical connection with an external circuit.

도 2e 를 참조하면, 상기한 공정을 통해 제조된 다수개의 CSP들을 사이에 충진되어져 있는 1차 및 2차 코팅 용액(50a, 50b)의 중심부를 소잉하여 각각의 CSP로 분리시킨다. 이때, 소잉 공정은 히트 슬러그(40)의 측면을 따라 소잉한다.Referring to FIG. 2E, a plurality of CSPs prepared through the above process are sawed and separated into respective CSPs by sawing the center portions of the primary and secondary coating solutions 50a and 50b which are filled therebetween. At this time, the sawing process saws along the side surface of the heat slug 40.

이상에서와 같이, 본 발명의 CSP의 제조방법은 웨이퍼 상태로 CSP들을 제조하기 때문에 공정의 단순화를 얻을 수 있으며, 아울러, 반도체 칩을 봉지하기 위한 코팅 공정을 2회에 걸쳐 실시함으로써, 반도체 칩의 후면에서 크랙이 발생되는 것을 방지할 수 있다. 또한, 반도체 칩의 후면에 히트 슬러그를 부착시킴으로써, 패키지의 열방출 능력을 향상시킬 수 있다.As described above, the manufacturing method of the CSP of the present invention can simplify the process because the CSPs are manufactured in a wafer state, and the coating process for encapsulating the semiconductor chip is carried out twice, so that Cracks can be prevented from occurring at the rear side. In addition, by attaching heat slug to the rear surface of the semiconductor chip, the heat dissipation ability of the package can be improved.

한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (6)

웨이퍼 상태에서 각 반도체 칩들의 본딩패드들 상에 솔더 범프를 형성하는 단계;Forming solder bumps on the bonding pads of the respective semiconductor chips in the wafer state; 상기 웨이퍼의 후면을 그의 스크라이브 라인을 따라 소정 깊이만큼 1차로 소잉하는 단계;Primary sawing the back surface of the wafer along a scribe line thereof by a predetermined depth; 상기 1차 소잉된 각 반도체 칩들의 후면에 히트 슬러그를 부착시키는 단계;Attaching a heat slug to the back surface of each of the first sawed semiconductor chips; 상기 히트 슬러그가 부착된 반도체 칩들 사이의 공간에 1차 코팅 용액을 충진시키는 단계;Filling a primary coating solution into a space between the semiconductor chips to which the heat slug is attached; 상기 웨이퍼의 상부면으로부터 상기 1차 코팅 용액이 충진되어 있는 부분까지를 2차 소잉하는 단계;Secondary sawing from an upper surface of the wafer to a portion where the primary coating solution is filled; 상기 솔더 범프가 형성된 각각의 반도체 칩들 상에 회로패턴이 구비된 탭 테이프를 부착시키는 단계;Attaching a tab tape having a circuit pattern on each of the semiconductor chips having the solder bumps formed thereon; 상기 탭 테이프가 부착된 반도체 칩들 사이의 공간에 2차 코팅 용액을 충진시키는 단계;Filling a secondary coating solution into a space between the semiconductor chips to which the tab tape is attached; 상기 탭 테이프 상에 솔더 볼들을 부착시키는 단계; 및Attaching solder balls to the tab tape; And 상기 1차 및 2차 코팅 용액에 의해 봉지된 반도체 칩들을 분리시키는 단계를 포함하는 것을 특징으로 하는 칩 크기 패키지의 제조방법.And separating the semiconductor chips encapsulated by the primary and secondary coating solution. 제 1 항에 있어서, 상기 1차 소잉은 솔더 범프가 형성된 웨이퍼 면을 접착 테이프 상에 부착·고정시킨 상태에서 실시하는 것을 특징으로 하는 칩 크기 패키지의 제조방법.The method of claim 1, wherein the first sawing is performed in a state where the wafer surface on which the solder bumps are formed is attached and fixed on an adhesive tape. 제 1 항 또는 제 2 항에 있어서, 상기 1차 소잉은 웨이퍼의 전체 두께에 대하여 50% 미만의 두께를 소잉하는 것을 특징으로 하는 칩 크기 패키지의 제조방법.3. The method of claim 1 or 2, wherein said primary sawing is sawing a thickness of less than 50% of the total thickness of the wafer. 제 1 항에 있어서, 상기 히트 슬러그는 반도체 칩의 하부면과 측면 일부분을 감싸도록 구비되는 것을 특징으로 하는 칩 크기 패키지의 제조방법.The method of claim 1, wherein the heat slug is provided to surround a lower surface and a portion of a side surface of the semiconductor chip. 제 4 항에 있어서, 상기 히트 슬러그는 반도체 칩의 측면에 위치되는 부분이 상기 반도체 칩과 소정 간격 이격되어 배치되는 것을 특징으로 하는 칩 크기 패키지의 제조방법.5. The method of claim 4, wherein the heat slug is disposed at a side portion of the semiconductor chip spaced apart from the semiconductor chip by a predetermined distance. 6. 제 1 항에 있어서, 상기 반도체 칩들은 상기 히트 슬러그의 측면을 따라 소잉된 것을 특징으로 하는 칩 크기 패키지의 제조방법.2. The method of claim 1 wherein the semiconductor chips are sawed along the sides of the heat slug.
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WO1996003772A2 (en) * 1994-07-26 1996-02-08 Philips Electronics N.V. Method of manufacturing a semiconductor device for surface mounting, and semiconductor device for surface mounting
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