KR100377183B1 - A single transistor ferroelectric memory and driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a single transistor ferroelectric memory and a driving method thereof, and an object thereof is to provide a single transistor ferroelectric memory having random read / write and a driving method thereof. The present invention implements a single transistor ferroelectric memory with random reads / writes. The thermal cavity well line is electrically isolated from the adjacent well line for random access, and the word line at the gate of the single transistor ferroelectric memory cell, the source line (well line) at the source (well), and the bit line and sense amplifier at the drain It is easy to create a bipolar one-pulse voltage to drive the ferroelectric memory without the write disturb by making it connected, and to use a single power supply to apply a low lead voltage to the word line from the internal read voltage generator during the read operation. It was made. In addition, low power and high speed operation characteristics are realized by using a polarization phenomenon of the ferroelectric when writing data to a single transistor ferroelectric memory, and by using a change of threshold voltage when reading data.

Description

A single transistor ferroelectric memory and driving method thereof

TECHNICAL FIELD The present invention relates to semiconductor technology, and more particularly, to a single transistor ferroelectric memory and a driving method thereof.

A general MOS transistor uses a silicon oxide film (SiO ₂ ) as a gate insulating film to control its operation according to a voltage applied to a gate. On the other hand, the single transistor ferroelectric transistor uses a method of controlling the operation according to the polarization characteristics of the ferroelectric material using a ferroelectric material (for example, PZT, SBT, etc.) as the gate insulating film.

A nonvolatile ferroelectric memory is a memory device using hysteresis characteristics between a voltage and a storage charge of a ferroelectric, in which polarization charges are preserved even when a power supply is turned off. The nonvolatile ferroelectric memory is generally composed of one transistor and one capacitor or a single transistor.

1 is a diagram illustrating charge-voltage hysteresis of a typical ferroelectric device, and the charge amount has two different values A and B when the voltage is 0V. By using this, the first and second states of the ferroelectric memory may be implemented. The polarization state of the ferroelectric element is arranged in a predetermined direction according to the voltage applied between the thin films to become a first state and a second state.

2A and 2B are conceptual diagrams illustrating an operating principle of an N-channel single transistor ferroelectric element, and when the voltage between the gate and the P-type silicon substrate (P-Si) is positive (Fig. 2A), the P-type silicon substrate ( P-Si) charges are induced on the surface, and if negative (FIG. 2B), charges are not induced.

3 is a block diagram of a conventional nonvolatile memory block.

The conventional nonvolatile memory includes a main controller 30 for generating various control signals required for a memory operation, a write voltage generator 31 for generating a write voltage by inputting a high program voltage Vpp, A word line controller 30 for selecting a word line through an address and a word line voltage selector for selectively applying a voltage to the selected word line by receiving a write voltage from the write voltage generator 31. 33), a memory cell array 34 in which a plurality of word lines, bit lines, source lines, and transistors are arranged, and an output form (eg, byte, word, or bit form) of a memory output through a sense amplifier during a read operation. And a sense amplifier unit 36 for sensing the bit line voltages of the selected cell and the unselected cell during the read operation. Here, the memory cell array 34 uses a common well, and a high program voltage Vpp is applied to a word line during a write operation (referencely, Vdd is normally applied to a word line).

4A illustrates an arrangement state of a cell array of a single transistor ferroelectric memory according to the related art, and includes a plurality of word lines WL1,... WLn and a plurality of bit lines BL1,... BLm on a common well WELL. ), And ferroelectric transistors FM1, ... FMm, ... FMn, ... FMn + m are used as the matrix structure so that the < RTI ID = 0.0 >

In the conventional cell arrangement, the supply voltage Vdd is applied to a desired word line, and a voltage of 0 V is applied to the bit line and the source line. A voltage of 0 V is applied to the word line and a voltage of Vdd is applied to the source line and the bit line, respectively, in order to prevent the program in the first state.

In this case, as shown in FIG. 4B, a write disturb phenomenon occurs in an unselected cell in which a voltage of ground voltages GND and 0V is applied to a word line and Vdd is applied to a source and a drain. There was a problem.

In order to program the selected cell to the second state, a voltage of 0V is applied to the gate and Vdd is applied to the source, the drain, and the well, respectively. In this case, since each cell cannot be selected, a voltage is commonly applied to all transistors of the array structure.

The cells in which the drain disturb is generated are more likely to be programmed into the second state, and the cells that repeatedly experience the drain disturbance when the neighboring cells are programmed into the first state are removed. There is a problem that a program disturb occurs in which data programmed in a state 1 is changed to a second state and data is destroyed.

As described above, in the conventional single transistor ferroelectric memory, the word line needs to apply Vdd to the source line and the bit line of the entire unselected cell in order to prevent the programming of the unselected cell. There is a problem that occurs.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a single transistor ferroelectric memory having random read / write and a driving method thereof.

1 is a charge-hysteresis characteristic diagram of a typical ferroelectric device.

2A and 2B are conceptual diagrams showing the operating principle of an N-channel single transistor ferroelectric element.

3 is a block diagram of a conventional nonvolatile memory block.

4A is a circuit diagram of a cell array of a single transistor ferroelectric memory according to the prior art.

4B is a diagram illustrating a voltage application state of unselected cells in the memory cell array of FIG. 4A.

5 is a block diagram of a single transistor ferroelectric memory according to an embodiment of the present invention.

6 is a circuit diagram of a cell array of a single transistor ferroelectric memory in accordance with one embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

50: main control unit 51: lead voltage generation unit

52: word line control unit 53: source line control unit

54: word line voltage selector 55: memory cell array

56: bit line control unit 57: sense amplifier unit

According to an aspect of the present invention, there is provided a single transistor ferroelectric memory, comprising: main control means for generating a plurality of control signals required for operation of the memory; A decode circuit for selecting a specific cell according to an address input during a read / write operation, the word line control means and a source line control means for providing a predetermined voltage to the selected cell; Read voltage generation means for generating a plurality of read voltages in a read operation; Word line voltage selecting means for selectively applying a predetermined read voltage from the read voltage generating means to selectively apply a voltage to a selected word line; A memory cell array including a plurality of word lines, bit lines, source lines, and ferroelectric transistors; Bit line control means for determining an output form of the memory during a read operation; And sensing amplification means for sensing bit line voltages of selected and unselected cells during a read operation, wherein the memory cell array is arranged in a direction parallel to the bit lines and the source lines to form a thermal common well. And a plurality of well lines connected to the source lines of the corresponding columns and electrically isolated from adjacent hot common wells.

Preferably, only a single power supply of supply voltage Vdd and ground voltage GND is applied to the memory cell array.

In addition, the present invention provides a method of operating a single transistor ferroelectric memory, in which a word line connected to a cell is transitioned from a ground voltage (GND) to a supply voltage (Vdd) in order to program a selected cell to a first state. The well line and the source line to which the cell is connected are shifted from the supply voltage Vdd to the ground voltage GND.

Preferably, in order to program the cell to the second state, the word line to which the cell is connected is shifted to the ground voltage Gnd, and the supply voltage Vdd is applied to the well line and the source line to which the cell is connected.

Preferably, in order to read the data of the cell, the read voltage is applied to the word line to which the cell is connected, and the ground voltage GND is applied to the well line and the source line to which cells other than the cell are connected.

That is, the present invention implements a single transistor ferroelectric memory with random reads / writes. The thermal cavity well line is electrically isolated from the adjacent well line for random access, and the word line at the gate of the single transistor ferroelectric memory cell, the source line (well line) at the source (well), and the bit line and sense amplifier at the drain Bipolar one-pulse voltage (with pulses swinging at + Vdd and -Vdd) that can drive a ferroelectric memory without the need for write disturb, so that the voltage difference between the gate and the well must be a bipolar one-pulse to drive a single transistor ), And a single power supply allows the internal read voltage generator to apply a low read voltage to the word line during the read operation. In addition, low power and high speed operation characteristics are realized by using a polarization phenomenon of the ferroelectric when writing data to a single transistor ferroelectric memory, and by using a change of threshold voltage when reading data.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

5 is a block diagram illustrating a single transistor ferroelectric memory according to an embodiment of the present invention, which will be described below with reference to the drawings.

The single transistor ferroelectric memory according to the present embodiment includes a main controller 50 for making a basic control signal of the single transistor ferroelectric memory, and a decode circuit for selecting a specific cell according to an address input during a read / write operation. From the word line control unit 52 and the source line control unit 53 for making an appropriate voltage for the display device, the read voltage generation unit 51 for generating a plurality of read voltages during the read operation, and the read voltage generation unit 51. A word line voltage selector 54 for selectively applying a read voltage to a selected word line, a memory cell array 55 including a plurality of word lines, bit lines, source lines, and ferroelectric transistors; Determining the output type (eg, byte, word or bit type) of the memory output through the sense amplifier 57 during the read operation And a bit line control unit 56, and a sense amplifier section 57 for sensing the bit line voltage of the selected cell and the non-selected cell during the read operation.

The dual word line controller 52, the bit line controller 56, the source line controller 53, the read voltage generator 57, and the word line voltage selector 54 may be implemented by simple logic, respectively. Unlike the conventional nonvolatile memory shown, the ferroelectric memory with low voltage operation does not need a high power supply, and can be implemented as a single power supply.

6 is a diagram illustrating an arrangement of a cell array of a single transistor ferroelectric memory according to an embodiment of the present invention, which will be described below with reference to the drawings.

In the cell array of the single transistor ferroelectric memory according to the present embodiment, each cell is arranged in rows and columns in the same manner as a general nonvolatile memory array, and one word line has gates of a plurality of m ferroelectric transistors. . In addition, the source lines SL1, SL2, ..., SLm and the bit lines BL1, BL2, ..., BLm are commonly used as column lines, and the well lines WELL1, WELL2, ..., WELLm are also column lines. Commonly used, word lines WL1, WL2, ..., WLn are arranged to intersect with them. The well line is connected to the source line.

In addition, well isolation is achieved by heat lines as shown. That is, the wells are connected to each other in the column direction, and the wells are separated from each other in the transverse direction. Thus, the thermal common welllines of adjacent rows are not electrically connected directly to each other. Since common welllines of adjacent columns are not connected to each other, potentials can be selectively applied to wells of any row through the common welllines.

Hereinafter, the write operation of the single transistor ferroelectric memory will be described. In the initial state, the word line is in the ground voltage (GND) state, and the source line (well line) is the supply voltage (Vdd state), so the voltage difference between the gate and the well (source) becomes negative (-), and thus the polarization of the ferroelectric The selected word line is shifted from Gnd to Vdd and the source line (well line) from Vdd to Gnd to program the particular cell into the first state, resulting in a positive voltage difference between the selected gate and the well (source). In this case, Vdd is applied to the well line (source line) of the non-selected cells and Gnd is applied to the word line, so that the initial polarization state is maintained as it is, so that no write disturb occurs. To program in the second state, Gnd is applied to the word line and Vdd is applied to the well line (source line) The word line controller 52 and the source line controller 53 apply a DC bias to both the gate and the source (well). By single tran It is easy to create a bipolar one pulse that can drive a sturdy ferroelectric memory, and the decoder can also be implemented with ease, as the voltage between the gate and the source is in the form of a bipolar one pulse, so ferroelectric polarization without light disturb The write operation is possible due to the characteristic, and since the write voltage is constant at Vdd, a separate write voltage generator is not required.

Hereinafter, the read operation of the single transistor ferroelectric memory will be described. Due to the ferroelectric polarization characteristic, the threshold voltage change of the transistor occurs. The data read operation may be performed by using the characteristic of the threshold voltage change. In general, the threshold voltage of a programmed cell becomes high, and the threshold voltage of an unprogrammed cell is the same as that of a general MOS transistor. To read the storage information of the selected memory cell at an arbitrary position, a predetermined read voltage is applied to the word line of the selected cell, and a ground voltage GND is applied to the source line (well line) to sense the bit line voltage. do. That is, if the cell to be read is a programmed cell, the read voltage applied to the gate is lower than the threshold voltage so that the cell is turned off and the current hardly flows. On the contrary, if the cell is not programmed, the gate voltage is higher than the threshold voltage, and the cell is turned on to allow current to flow. The sense amplifier 57 detects this and outputs it. As described above, the single transistor ferroelectric memory according to the present embodiment senses data by using the characteristics of the threshold voltage change due to the ferroelectric polarization, and a plurality of low voltages in the read voltage generator 51 using the single power sources Vdd and GND. A read voltage may be generated and applied to the word line.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention described above enables random read / write, has a low power and high-speed operation characteristics as compared to conventional nonvolatile memories (EEPROM, FLASH), and can implement a single transistor ferroelectric memory without write disturb.

Claims (5)

In a single transistor ferroelectric memory, Main control means for generating a plurality of control signals required for operation of the memory; A decode circuit for selecting a specific cell according to an address input during a read / write operation, the word line control means and a source line control means for providing a predetermined voltage to the selected cell; Read voltage generation means for generating a plurality of read voltages in a read operation; Word line voltage selecting means for selectively applying a predetermined read voltage from the read voltage generating means to selectively apply a voltage to a selected word line; A memory cell array in which a plurality of word lines, bit lines, source lines, and ferroelectric transistors are disposed; Bit line control means for determining an output form of the memory during a read operation; And Sensing amplification means for sensing bit line voltages of selected and unselected cells during a read operation; The memory cell array, A plurality of well lines arranged in a direction parallel to the bit line and the source line to form a hot common well and connected to the source line of the corresponding column and electrically isolated from adjacent hot common wells. Transistor ferroelectric memory. The method of claim 1, And applying only a single power supply of supply voltage (Vdd) and ground voltage (GND) to the memory cell array. In the method of operating the single transistor ferroelectric memory of claim 1, To program the selected cell to the first state, The word line to which the cell is connected is shifted from the ground voltage GND to the supply voltage Vdd, and the well line and the source line to which the cell is connected are shifted from the supply voltage Vdd to the ground voltage GND. Method of operation of a single transistor ferroelectric memory. The method of claim 3, To program the cell to a second state, And translating the word line to which the cell is connected to the ground voltage (Gnd) and applying a supply voltage (Vdd) to the well line and the source line to which the cell is connected. The method according to claim 3 or 4, To read the data of the cell, And applying the read voltage to a word line to which the cell is connected, and applying a ground voltage (GND) to a well line and a source line to which cells other than the cell are connected.