KR100369354B1 - Method for reducing contact resistance by using low energy dry cleaning and rapid thermal annealing - Google Patents
Method for reducing contact resistance by using low energy dry cleaning and rapid thermal annealing Download PDFInfo
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- KR100369354B1 KR100369354B1 KR10-1999-0025900A KR19990025900A KR100369354B1 KR 100369354 B1 KR100369354 B1 KR 100369354B1 KR 19990025900 A KR19990025900 A KR 19990025900A KR 100369354 B1 KR100369354 B1 KR 100369354B1
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 238000005108 dry cleaning Methods 0.000 title claims abstract description 31
- 238000004151 rapid thermal annealing Methods 0.000 title 1
- 230000008569 process Effects 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 30
- 238000010438 heat treatment Methods 0.000 claims abstract description 23
- 239000006227 byproduct Substances 0.000 claims abstract description 14
- 229910052736 halogen Inorganic materials 0.000 claims abstract description 12
- 150000002367 halogens Chemical class 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 7
- 238000004630 atomic force microscopy Methods 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007086 side reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005211 surface analysis Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
본 발명은 보다 용이한 공정으로 콘택홀 형성을 위한 식각 과정에서 발생한 하부 접합면의 손상을 효과적으로 복구할 수 있는, 저에너지 건식 세정 및 급속열처리 공정을 이용한 콘택 저항 감소 방법에 관한 것으로, 반도체 소자 제조 공정에서 콘택홀 형성을 위한 고에너지 플라즈마 건식 식각에 의해 콘택 바닥 접합면이 손상된 것을 복구하기 위하여 저에너지 건식 세정 및 고속 열처리를 복합적으로 실시하는데 그 특징이 있다. 즉, 콘택홀 형성을 위한 식각 공정 후, 1차 저에너지 건식 세정으로 식각 부산물을 제거한다. 이어서, 2차 저에너지 건식 세정 공정을 실시하면서 할로겐 램프를 이용하여 복합적으로 급속열처리를 실시하여 콘택 하부접합면 손상을 완전히 제거한다. 이와 같은 공정으로 식각 과정에서 발생한 하부 접합면의 변형을 최대한 보상하고, 공정 부산물을 저에너지 건식 세정을 이용하여 제거시킴으로써 콘택 하부 접합면의 구조 변형을 최소화시킬 수 있다.The present invention relates to a method for reducing contact resistance using a low energy dry cleaning and rapid heat treatment process, which can effectively repair damage to a lower junction surface generated during an etching process for forming a contact hole in an easier process. In order to recover the damage of the contact bottom bonding surface by the high-energy plasma dry etching for forming the contact hole, the low energy dry cleaning and the high speed heat treatment are combined. That is, after the etching process for forming the contact hole, the etching by-products are removed by primary low energy dry cleaning. Subsequently, a rapid heat treatment is performed in combination with a halogen lamp while performing the second low energy dry cleaning process to completely remove the contact lower junction surface damage. In this process, deformation of the lower joint surface generated during the etching process can be compensated to the maximum, and process by-products can be removed by using low energy dry cleaning, thereby minimizing structural deformation of the lower contact surface of the contact.
Description
본 발명은 반도체 메모리 소자 제조 방법에 관한 것으로, 특히 반도체 메모리 소자의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for forming a contact hole in a semiconductor memory device.
반도체 소자 제조 과정에서는 하부 접합면이 드러나도록 하기 위하여 콘택홀을 형성하는 공정이 있다. 즉, 하부 접합면 상에 형성된 층간절연막 등을 선택적으로 식각하여 하부 접합면을 노출시키는데, 이러한 식각 공정의 부산물인 절연막이 접합면 상에 잔류하고 계면 손상으로 이온이 주입되어 있는 접합면이 변형된다. 이러한 변형을 복구시키지 않을 경우 콘택저항이 증가하며, 소자의 특성이 저하되는 문제점이 있다.In the process of manufacturing a semiconductor device, there is a process of forming a contact hole so that the lower bonding surface is exposed. That is, the interlayer insulating film formed on the lower bonding surface is selectively etched to expose the lower bonding surface. An insulating film which is a by-product of the etching process remains on the bonding surface and the bonding surface into which ions are implanted due to interface damage is deformed. . If the deformation is not restored, there is a problem in that contact resistance is increased and device characteristics are deteriorated.
콘택홀 형성을 위한 식각 공정은 하부 박막층의 종류에 따라 공정 조건을 달리한다.In the etching process for forming the contact hole, process conditions vary depending on the type of the lower thin film layer.
또한, 식각으로 드러난 콘택홀 바닥의 하부 박막 계면 상변형을 최소화시키고 잔류하는 절연막의 제거를 위하여 저농도 습식 세정 및 저에너지 건식 세정 등을 실시한다. 그러나, 이러한 방법으로는 콘택홀 하부 접합면 손상의 보상 및 식각부산물의 제거가 충분히 이루어지지 못하여 효과적으로 콘택 저항 증가를 억제하지 못하고 있는 실정이다.In addition, low concentration wet cleaning and low energy dry cleaning are performed to minimize the phase deformation of the lower thin film interface at the bottom of the contact hole exposed by etching and to remove the remaining insulating film. However, this method does not sufficiently compensate for damage to the lower contact surface of the contact hole and remove the etch byproducts, and thus does not effectively suppress an increase in contact resistance.
고에너지 플라즈마 건식 식각에 의한 손상은 AFM(Atomic Force Microscopy) 또는 XPS(X-ray photoelectron spectroscopy) 등의 표면 분석 장치를 이용하여 확인한다.Damage due to high energy plasma dry etching is confirmed using a surface analysis device such as atomic force microscopy (AFM) or x-ray photoelectron spectroscopy (XPS).
첨부된 도면 도1a는 콘택홀 형성을 위한 식각 후 하부 접합면의 상태를 보이는 AFM 사진이다.1A is an AFM photograph showing a state of a lower bonding surface after etching for forming a contact hole.
도1b는 식각과정에서 발생한 손상을 보상하기 위한 급속열처리를 실시한 상태를 보이는 AFM 사진으로서, 급속열처리만을 적용한 경우 실제 표면의 손상이 효과적으로 개선되지 못함을 보이고 있다.FIG. 1B is an AFM photograph showing a state in which rapid heat treatment is performed to compensate for damage occurring during an etching process, and shows that the surface damage is not effectively improved when only rapid heat treatment is applied.
도1c는 저에너지 건식 세정을 실시한 후 하부 접합면의 상태를 보이는 AFM 사진이다. 저에너지 건식 세정은 CF4및 O2가스를 이용하여 식각 챔버에서 인시튜(In-Situ)로 진행하는 것이 일반적인데, 이 경우 콘택홀 형성을 위한 식각 보다 낮은 출력으로 상대적으로 짧은 시간 동안 공정을 실시하면, 화학적 손상 및 결정학적 손상은 거의 완전하게 제거할 수 있다. 그러나, 비록 저에너지라 할지라도 식각 공정이므로 접합면이 손실되는 문제점은 피할 수 없다.Figure 1c is an AFM photograph showing the state of the lower bonding surface after performing a low energy dry cleaning. Low-energy dry cleaning is generally carried out in-situ from the etching chamber using CF 4 and O 2 gases, in which case the process is carried out for a relatively short time at a lower power than the etching for forming contact holes. In turn, chemical and crystallographic damage can be almost completely eliminated. However, even if the energy is low, because of the etching process, the problem of loss of the joint surface is inevitable.
한편, 손상된 접합면을 복구하기 위하여 급속열처리 공정을 실시하는데 통상 급속열처리 공정을 실시하기 위한 별도의 공정을 진행해야 하므로 공정이 복잡해지는 문제점이 있다.On the other hand, there is a problem in that the process is complicated because a separate process for performing a rapid heat treatment process is usually required to perform a rapid heat treatment process to recover a damaged joint surface.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 보다 용이한 공정으로 콘택홀 형성을 위한 식각 과정에서 발생한 하부 접합면의 손상을 효과적으로 보상할 수 있는, 저에너지 건식 세정 및 급속열처리 공정을 이용한 콘택 저항 감소 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is an easier process, the contact resistance using a low-energy dry cleaning and rapid heat treatment process that can effectively compensate for the damage of the lower bonding surface generated during the etching process for forming the contact hole The purpose is to provide a reduction method.
도1a 내지 도1c는 종래 기술에 따른 콘택홀 형성시의 접합 손상 상태를 보이는 AFM 사진,1A to 1C are AFM photographs showing a bonding damage state when forming a contact hole according to the prior art;
도2a 내지 도2c는 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 형성 공정 단면도.2A to 2C are cross-sectional views of a contact hole forming process of a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
10: 실리콘 기판 11: 접합영역10: silicon substrate 11: junction area
12: 절연 산화막 A: 식각 부산물12: insulating oxide A: etching byproduct
B: 손상된 접합영역 표면B: damaged joint surface
C: 손상부위가 열처리로 제거된 접합영역 표면C: Surface of the junction area where the damaged part was removed by heat treatment
상기와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상부에 형성된 층간절연막을 플라즈마를 이용한 건식식각으로 선택적으로 제거하여 그 저면에 접합영역을 노출시키는 콘택홀을 형성하는 단계; 상기 접합영역 상에 잔류하는 식각부산물을 제거하기 위하여 플라즈마를 이용한 1차 건식 세정 공정을 실시하는 단계; 및 상기 접합영역의 식각 손상을 보상하기 위해 플라즈마를 이용한 2차 건식 세정 공정을 실시하면서 동시에 급속열처리를 실시하는 단계를 포함하는 반도체 소자의 콘택홀 형성 방법을 제공한다.According to an aspect of the present invention, there is provided a method of forming a contact hole on a bottom surface of a semiconductor substrate by selectively removing an interlayer insulating layer formed on an upper surface of a semiconductor substrate by dry etching using plasma; Performing a first dry cleaning process using plasma to remove the etch byproducts remaining on the junction region; And performing a rapid heat treatment while performing a second dry cleaning process using plasma to compensate for the etching damage of the junction region.
본 발명은 반도체 소자 제조 공정에서, 콘택홀 형성을 위한 고에너지 플라즈마 건식 식각에 의해 콘택 바닥 접합면이 손상된 것을 복구하기 위하여 저에너지 건식 세정 및 고속 열처리를 복합적으로 실시하는데 그 특징이 있다.The present invention is characterized in that a combination of low energy dry cleaning and high speed heat treatment is performed in order to recover damage of the contact bottom bonding surface by high energy plasma dry etching for forming a contact hole in a semiconductor device manufacturing process.
즉, 콘택홀 형성을 위한 식각 공정 후, 1차 저에너지 건식 세정으로 식각 부산물을 제거한다. 이어서, 2차 저에너지 건식 세정 공정을 실시하면서 할로겐 램프(Halogen Lamp)를 이용하여 복합적으로 급속열처리를 실시하여 콘택 하부접합면 손상을 완전히 제거한다. 이와 같은 공정으로 식각 과정에서 발생한 하부 접합면의 변형을 최대한 보상하고, 공정 부산물을 저에너지 건식 세정을 이용하여 제거함으로써 콘택 하부 접합면의 구조 변형을 최소화시킬 수 있다.That is, after the etching process for forming the contact hole, the etching by-products are removed by primary low energy dry cleaning. Subsequently, a rapid heat treatment is performed in combination with a halogen lamp while performing a second low energy dry cleaning process to completely remove damage to the contact lower junction surface. In this process, the deformation of the lower joint surface generated during the etching process can be compensated to the maximum, and the process by-products can be removed using low energy dry cleaning, thereby minimizing the structural deformation of the lower contact surface of the contact.
일반적으로 식각 공정에서 사용되고 있는 고에너지 플라즈마 건식 식각과 비교하여 저에너지 건식 세정은 접합면에 손상을 가하지 않고 접합면에 잔존하는 식각 부산물을 제거시키는 장점을 갖고 있다. 이러한 장점을 이용하면 접합면에 잔존하는 식각 부산물을 제거할 수 있을 뿐만 아니라, 식각 후의 거칠어진 접합면을 완화시켜 줄 수 있다.Compared with the high energy plasma dry etching generally used in the etching process, the low energy dry cleaning has an advantage of removing the etching by-products remaining on the bonding surface without damaging the bonding surface. By using this advantage, not only the etching by-products remaining on the joint surface can be removed, but also the rough joint surface after etching can be alleviated.
본 발명은 콘택홀 형성을 위한 식각 챔버와 동일한 챔버에서 저에너지 건식 세정 공정을 실시하며 저에너지 건식 세정에 의한 접합면의 손실을 최소화하기 위하여 CF4및 Ar 혼합가스를 이용한다. CF4및 Ar 혼합가스를 이용하는 경우 CF4및 O2혼합가스에 비하여 그 세정 효과는 떨어지나, 다른 형태의 식각 반응을 하지 않으므로 식각 공정에 의한 접합면 손실 등의 부작용을 미연에 방지 할 수 있다. 또한, 화학적 반응에도 미약한 반응을 보이므로 저에너지 건식세정과 급속열처리로 이루어지는 복합 공정 적용에 유리한 장점을 가지고 있다.The present invention performs a low energy dry cleaning process in the same chamber as the etching chamber for forming a contact hole, and uses a mixture of CF 4 and Ar to minimize the loss of the bonding surface due to low energy dry cleaning. When the mixed gas of CF 4 and Ar is used, the cleaning effect is inferior to that of the mixed gas of CF 4 and O 2 , but other types of etching reactions are not performed, thereby preventing side effects such as loss of the bonding surface due to the etching process. In addition, since the chemical reaction is weak, it has an advantage in the application of a complex process consisting of low energy dry cleaning and rapid heat treatment.
한편, 식각 챔버 내에 할로겐 램프를 장착하고 이를 이용하여 저에너지 건식 세정과 동시에 급속열처리를 실시한다. 700 W 이상의 할로겐 램프를 이용하여 짧은 시간에 고온 상태를 형성한다.Meanwhile, a halogen lamp is mounted in the etching chamber and rapid heat treatment is performed simultaneously with low energy dry cleaning. Halogen lamps of 700 W or more are used to form high temperatures in a short time.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 형성 방법을 상세히 설명한다.Hereinafter, a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 도2a에 도시한 바와 같이 트랜지스터의 소오스·드레인 등과 같은 접합영역(11)이 형성된 실리콘 기판(10) 상에 절연산화막(12)을 증착하고, 포토마스크를 이용하여 콘택홀 영역을 정의하는 식각마스크를 형성하고, 1000 W 내지 2000 W의 전력을 인가하여 고에너지 플라즈마로 절연산화막(12)을 건식식각하여 그 저면에 상기 접합영역(11)을 노출시키는 콘택홀을 형성한다. 이와 같은 콘택홀 형성 과정에서 접합영역(11)이 손상되며 식각 부산물(A)이 잔류하게 된다. 상기 건식식각은 700 W 이상 출력을 가져 짧은 시간에 고온을 발할 수 있는 할로겐 램프가 장착된 챔버 내에서 실시하며 이때 할로겐 램프는 꺼진 상태이다.First, as illustrated in FIG. 2A, an insulating oxide film 12 is deposited on a silicon substrate 10 on which a junction region 11 such as a source and a drain of a transistor is formed, and then a contact hole region is defined using a photomask. An etching mask is formed, and the insulating oxide film 12 is dry-etched with a high energy plasma by applying a power of 1000 W to 2000 W to form a contact hole exposing the junction region 11 on the bottom thereof. In the process of forming the contact hole, the junction region 11 is damaged and the etching byproduct A remains. The dry etching is performed in a chamber equipped with a halogen lamp capable of generating a high temperature in a short time with an output of 700 W or more, wherein the halogen lamp is turned off.
다음으로, 도2b에 도시한 바와 같이 손상된 접합영역(11)의 표면을 보상하기 위하여 상기 건식식각을 실시한 챔버 내에서 1000 W 미만의 전력으로 1차 저에너지 건식 세정공정을 실시하여 식각 부산물을 제거한다. 이에 따라 식각 부산물이 제거되고 손상된 접합영역 표면(B)이 드러난다. 이때, 할로겐 램프는 꺼진 상태이며 세정 가스로는 CF4와 O2의 혼합가스를 이용하거나, CF4와 Ar의 혼합가스를 이용한다.Next, in order to compensate for the surface of the damaged junction region 11 as shown in FIG. 2B, an etch byproduct is removed by performing a first low energy dry cleaning process with a power of less than 1000 W in the chamber where the dry etching is performed. . This removes the etch by-products and reveals the damaged junction area surface (B). At this time, the halogen lamp is turned off and the cleaning gas is used as a mixed gas of CF 4 and O 2 , or a mixed gas of CF 4 and Ar.
다음으로, 도2c에 도시한 바와 같이 2차 저에너지 건식 세정 공정을 진행하면서 동시에 챔버 내에 장착된 할로겐 램프를 켜서 급속열처리를 실시하여 접합영역(11)의 손상을 완전히 제거한다. 도면부호 'C'는 손상부위가 열처리로 제거된 접합영역 표면을 나타낸다. 2차 저에너지 건식 세정 공정은 1000 W 미만의 전력을 인가하고 CF4와 Ar의 혼합가스를 이용한다.Next, as shown in FIG. 2C, the secondary low energy dry cleaning process is performed, and at the same time, the halogen lamp mounted in the chamber is turned on to perform rapid heat treatment to completely remove the damage of the junction region 11. Reference numeral 'C' denotes the junction area surface from which the damaged part is removed by heat treatment. The second low energy dry cleaning process applies less than 1000 W of power and uses a mixture of CF 4 and Ar.
전술한 바와 같이 이루어지는 본 발명은 콘택홀 형성을 위한 식각 공정, 저에너지 건식 세정 공정 및 급속열처리 공정을 하나의 챔버에서 진행할 수 있어 콘택 하부 접합면의 손상을 쉽게 제거하고, 접합면을 양질화시킬 수 있다.According to the present invention made as described above, the etching process for forming the contact hole, the low energy dry cleaning process, and the rapid heat treatment process can be performed in one chamber, thereby easily removing damage to the lower contact surface of the contact and improving the quality of the bonding surface. have.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 단순한 후속 열처리 공정으로 콘택홀 하부 접합면의 손상을 일부 복구하던 종래 방법과 달리 건식식각 후 동일 챔버에서 급속열처리 및 저에너지 건식 세정 공정을 동시에 진행함으로써 고에너지 플라즈마 건식 식각에 의한 손상을 효과적으로 보상할 수 있다.According to the present invention made as described above, unlike the conventional method of partially repairing the damage of the contact hole lower junction surface by a simple subsequent heat treatment process, a rapid heat treatment and a low energy dry cleaning process are simultaneously performed in the same chamber after dry etching, thereby providing high energy plasma dry etching. Can effectively compensate for damage.
또한, CF4와 Ar 혼합가스 분위기에서 할로겐 램프를 이용한 급속열처리를 실시함으로써 이러한 복합 공정의 경우 발생하는 부수적 반응의 발생을 억제할 수 있다.In addition, by performing a rapid heat treatment using a halogen lamp in a CF 4 and Ar mixed gas atmosphere, it is possible to suppress the occurrence of side reactions occurring in the case of such a complex process.
따라서, 소자의 전기적인 특성을 향상시킬 수 있으며, 물리적인 특성의 개선을 통하여 타 기술에 비하여 상당한 시너지(Synergy) 효과를 기대할 수 있다.Therefore, the electrical characteristics of the device can be improved, and significant synergy effect can be expected compared to other technologies through the improvement of the physical characteristics.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100717811B1 (en) * | 2006-02-28 | 2007-05-11 | 주식회사 하이닉스반도체 | Method for forming contact in semiconductor device |
| KR100744246B1 (en) * | 2005-12-28 | 2007-07-30 | 동부일렉트로닉스 주식회사 | Method for fabricating metal line of semiconductor device |
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| KR20010011322A (en) * | 1999-07-27 | 2001-02-15 | 김영환 | Method for forming of contact |
| KR101732023B1 (en) | 2010-12-23 | 2017-05-02 | 삼성전자주식회사 | Methods of forming semiconductor devices |
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|---|---|---|---|---|
| JPS6473717A (en) * | 1987-09-16 | 1989-03-20 | Matsushita Electric Ind Co Ltd | Selective deposition of metal |
| KR900019159A (en) * | 1989-05-09 | 1990-12-24 | 후지쓰 가부시끼가이샤 | Semiconductor device manufacturing method |
| JPH0423323A (en) * | 1990-05-14 | 1992-01-27 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR19980043610A (en) * | 1996-12-04 | 1998-09-05 | 김영환 | Contact hole cleaning method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6473717A (en) * | 1987-09-16 | 1989-03-20 | Matsushita Electric Ind Co Ltd | Selective deposition of metal |
| KR900019159A (en) * | 1989-05-09 | 1990-12-24 | 후지쓰 가부시끼가이샤 | Semiconductor device manufacturing method |
| JPH0423323A (en) * | 1990-05-14 | 1992-01-27 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR19980043610A (en) * | 1996-12-04 | 1998-09-05 | 김영환 | Contact hole cleaning method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100744246B1 (en) * | 2005-12-28 | 2007-07-30 | 동부일렉트로닉스 주식회사 | Method for fabricating metal line of semiconductor device |
| KR100717811B1 (en) * | 2006-02-28 | 2007-05-11 | 주식회사 하이닉스반도체 | Method for forming contact in semiconductor device |
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