KR100358134B1 - Output driving circuit for reducing ground bouncing noise - Google Patents

Abstract

The present invention is to provide an output driving circuit to reduce the ground bounce noise by eliminating the case that the PMOS transistor and the NMOS transistor is turned on at the same time to eliminate the direct current flowing between the power supply voltage terminal and the ground power supply terminal. According to an aspect of the present invention, there is provided an output driving circuit comprising: pull-up and pull-down driving means each including a PMOS transistor and an NMOS transistor for pull-up or pull-down driving an output stage in response to a voltage level value of a pull-up control node or a pull-down control node; A short pulse generating means for receiving data input for output and generating a transition pulse when the data is transitioned; Pull-up node control means for controlling the voltage level value of the pull-up control node in response to the transition pulse and the data output from the short pulse generation means; And pull-down node control means for controlling the voltage level value of the pull-down control node in response to the transition pulse and the data output from the short pulse generating means.

Description

Output driving circuit to reduce ground bounce noise {OUTPUT DRIVING CIRCUIT FOR REDUCING GROUND BOUNCING NOISE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output driving circuit connected to an output terminal of a semiconductor device for driving an output of the device, and more particularly, ground bouncing noise generated by a large amount of current flowing instantaneously between a power supply voltage terminal and a ground power supply terminal. An output drive circuit for reducing the

The output driving circuit may be configured in various structures, but the ground bounce noise in the output driving circuit will be described through the output driving circuit having the simplest structure.

1 is a diagram showing an output driving circuit of the simplest structure, which is an output driving circuit of a CMOS inverter structure composed of a PMOS transistor and an NMOS transistor.

Specifically, the output buffer of FIG. 1 includes a PMOS transistor P1 and an NMOS transistor N1 that pull-up or pull-down drive the output terminal PAD, respectively, in response to a data signal Input to be output.

In general, the ground bounce noise is also called di / dt noise, and instantaneous current flows between the power supply voltage terminal (VDD) and the ground power supply terminal (VSS) to exist in the parasitic RLC component and package inside the chip. Due to the RLC component, the potential levels of the power supply voltage terminal VDD and the ground power supply terminal VSS are shaken, causing malfunction of the entire chip.

Referring to FIG. 1, when the data signal Input is simultaneously connected to the gate terminal of the PMOS transistor P1 driving the pull-up and the gate terminal of the NMOS transistor N1 driving the pull-down, the data when the power supply voltage is 5V. The PMOS transistor P1 and the NMOS transistor N1 are turned on at the same time between the voltage input terminal VDD and the ground power supply terminal VSS in a period of about 1V to 4V. Many leakage currents flow from tens of mA to hundreds of mA.

Therefore, in the case of a whole chip having a plurality of output driving circuits configured as described above, when a large number of output driving circuits are simultaneously transitioned, a large amount of current flows simultaneously in the entire chip, causing the chip to malfunction due to shaking of the power level inside the chip. do.

The present invention has been made to solve the above problems, and eliminates the case where the PMOS transistor and the NMOS transistor are turned on at the same time to eliminate the phenomenon that the current flows directly between the power supply voltage terminal and the ground power supply terminal to eliminate ground bounce noise. The purpose is to provide a reduced output drive circuit.

1 shows an output drive circuit of the simplest structure.

2 illustrates an output drive circuit according to an embodiment of the present invention.

* Description of the main parts of the drawing

100: pull up and pull down drive

120: short pulse generator

140: pull-up node control unit

160: pull down node control unit

The present invention for achieving the above object, in the output drive circuit, pull-up and pull-down driving means consisting of a PMOS transistor and an NMOS transistor to pull up or pull down the output stage, respectively, in response to a voltage level value of a pull-up control node or a pull-down control node. ; A short pulse generating means for receiving data input for output and generating a transition pulse when the data is transitioned; Pull-up node control means for controlling the voltage level value of the pull-up control node in response to the transition pulse and the data output from the short pulse generation means; And pull-down node control means for controlling the voltage level value of the pull-down control node in response to the transition pulse and the data output from the short pulse generating means.

Preferably, the pull-up node control means comprises: first delay means for delaying the data for any predetermined time; First three-phase buffering means for buffering the delayed data output from the first delaying means and outputting the delayed data output from the first delaying means to the first node in response to the transition pulse output from the short pulse generating means; Second three-phase buffering means for buffering a voltage level of a power supply voltage terminal and outputting the buffered voltage level to the first node in response to a transition pulse output from the short pulse generating means; First level holding means for maintaining a level value of the first node; And first buffering means for buffering a level value of the first node and outputting the buffered level value to the pull-up control node, wherein the first and second three-phase buffering means each of the transition pulses output from the short pulse generating means. Enabled at another level, and more preferably, the pull-down node control means comprises: second delay means for delaying the data for any predetermined time; Third three-phase buffering means for buffering the delayed data output from the second delay means and outputting the second data to the second node in response to the transition pulse output from the short pulse generating means; Fourth three-phase buffering means for buffering and outputting the voltage level of the ground power supply terminal to the second node in response to the transition pulse output from the short pulse generating means; Second level holding means for maintaining a level value of the second node; And second buffering means for buffering the level value of the second node and outputting the buffered value to the pull-down control node, wherein the third and fourth three-phase buffering means each of the transition pulses output from the short pulse generating means. It is enabled at another level.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Briefly summarized, the PMOS transistor and the NMOS transistor are configured to be turned off in response to the input data by first turning off both the PMOS transistor and the NMOS transistor for a short time when the input data transitions. It prevents the NMOS transistors from turning on at the same time, eliminating the instantaneous current flowing between the supply voltage and ground power stages, reducing ground bounce noise.

2 is a diagram illustrating an output driving circuit according to an exemplary embodiment of the present invention, in which the output terminal PAD is pulled up or pulled down in response to a voltage level value of a pull-up control node pucn or a pull-down control node pdcn, respectively. A pull-up and pull-down driving unit 100 composed of a PMOS transistor and an NMOS transistor, which receives data input to be output through an output buffer, is short when a data transition occurs, that is, a transition from 0V to 5V or from 5V to 0V. Short pulse generator 120 for generating a transition pulse for a time, pull-up for controlling the voltage level value of the pull-up control node (pucn) in response to the transition pulse and data (Data) output from the short pulse generator 120 A pull-down for controlling a voltage level value of the pull-down control node pdcn in response to a transition pulse and data output from the node controller 140 and the short pulse generator 120. And a pull controller 160, wherein the pull-up node controller 140 includes a delay unit 142 for delaying the data for a predetermined time and a transition pulse output from the short pulse generator 120. In response, the three-phase buffer 144 buffers the delayed data output from the delay unit 142 and outputs the result to the node ND1, and the power supply voltage terminal VDD in response to the transition pulse output from the short pulse generator 120. The three-phase buffer 146 buffers the voltage level of the node ND1 and outputs it to the node ND1, the level maintaining unit 148 for maintaining the level value of the node ND1, and the level value of the node ND1. The buffer 150 is output to the pull-up control node pucn.

In addition, the pull-down node controller 160 may delay the data (Data) for a predetermined time, the delay unit 162, the delay unit 162 in response to the transition pulse output from the short pulse generator 120 The three-phase buffer 166 buffering the delayed data output from the N-S2 output to the node ND2, and buffers the voltage level of the ground power supply terminal VSS in response to the transition pulse output from the short pulse generator 120. The pull-down control node pdcn buffers the three-phase buffer 164 output to the node ND2, the level holding unit 168 for maintaining the level value of the node ND2, and the level value of the node ND2. It consists of a buffer 170 for outputting.

The operation of the output drive circuit configured as described above will be described.

First, the short pulse generator 120 outputs a "high" level transition pulse when the data is transitioned, and the "high" level transition pulse output from the short pulse generator 120 is a three-phase buffer 146. 164 is enabled, respectively, and the power supply voltage level of "high" and the ground voltage level of "low" are output to the nodes ND1 and ND2 through the three-phase buffers 146 and 164, respectively. Subsequently, the "high" power supply voltage level output from the three-phase buffer 146 is transferred to the pull-up control node pucn via the buffer 150 to turn off the PMOS transistors of the pull-up and pull-down driving unit 100, The ground voltage level of the "low" output from the three-phase buffer 164 is transferred to the pull-down control node pdcn through the buffer 170 to turn off the NMOS transistors of the pull-up and pull-down driver 100.

At this time, the level holding units 148 and 168 respectively connected to the nodes ND1 and ND2 are for maintaining respective node level values, and are composed of an inverter having a relatively small driving force and an inverter having a relatively large driving force. This prevents the discharge phenomenon that can occur when the three-phase buffer connected to the node is disabled.

Next, as described above, the PMOS transistor and the NMOS transistor of the pull-up and pull-down driver 100 are both turned off in response to the pulse signal of the short pulse generator 120 when the data is transitioned. When a "low" level pulse signal is output from the 120, the three-phase buffers 144 and 166 are enabled by the "low" level pulse signal, and the original data Data is transferred through the buffers 150 and 170. It is delivered to the pull-up control node (pucn) and pull-down control node (pdcn), respectively. At this time, since the node ND1 and ND2 level values (that is, ND1 is "high" and ND2 are "low") of the previous state are maintained by the inverters having relatively small driving force of the level holding units 148 and 168. It is overwritten by the level value output from the three-phase buffers 144 and 166. Accordingly, the pull-up and pull-down driving unit 100 is driven in response to the original data, and the output terminal PAD responds to the data. Output signal.

As a result, the output driving circuit of the present invention turns on both the PMOS transistor and the NMOS transistor of the pull-up and pull-down driving unit 100 during the transition of the input data in response to the transition pulse output from the short pulse generator 120 as described above. After turning off, when the input data Data is at the "high" level, the pull-down node controller 160 turns on the NMOS transistor to drive the level value of the inverted input data Data to the output terminal PAD. When the input data is at the "low" level, the inverted input data Data is driven to the output terminal PAD by turning on the PMOS transistor through the pull-up node controller 140. Therefore, as in the prior art, the PMOS transistor and the NMOS transistor are simultaneously turned on to remove a current flowing directly between the power supply voltage terminal and the ground power supply terminal.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the PMOS transistor is configured by turning off both the PMOS transistor and the NMOS transistor for a short time at the time when the input data transitions, and then driving the PMOS transistor and the NMOS transistor in response to the input data. By preventing the and NMOS transistors from being turned on at the same time, the ground bounce noise can be reduced by eliminating the current flowing between the supply voltage terminal and the ground supply terminal.

Claims (4)

In the output drive circuit, Pull-up and pull-down driving means each including a PMOS transistor and an NMOS transistor that pull-up or pull-down the output stage in response to a voltage level value of a pull-up control node or a pull-down control node, respectively; A short pulse generating means for receiving data input for output and generating a transition pulse when the data is transitioned; Pull-up node control means for controlling the voltage level value of the pull-up control node in response to the transition pulse and the data output from the short pulse generation means; And Pull-down node control means for controlling the voltage level value of the pull-down control node in response to the transition pulse and the data output from the short pulse generating means; Output drive circuit comprising a. The method of claim 1, wherein the pull-up node control means, First delay means for delaying the data for any predetermined time; First three-phase buffering means for buffering the delayed data output from the first delaying means and outputting the delayed data output from the first delaying means to the first node in response to the transition pulse output from the short pulse generating means; Second three-phase buffering means for buffering a voltage level of a power supply voltage terminal and outputting the buffered voltage level to the first node in response to a transition pulse output from the short pulse generating means; First level holding means for maintaining a level value of the first node; And A first buffering means for buffering and outputting the level value of the first node to the pull-up control node; The first and second three-phase buffering means, And the output driving circuit is enabled at different levels of the transition pulses output from the short pulse generating means. The method of claim 2, wherein the pull-down node control means, Second delay means for delaying the data for any predetermined time; Third three-phase buffering means for buffering the delayed data output from the second delay means and outputting the second data to the second node in response to the transition pulse output from the short pulse generating means; Fourth three-phase buffering means for buffering and outputting the voltage level of the ground power supply terminal to the second node in response to the transition pulse output from the short pulse generating means; Second level holding means for maintaining a level value of the second node; And And second buffering means for buffering the level value of the second node and outputting the buffered value to the pull-down control node. The third and fourth three-phase buffering means, And the output driving circuit is enabled at different levels of the transition pulses output from the short pulse generating means. The method of claim 3, wherein the first and second level holding means, respectively, A first inverter having a relatively small driving force and a second inverter having a relatively large driving force are provided to prevent a discharge phenomenon occurring when all of the three-phase buffering means connected to the corresponding node are disabled. Output driving circuit.