KR100324020B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR100324020B1 KR100324020B1 KR1019980035019A KR19980035019A KR100324020B1 KR 100324020 B1 KR100324020 B1 KR 100324020B1 KR 1019980035019 A KR1019980035019 A KR 1019980035019A KR 19980035019 A KR19980035019 A KR 19980035019A KR 100324020 B1 KR100324020 B1 KR 100324020B1
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- insulating film
- forming
- semiconductor device
- metal wiring
- copper
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 55
- 239000002184 metal Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 230000015572 biosynthetic process Effects 0.000 title abstract 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052802 copper Inorganic materials 0.000 claims abstract description 37
- 239000010949 copper Substances 0.000 claims abstract description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 15
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 2
- 230000001629 suppression Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 3
- 230000002401 inhibitory effect Effects 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 하부물질층 상부에 제1절연막을 형성하는 공정과, 상기 제1절연막 상부에 장벽금속층을 패터닝하는 공정과, 상기 장벽금속층을 노출시키는 홈이 구비된 제2절연막을 전체표면상부에 형성하는 공정과, 상기 제2절연막을 질소가스 분위기하에서 열처리 또는 플라즈마처리하는 공정과, 상기 제2절연막을 구리막 증착 억제층으로 하여 상기 홈을 매립하는 구리막을 형성하는 공정으로 금속배선을 형성함으로써 저항이 낮고 전도율이 우수하여 좁은 폭과 얇은 두께로 금속배선을 형성할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시키며 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, comprising the steps of forming a first insulating film on the lower material layer, patterning a barrier metal layer on the first insulating film, and a groove for exposing the barrier metal layer Forming a provided second insulating film over the entire surface, heat treating or plasma treating the second insulating film under a nitrogen gas atmosphere, and copper filling the groove with the second insulating film serving as a copper film deposition inhibiting layer. It is a technology that enables the formation of metal wiring by forming a metal wiring to form a metal wiring with a narrow width and a thin thickness by improving the characteristics and reliability of the semiconductor device and enabling high integration of the semiconductor device. .
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 구리를 차세대 고집적 반도체소자의 배선 재료로 사용하기 위한 방법으로 메소리 소자 뿐 아니라 고속을 필요로 하는 비메모리 반도체소자에도 적용할 수 있도록 구리배선을 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and in particular, to use copper as a wiring material for next-generation highly integrated semiconductor devices. It relates to a technique for forming a wiring.
일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고 후속공정을 거쳐 이루어지며, 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is made through a subsequent process by filling a predetermined contact hole and via hole for wiring with a wiring material and forming a wiring layer. Metal wiring is used where resistance is required.
상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착 ( Physical Vapor Deposition, 이하에서 PVD 라 함 ) 방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법이 가장 널리 이용되고 있다.The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low resistivity and excellent workability. The method of filling the contact hole and the via hole by sputtering of the method is most widely used.
상기 스퍼터링방법은, 화학기상증착 ( chemical vapor deposition, 이하에서 CVD 라 함 ) 방법에 비하여 저온에서 실시되며 공정이 단순한 장점이 있으나, 단차피복비가 낮아 고집적화된 반도체소자의 제조공정에는 적용하기 어려운 단점이 있다.The sputtering method is performed at a low temperature compared to chemical vapor deposition (CVD), but the process is simple, but it is difficult to be applied to the manufacturing process of highly integrated semiconductor devices due to low step coverage ratio. have.
이를 해결하기 위하여, 단차피복비가 우수한 화학기상증착 ( chemical vapor deposition, 이하에서 CVD 라 함 ) 방법을 사용하게 되었다.In order to solve this problem, chemical vapor deposition (CVD), which has excellent step coverage ratio, is used.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
먼저, 소정의 하부물질층이 구비된 반도체기판(21) 상부에 산화막(23)을 형성하고, 그 상부에 장벽금속층(25)을 일정두께 형성한다. 이때, 상기 장벽금속층(25)은 TiN 으로 형성한다. (도 1a, 도 1b)First, an oxide film 23 is formed on the semiconductor substrate 21 having a predetermined lower material layer, and a barrier metal layer 25 is formed on the upper portion of the semiconductor substrate 21. In this case, the barrier metal layer 25 is formed of TiN. (FIG. 1A, FIG. 1B)
그 다음에, 금속배선마스크를 이용한 식각공정으로 상기 장벽금속층(25)을식각하고, 상기 장벽금속층(25) 표면에 구리막(27)을 선택적으로 증착한다. 이때, 상기 구리막(27)은 MOCVD 방법에 의한 선택적 구리 증착방법으로 형성한다.Next, the barrier metal layer 25 is etched by an etching process using a metal wiring mask, and a copper film 27 is selectively deposited on the barrier metal layer 25. In this case, the copper film 27 is formed by a selective copper deposition method by the MOCVD method.
이때, 상기 구리막(27)은 배선으로 사용할 때 저항을 줄이기 위하여 2000 Å 이상의 두께로 형성하여야 하는데 상기 구리막(27)은 증착시 상측 뿐만아니라 측면으로도 증착되어 고집적화된 서브마이크론 ( sub micron ) 공정에 사용하기가 어렵다.At this time, the copper film 27 should be formed to a thickness of 2000 Å or more in order to reduce the resistance when used as a wiring, the copper film 27 is deposited on the side as well as the upper side during deposition, highly integrated sub micron (sub micron) Difficult to use in process
여기서, 상기 선택적 구리 증착 방법은, 구리의 특성을 활용한 배선법으로 구리를 MOCVD 로 증착할때 도체와 절연체 사이의 성장률이 다르다는 것을 활용한 것이다. 즉, 절연체인 산화막 상부에 건식식각이 가능한 장벽금속층인 TiN 이나 WN 을 증착하고, 패터닝한 후 구리를 MOCVD 방법으로 증착시키면 장벽금속층에서는 구리의 성장이 빠르게 일어나고 절연체 위에서는 구리의 성장이 늦으므로 장벽금속층과 동일한 패턴을 얻을 수 있다.(도 1c, 도 1d)Here, the selective copper deposition method utilizes a difference in growth rate between the conductor and the insulator when the copper is deposited by MOCVD using a wiring method utilizing the characteristics of copper. In other words, if TiN or WN, which is a dry-etchable barrier metal layer, is deposited on the oxide layer as an insulator, and then copper is deposited by MOCVD method, the growth of copper occurs quickly in the barrier metal layer and the growth of copper on the insulator is slow. The same pattern as the metal layer can be obtained. (FIGS. 1C and 1D).
상기한 바와같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 고집적화된 반도체소자 상부에 선택적 구리 증착방법을 이용하여 금속배선을 형성하는데 있어서, 구리막의 증착시 상측뿐아니라 측면으로도 증착되어 서브마이크론 크기의 미세 금속배선을 형성하면 금속배선의 패터닝이 어렵게 되어 그에 따른 반도체 소자의 고집적화를 어렵게 하고 반도체소자의 특성 및 신뢰성을 저하시킬 수 있는 문제점이 있다.As described above, the metal wiring forming method of the semiconductor device according to the related art is formed on the highly integrated semiconductor device by using a selective copper deposition method, which is deposited not only on the upper side but also on the side when the copper film is deposited. Forming a micron-sized fine metal wire makes it difficult to pattern the metal wire, thereby making it difficult to achieve high integration of the semiconductor device and deteriorating the characteristics and reliability of the semiconductor device.
참고로, 구리의 선택적 증착 특성을 높이기 위한 방법으로는 고온 열처리, 질소 플라즈마 처리 또는 DMDCS ( dimethyldiclorosilane ) 을 이용하는 방법등이있으나, 구리막의 증착시 상측뿐아니라 측면으로도 증착되어 미세패턴의 형성을 어렵게 하는 문제점이 있다.For reference, methods for enhancing the selective deposition characteristics of copper include high temperature heat treatment, nitrogen plasma treatment, or dimethyldiclorosilane (DMDCS). There is a problem.
본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 구리막이 형성될 부분의 절연막을 노출시키는 홈을 형성하고 상기 홈에 구리막을 선택 증착하여 구리막의 측면 증착을 억제함으로써 반도체소자의 고속화 및 고집적화에 충분한 금속배선을 형성할 수 있도록 하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the related art, the present invention provides a groove for exposing an insulating film of a portion where a copper film is to be formed, and selects and deposits a copper film on the groove to suppress sidewall deposition of the copper film. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device that can form a sufficient metal wiring.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2c 는 본 발명의 실시예에 반도체소자의 금속배선 형성방법을 도시한 단면도.2A to 2C are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device in an embodiment of the present invention.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11,21 : 반도체기판 13,23 : 제1산화막11,21: semiconductor substrate 13,23: first oxide film
15,25 : 장벽금속층 17 : 제2산화막15,25 barrier metal layer 17 second oxide film
19,27 : 구리막19,27: copper film
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,
하부물질층 상부에 제1절연막을 형성하는 공정과,Forming a first insulating film on the lower material layer;
상기 제1절연막 상부에 금속배선 마스크를 이용한 사진식각공정으로 장벽금속층 패턴을 형성하는 공정과,Forming a barrier metal layer pattern on the first insulating layer by a photolithography process using a metal wiring mask;
전체표면상부에 상기 장벽금속층패턴을 노출시키는 홈을 형성하는 공정과,Forming a groove exposing the barrier metal layer pattern on an entire surface thereof;
상기 제2절연막을 질소가스 분위기하에서 열처리 또는 플라즈마처리하는 공정과,Heat treating or plasma treating the second insulating film under a nitrogen gas atmosphere;
상기 장벽금속층패턴 상에 상기 홈을 매립하는 구리막을 선택증착하되, 상기 제2절연막을 구리막의 측면 증착 억제층으로 하여 실시하는 공정을 포함하는 것을 특징으로한다.And selectively depositing a copper film filling the groove on the barrier metal layer pattern, and using the second insulating film as a side deposition inhibiting layer of the copper film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A through 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
먼저, 하부구조물이 형성된 반도체기판(11) 상부에 제1산화막(13)을 형성하고 그 상부에 TiN 으로 장벽금속층(15)을 패터닝하여 장벽금속층(15)패턴을 형성한다. 이때, 상기 장벽금속층(15)패턴은 금속배선 마스크(도시안됨)를 이용한 식각공정으로 형성한다.First, the first oxide film 13 is formed on the semiconductor substrate 11 on which the lower structure is formed, and the barrier metal layer 15 is patterned by TiN on the upper portion thereof to form the barrier metal layer 15 pattern. In this case, the barrier metal layer 15 pattern is formed by an etching process using a metal wiring mask (not shown).
그리고, 상기 장벽금속층(15)패턴을 완전히 도포할 수 있도록 전체표면상부에 제2산화막(17)을 두껍게 형성하고 이를 평탄화시킨다. (도 2a)In addition, the second oxide film 17 is thickly formed on the entire surface of the barrier metal layer 15 so as to be completely coated and planarized. (FIG. 2A)
그 다음에, 금속배선 마스크를 이용한 식각공정으로 상기 제2산화막(17)을 식각하여 상기 장벽금속층(15)패턴을 노출시키는 홈을 형성한다. (도 2b)Next, the second oxide layer 17 is etched by an etching process using a metal wiring mask to form a groove exposing the barrier metal layer 15 pattern. (FIG. 2B)
그리고, 질소가스 분위기하에서 열처리 또는 플라즈마처리하여 상기 제2산화막(17) 상부에는 구리막의 증착이 일어나지 않도록 한다.Then, heat treatment or plasma treatment is performed in a nitrogen gas atmosphere to prevent deposition of a copper film on the second oxide film 17.
그리고, MOCVD 를 이용한 선택적 구리 증착방법으로 상기 장벽금속층(15) 패턴에 콘택되는 구리막(19)을 형성한다. 이때, 상기 구리막(19)은 상기 장벽금속층 (15)패턴에 우선적으로 선택증착된다. 이때, 상기 제2산화막(17)은 상기 구리막 (19)의 증착공정시 측면 성장, 즉 측면 증착되는 것을 방지하는 역할을 한다. (도 2c)In addition, a copper film 19 contacting the barrier metal layer 15 pattern is formed by a selective copper deposition method using MOCVD. At this time, the copper film 19 is preferentially deposited on the barrier metal layer 15 pattern. In this case, the second oxide layer 17 prevents side growth, that is, side deposition, during the deposition process of the copper layer 19. (FIG. 2C)
여기서, 상기 하부구조물이 형성된 반도체기판(11)은, 상기 반도체기판(11)이나 기타 다른 물질층으로 대신할 수 있다.Here, the semiconductor substrate 11 on which the substructure is formed may be replaced by the semiconductor substrate 11 or another material layer.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 장벽금속층을 금속배선마스크로 패터닝하여 장벽금속층패턴을 형성하고 상기 장벽금속층패턴을 노출시키는 홈을 갖는 절연막을 형성한 다음, 상기 홈 내부의 장벽 금속층패턴 상에 선택적 구리 증착방법으로 구리막을 선택 증착함으로써 장벽 금속층패턴과 구리막의 적층구조 금속배선을 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고속화 및 고집적화를 가능하게 하는 효과가 있다. 여기서, 상기 절연막이 구리막의 측면 증착을 억제한다.As described above, in the method of forming a metal wiring of the semiconductor device according to the present invention, the barrier metal layer is patterned with a metal wiring mask to form a barrier metal layer pattern and to form an insulating film having grooves exposing the barrier metal layer pattern. By selectively depositing a copper film on the barrier metal layer pattern inside the groove by forming a stacked structure metal wiring of the barrier metal layer pattern and the copper film, it is possible to improve the characteristics and reliability of the semiconductor device, thereby increasing the speed and high integration of the semiconductor device. It's effective. Here, the insulating film suppresses side deposition of the copper film.
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