KR100213242B1 - Method for analgzing external synchronous signal and apparatus therefor - Google Patents

Abstract

The present invention relates to a method for analyzing the presence or absence of an external synchronization signal, a pulse width and a polarity for generating a video signal synchronized with an input external synchronization signal, and a device suitable therefor. Synchronization signal analysis method for generating and outputting a short pulse (SHORT), when rising and falling of the input external synchronization signal; Selecting one of rising and falling short pulses output from the step; And using a short pulse selected by the selecting step as an interrupt request signal IRQ, storing a predetermined counter value in a predetermined data register.

Therefore, the method for analyzing an external synchronization signal and a device suitable therefor according to the present invention have the effect of reducing the burden of software and speeding up the processing speed by converting the conventional software process into a hardware process.

Description

Method for analyzing external synchronous signal and suitable device therefor {Method for analgzing external synchronous signal and apparatus therefor}

The present invention relates to a method for analyzing an external synchronization signal and a device suitable therefor, and more particularly, to a method for analyzing the presence, the pulse width, and the polarity of an external synchronization signal for generating a video signal synchronized with an input external synchronization signal. And a device suitable for the same.

When editing a graphic screen created by the graphics controller to overlay a picture of a television signal or other video signal (a function of overlapping another screen on the screen), the graphics system synchronizes the video signal with the synchronization signal of the screen to be overlaid. Must be created.

At this time, the graphic controller should determine the presence and the polarity of the external vertical synchronization signal and the horizontal synchronization signal.

In the related art, the video signal overlay function is performed by utilizing each register of the graphic controller in a state in which information for determining the presence and absence of an external vertical synchronization signal and a horizontal synchronization signal and polarity is obtained in advance.

However, such a conventional technology has a disadvantage in that the software burden is large and slow because it is processed in software.

SUMMARY OF THE INVENTION The present invention has been made to solve at least some of the above-described problems, and provides a method for analyzing the presence, the pulse width, and the polarity of an external synchronization signal for generating a video signal synchronized with an input external synchronization signal. Another object is to provide an apparatus suitable for the purpose.

1 is a schematic diagram illustrating a graphics system for performing a general overlay function.

2 is a view showing a detailed configuration of a graphic controller according to the present invention.

3 is a view showing a waveform of the composite synchronization signal HVSYNC.

Synchronization signal analysis method for performing the overlay function using the external synchronization signal according to the present invention to achieve the above object (a) when the input and the external synchronization signal rising and falling, generating a short pulse (SHORT) to output step; (b) selecting one of the rising and falling short pulses output from the step; (c) storing a predetermined counter value in a predetermined data register by utilizing the short pulse selected by the selecting step as an interrupt request signal IRQ; And (d) repeating steps (a) to (c) to obtain a difference between the counter values stored in the data register, and if the count value is constant, it is determined that a synchronization signal exists and The pulse width is extracted by multiplying the difference of the counter value by a period, and the counter value is obtained for every edge signal of the external synchronization signal, and then the rising edge is compared by comparing counter values of rising edge to falling edge and falling edge to rising edge. It is preferable to include the step of determining the negative polarity if the length of the falling edge is large, and the determination of the positive polarity if the time between the falling edge and the rising edge is large.

Synchronization signal analysis apparatus for performing an overlay function using an external synchronization signal according to the present invention to achieve the above another object is an edge detector for generating and outputting a short pulse (SHORT) when the external synchronization signal is rising and falling ; A selector for selecting and outputting one of the rising and falling short pulses output from the edge detector; A tri-state gate which stores the value of the counter in a data register by using the short pulse output from the selector as an interrupt request signal IRQ; And obtaining a difference between the counter values stored in the data register, determining that a synchronization signal exists if the value is constant, extracting a pulse width by multiplying the difference of the counter value by the period of the counter, and extracting the external synchronization signal. After the counter value is obtained for each edge signal, the counter value of rising edge vs. falling edge and falling edge vs. rising edge is compared. It is preferable to include a microprocessor that determines that the polarity of the positive time is large.

In the present invention, when the input external synchronization signal is a complex type, it further comprises an up-down counter for extracting the vertical synchronization signal.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

1 is a schematic diagram illustrating a graphics system for performing a general overlay function.

The apparatus shown in FIG. 1 outputs an external graphics system 10 that outputs a synchronization signal of an RG B signal and an RG B signal, and an RB G signal synchronized with a synchronization signal output from the external graphics system 10 only at an overlay point. Video R, G, and B switches 14 and a graphics system for selecting and outputting one of an RB G signal output from the graphics controller 12, the graphics controller 12, and an RG B signal output from the graphics system 10 ( The multiplexer 16 for selecting and outputting the synchronous signal outputted from 10) and the synchronous signal outputted from the graphics controller 12, and the RG B signal outputted from the video RG B switch 14 and the synchronization outputted from the multiplexer 16. The cathode ray tube 18 is displayed by superimposing the image output from the graphics controller 12 on the image output from the graphics system 10 by a signal.

Next, the operation of the apparatus shown in FIG. 1 will be described.

In order to perform the function of the video overlay, the graphics controller 12 inputs an external synchronization signal and outputs the R. G. B signal synchronized with the video R. G. B switch 14 to the video synchronization signal.

At the overlay point of the image, the video RG B switch 14 outputs the video RG B signal output from the graphics controller 12 to the cathode ray tube 18, and the screen of the cathode ray tube 18 is displayed on the screen of the external graphics system 10. The image of the graphics controller 12 is synchronized and overlaid on the image.

Of course, beyond the overlay point, the video R. G. B switch 14 outputs the R. G. B signal of the external graphics system 10.

Here, the graphics controller 12 needs to analyze the synchronization signal of the external graphics system 10. First, it is necessary to determine the existence of the vertical and horizontal synchronization signals, analyze the polarity thereof, and extract the pulse widths of the horizontal and vertical synchronization signals.

2 is a diagram showing a detailed configuration of a graphic controller according to the present invention, and shows a detailed configuration of the graphic controller shown in FIG.

The apparatus shown in FIG. 2 separates the vertical synchronizing signal from the hybrid synchronizing signal HVSYNC shown in FIG. 3 and horizontally synchronizes the circuit unit 200 to determine the presence or absence of the vertical synchronizing signal, polarity determination, and pulse width. And a microprocessor 400 for analyzing the presence or absence of a signal, polarity determination, and pulse width, and analyzing a synchronization signal output from the circuit units 200 and 300.

Here, the type of the composite synchronization signal HVSYNC may be in the form of a synchronization signal including a horizontal synchronization signal or a vertical synchronization signal.

First, looking at the configuration of the circuit unit 200 for determining the presence or absence of the vertical synchronization signal, polarity determination and pulse width, the up / down counter 20 for separating the vertical synchronization signal from the composite synchronization signal, the up / down counter ( 20 is output from the first selector 21 and the first selector 21 for selecting and outputting either the second vertical synchronous signal VSYNCI 'or the first vertical synchronous signal VSYNCI which is input alone. When the vertical synchronization signal rises and falls, a first edge detector 22 that generates and outputs a short pulse and a first pulse that selects and outputs one of the short pulses of the rising or falling output from the edge detector 22. 3- which stores the value of the first counter 24 in the first data register 26 according to the interrupt request signal IRQ1 generated by the short selector 23 output from the second selector 23 and the second selector 23. It consists of a tri-state gate 25.

In addition, referring to the configuration of the circuit unit 300 for determining the presence or absence of the horizontal synchronization signal, the pulse width and the polarity, a second pulse for generating and outputting a short pulse when the horizontal composite synchronization signal is raised and lowered is inputted. The short pulse output from the third selector 33 and the third selector 33 to select and output one of the short pulses at the time of rising or falling output from the edge detector 32 and the second edge detector 32. The tri-state gate 35 stores the value of the second counter 34 in the second data register 36 by the generated second interrupt request signal IRQ2.

Next, a method for determining the presence, the pulse width, and the polarity of the vertical / horizontal synchronization signal will be described with reference to the drawing shown in FIG. 2.

First, a method of determining the presence or absence of the vertical synchronization signal, extracting the pulse width, and determining the polarity will be described.

The first selector 21 selects the first vertical synchronization signal VSYNCI, which is input alone, and the first edge detector 22 generates a short pulse generated when the inputted first vertical synchronization signal is raised or lowered. Output it.

The second selector 23 selects one of the short pulses output from the first edge detector 22. This selected signal is an interrupt request signal IRQ1, which, when input to the tri-state gate 25, stores the value of the first counter 24 in the first data register 26.

As a result of repeating this operation several times, the microprocessor 400 obtains the difference between the values stored in the first data register 26. If the value is always constant, the existence of the vertical synchronization signal is proved, and the first counter ( The pulse width is obtained by multiplying the difference of the values stored in the period of 24).

In addition, the microprocessor 400 detects the edge signal from the vertical synchronization signal, obtains the value of the first counter for each edge, and then compares the counter value of rising edge vs. falling edge and falling edge vs. rising edge to rise edge vs. falling edge. If the edge length is large, it is determined as negative polarity. If the time between the falling edge and rising edge is large, it is determined as positive polarity.

In addition, a method of determining the presence or absence of the horizontal synchronization signal, extracting the pulse width, and determining the polarity will be described as follows.

The second edge detector 32 generates and outputs a short pulse generated when the input horizontal synchronization signal rises or falls.

The third selector 33 selects one of the short pulses output from the second edge detector 32. This selected signal is an interrupt request signal IRQ2, which, when input to the tri-state gate 35, stores the value of the second counter 34 in the second data register 36.

As a result of repeating this operation several times, the microprocessor 400 obtains the difference between the values stored in the second data register 36, and if the value is always constant, the existence of the horizontal synchronization signal is proved, and the second counter ( The pulse width is obtained by multiplying the difference of the values stored in the cycle of 34).

In addition, the microprocessor 400 detects the edge signal from the horizontal synchronization signal to obtain the value of the second counter for each edge, and then compares the counter values of the rising edge to the falling edge and the falling edge to the rising edge, and then the rising edge to falling edge. If the edge length is large, it is determined as negative polarity. If the time between the falling edge and rising edge is large, it is determined as positive polarity.

In addition, when the composite synchronous signal is a combination of a horizontal synchronous signal and a vertical synchronous signal, the vertical synchronous signal is extracted by using the up-down counter 20. The composite synchronous signal is used as an up / down signal of the up / down counter. When the composite sync signal is high, the up / down counter is incremented and decremented when it is low. At this time, when all of the counters reach the high state, the high state is maintained in the second vertical synchronization signal VSYNC ', and when the counters reach the low state, the low state is maintained.

Here, since the composite synchronization signal section is shorter than the vertical synchronization signal section, even if a high or low value is input to the up / down counter in the composite synchronization signal section, the counter values cannot all be controlled to be high or all low. For this reason, the value of the second vertical synchronization signal VYSNC 'cannot be changed. However, when the up / down counters are all high or all low, the up / down signal should be kept high or all low even if the up / down signals continue to occur.

As described above, the method for analyzing an external synchronization signal and a device suitable therefor according to the present invention have the effect of reducing the burden of software and speeding up the processing speed by converting the conventional software process into a hardware process.

Claims (3)

In the synchronization signal analysis method for performing an overlay function using an external synchronization signal, (a) generating and outputting a short pulse (SHORT) when the input external synchronization signal rises and falls; (b) selecting one of the rising and falling short pulses output from the step; (c) storing a predetermined counter value in a predetermined data register by utilizing the short pulse selected by the selecting step as an interrupt request signal IRQ; And (d) Repeating steps (a) to (c) to obtain a difference between the counter values stored in the data register, and if the count value is constant, it is determined that a synchronization signal exists and the period of the counter The pulse width is extracted by multiplying the difference between the counter values, and the counter value is obtained for every edge signal of the external synchronization signal. Then, the counter values of rising edge vs. falling edge and falling edge vs. rising edge are compared. Determining the polarity of the negative when the length of the falling edge is large, and determining the positive polarity when the time between the falling edge and the rising edge is large. In the sync signal analysis apparatus for performing an overlay function using an external sync signal, An edge detector generating and outputting a short pulse when the external synchronization signal is raised and lowered; A selector for selecting and outputting one of the rising and falling short pulses output from the edge detector; A tri-state gate which stores the value of the counter in a data register by using the short pulse output from the selector as an interrupt request signal IRQ; And The difference between the counter value stored in the data register is obtained, and if the value is constant, it is determined that there is a synchronization signal, the period of the counter is multiplied by the difference of the counter value to extract a pulse width, After calculating the counter value for each edge signal, compare the counter value of rising edge to falling edge and falling edge to rising edge, and if the length of rising edge to falling edge is large, it is determined as negative polarity And a microprocessor for determining that the polarity is positive when the time is large. The apparatus of claim 2, further comprising an up-down counter for extracting a vertical synchronization signal when the input external synchronization signal is a complex type.