KR0167141B1 - Semiconductor package - Google Patents
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- KR0167141B1 KR0167141B1 KR1019940039354A KR19940039354A KR0167141B1 KR 0167141 B1 KR0167141 B1 KR 0167141B1 KR 1019940039354 A KR1019940039354 A KR 1019940039354A KR 19940039354 A KR19940039354 A KR 19940039354A KR 0167141 B1 KR0167141 B1 KR 0167141B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/181—Encapsulation
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- Condensed Matter Physics & Semiconductors (AREA)
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- Engineering & Computer Science (AREA)
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Abstract
본 발명은 반도체 패키지[비.지.에이 반도체 패키지(1), 시.오.비 반도체 패키지(1A), 수퍼 비지에이 반도체 패키지(1B)]에 관한 것으로서, PCB 및 세라믹기판(8) 상부의 서브스트레이트에 직접 본딩된 반도체 패키지[비.지.에이 반도체(1), 시.오.비 반도체 패키지(1A), 수퍼 비지에이 반도채패키지(1B)]의 C4 또는 플립칩다이로된 반도체칩(5)을 열전도성이 양호한 애디히시브에폭시(7)로 열방출수단의 메탈캡(2)이나 메탈플레이트(3)에 직접 접착시키므로서, 반도체 패키지(1)의 작동중 반도체칩의 회로에서 발생하는 열을 에폭시와 열방출수단을 통해 외부로 용이하게 방출시킬 수 있도록 하여 고집적화된 반도체 패키지의 회로적 기능동작을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package (B.G.A. semiconductor package 1, C.O.B. semiconductor package 1A, super BG semiconductor package 1B), A semiconductor chip made of C4 or flip chip die of a semiconductor package (B.G.A semiconductor 1, S.O.B semiconductor package 1A, super BG semiconductor package 1B) bonded directly to the substrate (5) is directly bonded to the metal cap (2) or the metal plate (3) of the heat dissipation means by an additive epoxy (7) having good thermal conductivity, so that in the circuit of the semiconductor chip during operation of the semiconductor package (1) The generated heat can be easily released to the outside through the epoxy and the heat dissipation means, thereby improving the circuit functional operation of the highly integrated semiconductor package.
Description
제1도는 본 발명의 반도체 패키지에 적용되는 열방출수단인 메탈캡 구조도.1 is a metal cap structure diagram of heat dissipation means applied to a semiconductor package of the present invention.
제2도는 본 발명의 비.지.에이(B.G.A) 반도체칩이 에폭시로 열방출수단인 메탈캡에 접착된상태의 구조도.2 is a structural diagram of a B.G.A semiconductor chip of the present invention bonded to a metal cap which is a heat-releasing means by epoxy.
제3도는 본 발명의 비.지.에이 반도체 패키지의 구성도.3 is a configuration diagram of the B.A. semiconductor package of the present invention.
제4도는 본 발명의 다른 실시예의 열방출수단인 메탈플레이트에 비.지.에이 반도체칩이 에폭시로 접착된 상태의 구성도.4 is a block diagram of a B.A. semiconductor chip bonded to an epoxy on a metal plate which is a heat dissipation means according to another embodiment of the present invention.
제5도는 본 발명의 다른 실시예의 비.지.에이 반도체 패키지의 반도체칩 외부에 언더필메타리얼이 충진된 상태의 구조도.5 is a structural diagram of an underfill material filled in a semiconductor chip of a BG semiconductor package according to another embodiment of the present invention.
제6도는 본 발명의 열방출수단인 메탈캡의 다른 실시예 구성도.Figure 6 is another embodiment configuration of the metal cap which is a heat dissipation means of the present invention.
제7도는 본 발명의 열방출수단인 메탈캡의 또 다른 실시예 구성도.Figure 7 is another embodiment configuration of the metal cap which is a heat dissipation means of the present invention.
제8도는 본 발명의 열방출수단인 메탈플레이트의 다른 실시예 구성도.8 is another embodiment of the metal plate which is the heat dissipation means of the present invention.
제9도는 본 발명의 다른 실시예의 비.지.에이 반도체 피키지의 구조도로서, 언더필메타리얼과 글럽탑메타리얼이 충진된 상태도.9 is a structural diagram of a B.G semiconductor package according to another embodiment of the present invention, in which an underfill material and a glove top material are filled.
제10도는 본 발명의 또 다른 실시예의 비.지.에이 반도체 패키지의 구조도로서, 열방출수단이 방열핀으로 형성된 것.FIG. 10 is a structural diagram of a B. G semiconductor package according to another embodiment of the present invention, wherein the heat dissipation means is formed of heat dissipation fins.
제11도는 시.오.비(C.O.B)반도체 패키지의 일반적인 구성도.11 is a general configuration diagram of a C.O.B semiconductor package.
제12도는 수퍼 비.지.에이 반도체 패키지의 일반적인 구성도.12 is a general configuration diagram of a super B.A semiconductor package.
제13도는 일반적인 종래의 비.지.에이 반도체 패키지의 구성도로서, 컴파운드재로 패키지몰드된 상태도.13 is a configuration diagram of a conventional B.A. semiconductor package, which is packaged with a compound material.
제14도는 종래의 일반적인 열방출수단인 메탈캡이 씌워진 상태의 비.지.에이 반도체 패키지의 구성도.14 is a block diagram of a B.G semiconductor package in a state in which a metal cap, which is a conventional heat dissipation means, is covered.
제15도는 종래의 일반적인 다른 실시예의 C4 또는 플립칩다이로 구비된 반도체칩의 구성도.15 is a configuration diagram of a semiconductor chip provided with a C4 or flip chip die according to another conventional general embodiment.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 비.지.에이 반도체 패키지 1A : 시.오.비 반도체 패키지1: B.G.A semiconductor package 1A: C.O.non-semiconductor package
1B : 수퍼비.지.에이 반도체 패키지 2 : 열방출수단인 메탈캡1B: Super B.A semiconductor package 2: Metal cap for heat dissipation means
3 : 열방출수단인 메탈플레이트 4 : 구멍3: metal plate as a heat dissipation means 4: hole
5 : 반도체칩 6 : 범프5 semiconductor chip 6 bump
7 : 에폭시 8 : PCB 및 세라믹기판7: epoxy 8: PCB and ceramic substrate
9 : 언더필메타리얼(UNDER FILL MATERIAL)9: UNDER FILL MATERIAL
10 : 글럽탑메타리얼(GLOB TOP MATERIAL)10: GLOB TOP MATERIAL
11 : 핀타입(FIN TYPE)열방출수단 11A : 방열핀11: Fin type heat dissipation means 11A: Heat dissipation fin
본 발명은 반도채 패키지에 관한 것으로서, 특히 PCB(Printed Circuit Board)및 세라믹기판이 적용되는 반도체 패키지 [비.지.에이(BALL GRID ARRAY)반도체 패키지와, 시.오.비(CHIP ON BOARD)반도체 패키지와, 수퍼 비.지.에이(SUPER B.G.A)반도체 패키지]의 C4 (컨트롤즈 컬랩스 칩 캐리어: CONTROLLED COLLAPSE CHIP CARRIER), 또는 플립칩다이(FLIP CHIP)로 된 반도체칩에 구비된 범프(BUMP)가 열방출수단인 메탈켑(METAL CAP)이나 메탈플레이트(METAL PLATE)의 반대방향으로 위치되도록 에디히시브에폭시(ADHESIVE EPOXY)및 폴리마이드에폭시(POLYMIDE)로 반도체칩을 접착하여 반도체칩의 본딩패드를 PCB나 세라믹시판의 서브스트레이트(SUBSTRATE)에 직접 본딩할 수 있도록 한 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor package, and in particular, a semiconductor package to which a printed circuit board (PCB) and a ceramic substrate are applied [BALL GRID ARRAY semiconductor package and a chip on board]. Semiconductor package and SUPER BGA Semiconductor Package] C4 (Controls Collabs Chip Carrier), or bumps on semiconductor chips made of flip chip die BUMP is bonded to the semiconductor chip by ADHESIVE EPOXY and POLYMIDE so that the BUMP is located in the opposite direction of the metal CAP or METAL PLATE. The present invention relates to a semiconductor package capable of bonding a bonding pad directly to a substrate or a substrate of a ceramic substrate.
일반적으로 PCB 및 세라믹기판(8)상에 안치되는 반도체 패키지[비.지.에이 반도체 패키지(1), 시.오.비 반도체 패키지(1A), 수퍼 비.지.에이 반도체 패키지(IB)]의 반도체칩(5)은 첨부된 도면 제11도에서 제15도에 도시된 바와 같이 PCB 및 세라믹기판(8)에 에폭시(7)로 접착된 반도체칩(5)의 본딩패드와 기판(8)의 회로를 금선이나 알루미늄선으로된 와이어(W)을 이용하여 상호 연결시키고, 반도체칩(5)과 내부회로를 보호하기 위하여 반도체칩(5)의 외부에 컴파운드몰드재인 패키지(P)를 성형시키거나 메탈캡(2)을 씌워 반도체 패키지(1)를 제조하였으나, 차세대 반도체 패키지(1)의 제조에 있어 고집적화된 제품이 요구됨에 따라 반도체 패키지[비.지.에이 반도체 패키지(1), 시.오.비 반도체 패키지(1A), 수퍼 비.지.에이(1B)]의 C4 [컨트롤즈 컬랩스 칩 캐리어(CONTROLLED COLLAPSE CHIP CARRIER: 반도체칩의 인출패드위에 금속으로 볼을 형성)], 또는 플립칩다이[FLIP CHIP: PCB에 직접 칩을 페이스다운(FACE DOWN)형태로 붙이는 방법으로서 본딩패드(BONDING PAD)상에 범프(BUMP)를 형성하여 와이어본딩까지 완료시키는 것]로된 반도체칩을 PCB나 세라믹기판(8)의 서브스트레이트(SUBSTRATE: 위에 소자, 회로 및 에피층이 만들어지는 원판)에 직접 반도체칩을 본딩할 수 있도록 하므로서, 반도체칩의 본딩패드의 배치를 칩의 가장자리주변에서 에어리어어레이(AREA ARRAY)방식으로 할 수 있고, 본딩패드 간의 간격을 최대한 줄일 수 있어 반도체칩의 단위 면적당 집적도를 향상시킬 수 있도록 하며, 반도체칩의 사이즈를 줄일 수 있도록 한 반도체 패키지가 개발되었다.Generally, semiconductor packages placed on PCBs and ceramic substrates 8 [B.G.A semiconductor packages 1, S.O.B semiconductor packages 1A, super B.A. semiconductor packages IB] The semiconductor chip 5 of FIG. 11 is a bonding pad and a substrate 8 of the semiconductor chip 5 bonded to the PCB and the ceramic substrate 8 with an epoxy 7 as shown in FIGS. 11 to 15. Circuits are interconnected by wires made of gold or aluminum wires, and a package P, which is a compound molding material, is formed on the outside of the semiconductor chip 5 to protect the semiconductor chip 5 and the internal circuits. In addition, the semiconductor package 1 is manufactured by covering the metal cap 2, but as a highly integrated product is required in the manufacture of the next-generation semiconductor package 1, the semiconductor package [B.G.A. CONTROLLED COLLAPS C4 CONTROLLED COLLAPS OF O.N Semiconductor Package (1A), SUPER B.G.A (1B)] E CHIP CARRIER: Metal ball on the extraction pad of semiconductor chip)], or flip chip die [FLIP CHIP: The method of attaching the chip directly to the PCB in the form of face down, on the bonding pad. Bonding the semiconductor chip directly to the substrate (SUBSTRATE) of the PCB or the ceramic substrate 8, which forms a bump and completes wire bonding. In this way, the bonding pads of the semiconductor chip can be arranged in an area array around the edge of the chip, and the spacing between the bonding pads can be reduced as much as possible to improve the integration density per unit area of the semiconductor chip. In addition, a semiconductor package has been developed to reduce the size of the semiconductor chip.
그런, 종래의 C4 및 플립칩다이로 된 반도체칩(5)을 이용한 반도체 패키지는 도시된 도면 제15도에 도시된 바와 같이 반도체칩(5)의 하부면에 구비된 범프(6)가 PCB 또는 세라믹기판(8)에 접촉되어 직접 본딩되도록 하고, 반도체칩(5)과 내부의 회로를 보호하기 위하여 반도체칩(5) 외부에 메탈칩(2)을 쒸우거나 합성수지컴파운드재로 패키지(P)몰딩하므로 인하여 반도체 패키지(1)의 고속작동시 반도체칩(5)의 고집적도에 의하여 발생하는 열이 메탈캡(2)과 패키지(P)에 의해 외부로 방출되는 열이 저항을 받아 용이하게 방출되지 못하므로서, 반도체칩(5)이 열적스트레스받아 회로적작동기능이 원활하게 발휘되지 못하는 문제점이 있었다.In the semiconductor package using the semiconductor chip 5 of the conventional C4 and flip chip die, the bump 6 provided on the lower surface of the semiconductor chip 5 may be a PCB or the like. In order to contact the ceramic substrate 8 to be directly bonded, and to protect the semiconductor chip 5 and the internal circuits, the metal chip 2 is embedded outside the semiconductor chip 5 or the package P is molded of a synthetic resin material. Therefore, the heat generated by the high integration of the semiconductor chip 5 during the high-speed operation of the semiconductor package 1 is not easily released due to the resistance of heat released to the outside by the metal cap 2 and the package P. There is a problem that the semiconductor chip 5 is thermally stressed and the circuit operation function is not exhibited smoothly.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 발명한 것으로서, PCB 및 세라믹기판 상부의 서브스트레이트에 반도체칩의 C4(컨트롤즈 컬랩스 칩 캐리어)또는 플립칩다이가 직접 본딩되는 반도체 패키지[비.지.에이 반도체, 시.오.비 반도체 패키지, 수퍼 비.지.에이 반도체]에 있어, 상기한 반도체칩의 상부에 열방출수단인 평면상의 메탈플레이트를 애폭시(전기적으로 비전도성이고, 열적전도성이 양호한 것)로 직접 부착하여 반도체 패키지의 작동중 반도체칩의 회로에서 발생하는 열을 외부로 용이하게 방출시킬 수 있도록 함은 물론, 상기한 반도체칩의 외부에는 언더필메타리얼을 충진시켜 반도체칩의 외부 노출을 방지하고, 각 구성 부품의 스트레스를 방지하며, 반도체칩과 열방출수단을 견고하게 고정시킬 수 있도록 한 것을 목적으로 한다.Accordingly, the present invention is invented to solve the above conventional problems, a semiconductor package in which C4 (controls collapsing chip carrier) or flip chip die of the semiconductor chip is directly bonded to the substrate on the PCB and the ceramic substrate. In [B.G.A semiconductor, S.O.B. semiconductor package, super B.A. semiconductor], a planar metal plate, which is a heat dissipation means, is epoxy-deposited on the upper part of the semiconductor chip. And heat transfer from the semiconductor chip during the operation of the semiconductor package to the outside, and the underfill material is filled in the outside of the semiconductor chip. To prevent external exposure of the semiconductor chip, to prevent stress of each component, and to securely fix the semiconductor chip and the heat dissipation means. Do as an enemy.
이하, 첨부된 도면에 의하여 본발명을 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
PCB 및 세라믹기판(8) 상부의 서브스트레이트에 직접 본딩된 반도체 패키지[비.지.에이 반도체 패키지(1), 시.오.비 반도체 패키지(1A), 수퍼 비.지.에이 반도체 패키지(1B)]의 C4 또는 플립칩다이로된 반도체칩(5)과 내부의 구성회로들을 보호하기 위하여 반도체칩(5)의 외부에 쒸워지는 열방출수단에 반도체칩(5)을 에폭시(7)로 직접 접착시키므로서, 고집적화된 반도체칩(5)의 고속작동시 회로에서 발생하는 열이 에폭시(7)와 열방출수단을 통해 외부로 용이하게 방출될 수 있도록 한 것이다.Semiconductor packages directly bonded to the substrate on the PCB and the ceramic substrate 8 [B.G.A semiconductor package 1, S.O.B semiconductor package 1A, Super B.G.A semiconductor package 1B C4 or flip chip die of the semiconductor chip 5 and the internal circuits to protect the internal circuits, the semiconductor chip 5 directly to the epoxy (7) to heat dissipation means outside the semiconductor chip (5) By bonding, the heat generated in the circuit during high-speed operation of the highly integrated semiconductor chip 5 can be easily released to the outside through the epoxy 7 and the heat dissipation means.
상기한 C4, 또는 플립칩다이로 되어진 반도체칩(5)과 에폭시(7)로 직접 접착된 열방출수단은 메탈캡(2)으로 구비하고, 이 메탈캡(2)의 하단부와 접촉되는 PCB 및 세라믹기판(8)의 사이에는 도시된 도면 제3도에서 보는바와 같이 애디히시브에폭시(7A)로 접착시켜 반도체칩(5)과 내부의 회로기능구성품들을 보호할 수 있도록 하였다.The heat dissipation means directly bonded to the C4 or the semiconductor chip 5 made of a flip chip die and the epoxy 7 is provided with a metal cap 2, and the PCB is in contact with the lower end of the metal cap 2; As shown in FIG. 3, the ceramic substrate 8 is bonded with an additive epoxy 7A to protect the semiconductor chip 5 and the circuit functional components therein.
상기 열방출수단의 다른 실시예에 있어서는 평면상의 메탈플레이트(3)를 구비하고 이 메탈플레이트(3)의 하부면에 C4, 또는 플립칩다이로된 반도체칩(1)을 에폭시(7)로 직접 접착 시킨다.In another embodiment of the heat dissipation means, the semiconductor chip 1 having a planar metal plate 3 and having a C4 or flip chip die on the lower surface of the metal plate 3 is directly coated with an epoxy 7. Glue.
상기와 같이 열방출수단의 메탈캡(2)과 메탈플레이트(3)는 반도체칩(5)의 상부에 구비되도록 하고, 반도체칩(5)의 상부면은 에폭시(7)로 메탈캡(2) 및 메탈플레이트(3)에 접착시키므로서, 범퍼(6)가 없는면을 열방출수단에 직접 접착시키도록 하여 회로 작동시 반도체칩(5)에서 발생하는 열이 에폭시(7)와 열방출수단을 통해 외부로 용이하게 배출될수 있게 한 것이다.As described above, the metal cap 2 and the metal plate 3 of the heat dissipation means are provided on the upper portion of the semiconductor chip 5, and the upper surface of the semiconductor chip 5 is made of an epoxy 7 and the metal cap 2. And by adhering to the metal plate 3, the surface without the bumper 6 is directly adhered to the heat dissipating means so that the heat generated from the semiconductor chip 5 during the circuit operation causes the epoxy 7 and the heat dissipating means. It can be easily discharged to the outside through.
상기한 열방출수단의 메탈캡(2)과 메탈플레이트(3)는 반도체 패키지의 동작시 반도체칩(5)에서 발생하는 열의 방출성을 좋게하기 위하여 알루미늄(Al), 구리(Cu),구리(Cu)+니켈(Ni)합금 또는 스테인레스재로 이루어지는 그룹으로 부터 선택되는 소재로 된 메탈캡(2)과 메탈플레이트(3)로 구비하여 열 방출성을 양호하게 한 것이다.The metal cap 2 and the metal plate 3 of the heat dissipation means are made of aluminum (Al), copper (Cu), and copper (copper) in order to improve heat dissipation generated from the semiconductor chip 5 during operation of the semiconductor package. It is provided with a metal cap (2) and a metal plate (3) made of a material selected from the group consisting of Cu) + nickel (Ni) alloy or stainless steel to improve heat dissipation.
상기한 반도체칩(5)을 열방출수단의 메탈캡(2)이나 메탈플레이트(3)에 접착시키는 에폭시(7)는 전기적으로 비전도체이고, 열전도성이 우수한 애디히시브에폭시재를 이용하거나, 또는 폴리마이드재(POLYMIDE)로 하여 반도체칩(5)의 회로에서 발생한 열 방출성을 향상시키도록 한다.Epoxy (7) for adhering the semiconductor chip (5) to the metal cap (2) or metal plate (3) of the heat dissipation means is electrically non-conductive, using an additive epoxy material excellent in thermal conductivity, Alternatively, the polyimide material may be used to improve heat dissipation generated in the circuit of the semiconductor chip 5.
상기한 열방출수단의 메탈캡(2)과 메탈플레이트(3)에 접착된 반도체칩(5)의 외부와 PCB 및 세라믹기판(8)의 사이에는 언더필메타리얼(9: UNDER FILL MATERIAL)을 충진시켜 반도체칩(5)이 외부로 노출되는 것을 방지하고, 또한 반도체칩(5)과 메탈플레이트(3)를 기판(8)에서 견고하게 고정될 수 있도록 하며, 각 구성 부품들의 외력에 의한 스트레스를 저감시킬 수 있도록 한 것이다.An underfill material (9: UNFILL MATERIAL) is filled between the outside of the semiconductor chip 5 bonded to the metal cap 2 and the metal plate 3 of the heat dissipation means and the PCB and the ceramic substrate 8. This prevents the semiconductor chip 5 from being exposed to the outside, and also allows the semiconductor chip 5 and the metal plate 3 to be firmly fixed to the substrate 8 and to prevent stress caused by external force of each component. It is to reduce.
또한, 상기 열방출수단에는 하나 이상의 구멍(4)을 형성하여 반도체칩(5)에서 발생된 열이 구멍(4)을 통하여 외부로 용이하게 방출될 수 있게 하므로서 열방출의 극대화를 이룰수 있게 한 것이다.In addition, at least one hole 4 is formed in the heat dissipation means, so that heat generated in the semiconductor chip 5 can be easily discharged to the outside through the hole 4, thereby maximizing heat dissipation. .
상기와 같이 열방출수단에 형성된 구멍(4)에는 반도체칩(5)과 접착되는 에폭시(7)가 충진 유입되어 반도체칩(5)과 열방출수단의 접착력을 향상시킬 수 있도록 하였으며, 열전도성이 좋은 애디히시브에폭시 또는 폴리마이드에폭시가 열방출수단의 구멍(4)을 통해 메탈캡(2)과 메탈플레이트(3)의 외부로 노출되어 외부공기와 직접 접촉됨에 따라서, 반도체칩(5)에서 발생하는 열의 방출이 용이하게 이루어질수 있도록 한 것이다.As described above, the hole 4 formed in the heat dissipating means is filled with epoxy 7 adhering to the semiconductor chip 5 to improve the adhesion between the semiconductor chip 5 and the heat dissipating means. In the semiconductor chip 5, as a good additive epoxy or polyamide epoxy is exposed to the outside of the metal cap 2 and the metal plate 3 through the hole 4 of the heat dissipation means and is in direct contact with the external air. It is to facilitate the release of the generated heat.
또한, 상기 열방지수단인 메탈캡(2)의 측면에 형성되는 하나 이상의 구멍(4)으로는 외부의 공기와 반도체 패키지의 동작시 반도체칩(5)에서 발생한 열의 통기성을 좋게하여, 반도체 패키지의 회로작동시 반도체칩(5)에서 발생하는 열의 열방출성을 향상시켜 반도체 패키지의 기능동작성을 높일 수 있게 한 것이다.In addition, the at least one hole 4 formed in the side surface of the metal cap 2, which is the heat preventing means, improves air permeability of the semiconductor chip 5 during operation of the semiconductor package with external air, thereby improving the It is to improve the heat dissipation of heat generated from the semiconductor chip 5 during the circuit operation to increase the functional operability of the semiconductor package.
한편, 본 발명의 반도체 패키지중 비.지.에이 반도체 패키지(1)의 다른 실시예에 있어서는, 도시된 도면 제9도에서 보는바와 같이 열방출수단인 메탈플레이트(3)하부로 에폭시(7)에 의해 접착된 반도체칩(5)과 PCB 및 세라믹기판(8)사이에는 언더필메타리얼(9)을 충진시키고, 이 언더필메타리얼(9)과 반도체칩(5)의 외부에는 글럽탑메타리얼(11: GLOB TOP MATERIAL)을 충진시켜 언더필메타리얼(9)을 보호하는 동시에 반도체칩(5)과 그외의 구성부품등을 견고하게 고착시킬 수 있게 한 것이다.On the other hand, in another embodiment of the B. G. semiconductor package 1 of the semiconductor package of the present invention, the epoxy (7) under the metal plate (3) which is a heat dissipation means as shown in FIG. The underfill material 9 is filled between the semiconductor chip 5 bonded to each other by the PCB and the ceramic substrate 8, and the outside of the underfill material 9 and the semiconductor chip 5 is provided with a glove top material ( 11: GLOB TOP MATERIAL) is used to protect the underfill material 9 and to firmly fix the semiconductor chip 5 and other components.
상기 비.지.에이 반도체(1)의 또 다른 실시예에 있어서는 도시된 도면 제10도에서 보는바와 같이 열방출수단인 메탈캡(2)이나 메탈플레이트(3)의 외부측으로 다수개의 방열핀(11:FIN)을 가진 핀타입열방출수단(11)을 구비하고, 방열핀(11A)의 반대측 열방출수단(11)에는 반도체칩(5)을 에폭시(7)로 부착하므로서, 반도체칩(5)에서 발생하는 열이 에폭시(7)를 통하여 핀타입열방출수단(11)인 방열핀(11A)에 전달되었을때 외부공기와 최대한 많이 접촉되는 방열핀(11A)에 의하여 열을 냉각시킬 수 있도록 함에 따라 반도체칩(5)에서 발생한 열의 외부방출을 높일 수 있게 한 것이다.In another embodiment of the B.G semiconductor 1, as shown in FIG. 10, a plurality of heat dissipation fins 11 are provided to the outside of the metal cap 2 or the metal plate 3, which are heat dissipation means. A fin type heat dissipating means 11 having a fin (FIN), and the semiconductor chip 5 is attached to the heat dissipating means 11 on the opposite side of the heat dissipation fins 11A by an epoxy 7. When the generated heat is transferred to the heat radiation fin (11A), the fin-type heat dissipation means (11) through the epoxy (7) to allow the heat to be cooled by the heat radiation fin (11A) in contact with the outside air as much as possible This is to increase the external discharge of heat generated in (5).
이상에서와 같이 본 발명은 반도체 패키지(비.지.에이 반도체, 시.오.비 반도체 패키지, 수퍼 비.지.에이 반도체 패키지)의 C4 (컨트롤즈 컬랩스 칩 캐리어), 또는 플립칩다이로된 반도체칩의 범프가 열방출수단인 메탈캡이나 메탈플레이트의 반대방향으로 위치되도록 애디히시브에폭시(전기적으로 비전도성이고, 열적전도성이 양호한 것)로 반도체칩을 접착하여 PCB 및 세라믹기판의 서브스트레이트에 직접 반도체칩을 본딩할 수 있도록 하므로서, 반도체 패키지의 작동중 반도체칩의 회로에서 발생하는 열을 에폭시와 열방출수단을 통해 외부로 용이하게 방출시킬 수 있도록 하여 고집적화된 반도체 패키지의 회로적 기능동작을 향상시킴에 따라 반도체 패키지 제품의 품질신뢰도를 높일수 있는 효과가 있는 것이다.As described above, the present invention provides a C4 (Controls Collabs Chip Carrier) or a flip chip die of a semiconductor package (B.G. Semiconductor, C.O.V. Semiconductor Package, Super B.G. Semiconductor Package). PCBs and ceramic substrates are bonded by adhering the semiconductor chips with an additive epoxy (electrically nonconductive and good thermal conductivity) so that the bumps of the semiconductor chips are located in the opposite direction of the metal cap or the metal plate, which are heat radiating means. By bonding the semiconductor chip directly to the straight, it is possible to easily release the heat generated from the circuit of the semiconductor chip during the operation of the semiconductor package to the outside through the epoxy and heat dissipation means, so that the circuit function of the highly integrated semiconductor package By improving the operation, it is possible to increase the quality reliability of semiconductor package products.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940039354A KR0167141B1 (en) | 1994-12-30 | 1994-12-30 | Semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940039354A KR0167141B1 (en) | 1994-12-30 | 1994-12-30 | Semiconductor package |
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| KR960026684A KR960026684A (en) | 1996-07-22 |
| KR0167141B1 true KR0167141B1 (en) | 1998-12-15 |
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| KR1019940039354A KR0167141B1 (en) | 1994-12-30 | 1994-12-30 | Semiconductor package |
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| KR100547391B1 (en) * | 2003-10-23 | 2006-01-31 | (주)동양기연 | Manufacturing method of heat sink for semiconductor package mounting |
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1994
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