KR0137558B1 - Mpeg-2 inverse multiplexer - Google Patents

Abstract

The present invention relates to an MPEG-2 demultiplexer, comprising: a byte alignment serial / parallel converter (6) for receiving a multiplexed serial bit stream and converting the result into parallel data in parallel by predetermined bits; TS packet demultiplexer (8) for receiving the parallel data according to PID) and outputting a PCR for restoring a clock and a distinct Widow signal that distinguishes the contents of the PES packet by interpreting the TS packet, and the program in the parallel data A PSI processing unit 10 for initializing the packet discrimination signal (PID) by analyzing the information about the PES packet, and the phase-adjusted data, window signal, DTS, and PTS reference signal by PES packet analysis of the parallel data and the discrimination window signal. And a PES packet demultiplexer 9 for outputting a signal, and a window clock recoverer 11 for restoring a system clock according to the PCR. It is effective to separate compressed video, audio and data from data, especially to satisfy the system standard proposed by MPEG-2.

Description

MP-2 demultiplexer

1 is a schematic diagram of multiplexing,

2 is a block diagram of an MPEG-2 demultiplexer according to the present invention;

3 is a detailed block diagram of a TS (Transport Stream) packet demultiplexer of FIG. 2;

4 is a detailed block diagram of a packetized elementery stream (PES) packet demultiplexer of FIG.

5 is the main signal timing diagram in FIGS.

* Description of the symbols for the main parts of the drawings *

1,2: Encoder 3,4: Packetizer

5: TS multiplexer 6: byte-aligned serial / parallel converter

7: divider 8: TS packet demultiplexer

9: PES packet demultiplexer

10: PSI (Program Specific Information) processing unit

11: system clock recovery unit 12: parallel / serial conversion unit

13: Sync byte detection unit 14: 188 byte counter

15,19: header processing unit 16: adaptive field processing unit

17: data byte processing unit 18: PES packet information detection unit

20: DTS (Decording Time Stamp), PTS (Presentation Time Stamp) output processing unit

21: data window generator 22: 8-bit counter

The present invention relates to an MPEG-2 demultiplexer.

In general, television broadcasting, including high-definition television (HDTV), is being studied digitally, and in the United States, the National Television System Committee (NTSC) satellite broadcasting has already begun digitally. In addition, the United States recently proposed a digital integration standard called Grand Alliance system among companies participating in HDTV, and the digital HDTV standard will be completed next year. Here, the meaning of the digital method is very large, that is, it can be said that the TV receiver contains the possibility of developing into a multimedia system beyond the concept of a receiver receiving only TV broadcast. This is because digital methods can be easily compatible with computers and other communication systems. NTSC satellite broadcasting and Grand Union HDTV systems have already been designed to focus on this perspective, making it compatible with other systems and easily expandable. Among the components of the system, video and audio compression techniques and these compressed signals and other The system technique for multiplexing data adopts the standard proposed by the international standard MPEG-2. In the coming years, digital communications standards with video, such as the Broadband Digital Information Service Network (BISDN), Satellite Broadcasting System (DBS), and Cable TV (CATV), will likely follow a similar structure.

Accordingly, there has been a demand for an MPEG-2 demultiplexer to implement such a technique.

The present invention devised in response to the above requirements provides an MPEG-2 demultiplexer that separates compressed video, audio and data from input multiplexed digital data, in particular satisfying the system standard proposed by MPEG-2. The purpose is.

In order to achieve the above object, the present invention provides a byte-aligned serial / parallel conversion unit for receiving a multiplexed serial bit stream and converting it into parallel data in parallel by predetermined bits and outputting the packet according to a packet discrimination signal (PID). TS packet demultiplexer which receives parallel data and interprets TS packet to output distinguished window signal and PCR for restoring clock and PES packet, and TS packet demultiplexer to analyze the program information from the parallel data A PSI processing unit for initializing a discrimination signal (PID), a PES packet demultiplexer for outputting phase-adjusted data, window signals, DTS, and PTS reference signals by analyzing the parallel data and the distinguishing window signal by PES packets; And a window clock recovery unit for restoring the system clock in accordance with PCR.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 5.

First, FIG. 1 is a schematic diagram of multiplexing. As shown in FIG. 1, the multiplexing method using TS (Transport Stream) can be divided into two steps. That is, the compressed bit stream output from each video and audio encoder (1, 2) is configured as a packetize elementery stream (PES) packet through a packetizer (3, 4), respectively. Next, these PES packets are multiplexed back into transport packets in units of 188 bytes through the TS multiplexer 5. The present invention relates to a demultiplexer for separating a multiplexed signal into a signal such as compressed video and audio.

2 is a block diagram of an MPEG-2 demultiplexer according to an embodiment of the present invention, FIG. 3 is a detailed block diagram of a TS packet demultiplexer of FIG. 2, and FIG. 4 is a detailed block diagram of a PES packet demultiplexer of FIG. 5 is a main signal timing diagram in FIGS. 2 to 4, in which 6 is a byte-aligned serial / parallel converter, 7 is a divider, 8 is a TS packet demultiplexer, and 9 is a PES packet inverse. A multiplexer, 10 is a PSI (Program Specific Information) processor, 11 is a system clock recovery unit, 12 is a parallel / serial converter, 13 is a sync byte detector, 14 is a 188 byte counter, 15 and 19 is a header processor, and 16 is adapted A field processor, 17 is a data byte processor, 18 is a PES packet information detector, 20 is a Decoding-T Time Stamp (DTS), a Presentation Time Stamp (PTS) output processor, 21 is a data window generator, and 22 is an 8-bit counter. Represent each.

First, as shown in FIG. 2, the present invention provides a byte-aligned serial / parallel converter 6 for receiving a multiplexed serial bit stream and converting the data into parallel data in parallel form by one byte; Receives the parallel data according to a packet identification signal (PID) and interprets the TS to packet-resolve the distinguishing window signals (pv_win, pa_win, pd_win) and the clock to distinguish the contents of the PES packet according to each elementary stream. A TS packet demultiplexer 8 for outputting a PCR (Program Clock Referance), a PSI processor 10 for interpreting information about a program from the parallel data to initialize the packet discrimination signal (PID), and the parallel data And a PES packet demultiplexer (9) for parsing the distinguished window signals (pv_win, pa_win, pd_win) to output the phase adjusted data, the window signal, the DTS, and the PTS reference signal. Accordingly, a system clock recovery unit 11 for outputting the 27 MHz clock and the LPCR to restore the system clock is provided.

In addition, a parallel / serial converter 12 for converting data output from the PES packet demultiplexer 9 into serial data and a clock (S clock) input in accordance with the serial bit stream are divided into eight bytes for one byte. A divider 7 for outputting a clock (P clock) suitable for parallel data is further provided.

Here, the byte alignment serial / parallel converter 6 is configured to convert the received serial bit stream into an 8-bit parallel signal in accordance with the byte unit of the MPEG-2 system syntax.

As shown in FIG. 3, the TS packet demultiplexer 8 includes a sync byte detector 13 for detecting a sync byte in a TS packet of the parallel data, and a PS packet counted according to the sync byte. A 188-byte counter 14 for outputting an end point signal of < RTI ID = 0.0 >, < / RTI > A distinction window signal (pv_win, pa_win) whose phase is compensated by processing the parallel data according to the output of the adaptive field processor 16, the 188 byte counter 14, the header processor 15, and the adaptive field processor 16, which are outputted. and a data byte processing unit 17 for outputting pd_win).

As shown in FIG. 4, the PES packet demultiplexer 9 receives the parallel data and detects the starting point and shape information of the PES packet, and the distinguished window signal. a header processor (19) which receives (pv_win, pa_win, pd_win), analyzes the header according to the starting point and type information of the PES packet, detects header and data length information of the PES packet, and generates a count control signal; 8-bit counter 22 for outputting payload start information, which is a reference signal starting from a PES packet, video, audio, and data information according to the count control signal, starting point and shape information of the PES packet, and the distinguishing window signal (pv_win). data window generator 21 for outputting the final window signal according to pa_win, pd_win), and DTS and PTS in the parallel data according to the output of the header processor 19 Has a DTS and PTS output processing section 20 for converting the output pocket into output pockets.

Looking at the detailed operation of the present invention configured as described above are as follows.

First, in FIG. 2, a byte-aligned serial / parallel converter 6 converts a bit stream serially input in units of bytes. At this time, the serial stream is byte aligned to fit the byte unit of MPEG-2 system syntax. The overall operation of the MPEG-2 demultiplexer of the present invention is performed in this converted byte unit. Therefore, the clock inputted according to the serial data also provides a clock that is synchronized with the parallel data through the divider 7. The converted parallel data is first passed through a TS packet demultiplexer 8 for releasing a transport packet. At this time, the PSI processor 10 analyzes information about a program to separate a desired PID before separating video and audio signals. It should be initialized. Based on the PID information thus initialized, the TS packet demultiplexer 8 delays and outputs the input parallel data as it is, and also distinguishes each (video, audio, data) PES packet in phase with it. The signals pv_win, pa_win, and pd_win are output. The receiving end should restore the clock used by the transmitting end, which can be restored using a time stamp called PCR included in the transport packet. That is, the TS packet demultiplexer 8 outputs this information to the system clock recovery unit 11 to output the locked 27 MHz clock and LPCR (Local PCR) from the system clock recovery unit 11. The PES packet demultiplexer 9 demultiplexes the PES packet by receiving the data and the distinct window signals pv_win, pa_win, and pd_win output from the TS packet demultiplexer 8. At this time, the PES packet demultiplexer 9 outputs the phase-controlled data and the final window signals (video_win, audio_win, data_win) indicating the actual video, audio, and data to each decoder. It also outputs DTS and PTS, which are time stamps to adjust the phase of audio and video. If you want to output data serially, the serial data is output through the parallel / serial conversion unit 12.

The operation of the TS packet demultiplexer 8 shown in FIG. 3 will be described.

First, the transport packet has a configuration of 188 byte units. The first byte is a sync byte. By using this information, the starting point of the transport packet can be known. In other words, the sync byte detector 13 finds the sync byte and then uses the 188 byte counter 14 to find out that the transmission packet is finished based on the sync byte. The signal indicating the end of the TS packet output from the 188 byte counter 14 is again input to the sync byte detection unit 13 and simultaneously to the data byte processing unit 17. The sync byte detector 13 outputs a reference signal to the header processor 15 to process header signals following the sync byte if a sync byte is detected at the start of the TS packet by using the signal output from the counter 14. . If the sync byte is not detected at the start, the sync byte is detected again, and the above process is repeated. The header processor 15 detects whether an adaptation field signal has been transmitted, and then outputs the reference signal to the adaptation field processor 16. By using the reference signals output from the counter 14, the header processor 15, and the adaptive field processor 16, the data byte processor 17 outputs window signals corresponding to the data and the PES packet whose phase has been compensated. do.

The operation of the PES packet demultiplexer 9 shown in FIG. 3 will be described.

First, the PES packet information detecting unit 18 detects the starting point of the PES packet and outputs the information to the header processing unit 19 and the data window generating unit 21 (PES starting point, PES type). The header processing unit 19 inputs a window for distinguishing the PES packets output from the TS packet demultiplexing unit 8 to interpret the headers, and in particular, detects the header and data length signals of the PES packets to the 8-bit counter 22. It will output a reference signal to load this signal. The 8-bit counter 22 outputs a reference signal starting from the PES packet to actual data, audio, and data information to the data window generator 21. In the data window generator 21, the reference signals (PES start point, PES type) output from the PES packet information detector 18 and the distinguished window signals (pv_win, pa_win, pd_win) output from the TS packet demultiplexer 8 ) Are used to generate window signals (video_win, audio_win, data_win) corresponding to the final video, audio, and data. The DTS and PTS output processing unit 20 finds the DTS and the PTS by using the reference signal output from the header processing unit 19, and then converts them to a desired output format and outputs the same. For reference, FIG. 5 is a signal diagram showing the relationship between the input and output signals of each block described above.

The present invention as described above has the effect of separating the compressed video, audio and data from the input digital data, in particular to operate to meet the system standard proposed by MPEG-2.

Claims (6)

A byte-aligned serial / parallel converter 6 for receiving the multiplexed serial bit streams and converting them into parallel data in parallel form by predetermined bits; A TS packet demultiplexer 8 for receiving the parallel data according to a packet discrimination signal (PID) and analyzing a TS packet to output a discrimination window signal for distinguishing the contents of the PES packet and a PCR for restoring a clock; A program specific information (PSI) processor 10 for interpreting information about a program from the parallel data and initializing the packet discrimination signal (PID); A PES packet demultiplexer (9) for parsing the parallel data and the distinguished window signal and outputting phase-adjusted data, window signals, DTS, and PTS reference signals; MPEG-2 demultiplexer characterized in that it comprises a window clock recovery unit 11 for restoring the system clock in accordance with the PCR The method of claim 1, And a parallel / serial converting section (12) for converting data output from said PES packet demultiplexing section (9) into serial data. The method of claim 1, The byte-aligned serial / parallel converter 6 And converting the received serial bit stream into an 8-bit parallel signal in accordance with byte units of MPEG-2 system syntax. The method of claim 1, The TS packet demultiplexer 8 A sync byte detection unit 13 for detecting a sync byte in the TS packet of the parallel data; A 188 byte counter 14 for counting according to the sync byte and outputting an endpoint signal of the TS packet; A first header processor 15 for interpreting the header of the parallel data according to the sync byte and outputting header information; An adaptive field processing unit 16 for outputting a PCR necessary to restore a system clock from a TS packet; And a data byte processor 17 for processing the parallel data according to the outputs of the 188 byte counter 14, the header processor 15, and the adaptive field processor 16, and outputting a phase-compensated distinct window signal. Featured MPEG-2 Demultiplexer. The method of claim 1, The PES packet demultiplexer 9 is A PES packet information detector 18 for receiving the parallel data and detecting starting point and shape information of the PES packet; A second header processor (19) which receives the distinguishing window signal and analyzes the header according to the starting point and shape information of the PES packet to detect the header and data length information of the PES packet, and generates a count control signal; An 8-bit counter 22 for outputting payload start information which is a reference signal starting from a PES packet according to the count control signal; A data window generator 21 for outputting a final window signal according to the start point and shape information of the PES packet and the distinguished window signal; MPEG-2 demultiplexer, characterized in that it comprises a DTS, PTS output processing unit 20 to find the DTS and PTS in the parallel data in accordance with the output of the second header processing unit 19, and then converts to a predetermined output format. . The method of claim 1, The system clock recovery unit 11, MPEG-2 demultiplexer configured to output a 27 MHz clock and LPCR according to the PCR.