JPS643064B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a method for manufacturing a semiconductor device that simplifies the manufacturing process by simultaneously forming a polycrystalline silicon thin film used for wiring and load resistance of a semiconductor device such as an LSI. It is related to.

Conventional Structure and Problems An example of a conventional method for forming wiring and load resistance using a polycrystalline silicon thin film in a MOS/LSI manufacturing process will be explained with reference to step-by-step sectional views shown in FIGS. 1a to 1h. First, in order to form an n-channel MOS transistor, a thick field SiO ₂ film 2 and a thin gate SiO ₂ film 3 are formed on a P-type silicon substrate 1 (FIG. 1a). For example, the thickness is applied to the surface using low pressure vapor phase deposition (LPCVD).
A 400 nm polycrystalline silicon film 4 was grown, phosphorous was ion-implanted into the polycrystalline silicon film 4, and the temperature was heated to 900°C.
After annealing for about 30 minutes, the sheet resistance was reduced to 20Ω/
It is formed in the low resistance layer of □ (Fig. 1b). Next, the low resistance polycrystalline silicon layer 4 is patterned by photolithography and dry etching to form a pattern on the gate electrode 4.
Source/drain regions 5 are formed in a self-aligned manner by As implantation (FIG. 1c). After forming the source/drain regions, a SiO ₂ film 6 with a thickness of about 400 nm is formed on the surface by low-temperature CVD (FIG. 1d). A contact window 7 is formed in a part of the SiO ₂ film 6 (FIG. 1e). Next, a second layer of polycrystalline silicon film 8 is formed to a thickness of 200 nm, boron B ⁺ ions are implanted, and annealing is performed to form a sheet resistance layer of about 10 ⁵ to ^{10 7} Ω/□ ( Figure 1 f). The second layer polycrystalline silicon film 8 is patterned to form a load resistance layer (FIG. 1g). Thereafter, an interlayer insulating film 9 is formed on the second polycrystalline silicon layer 8, and further,
By opening a contact window in this and then forming an aluminum Al electrode 10, electrode terminals for the source S, gate G, drain D, and load resistor R of the MOS transistor are formed (FIG. 1h).

In the conventional method described above, the polycrystalline silicon film is formed twice, including the formation of the first layer of low resistance polycrystalline silicon layer that will become the gate electrode and the formation of the second layer of high resistance polycrystalline silicon layer that will become the load resistance. It requires formation and the process is complicated. Furthermore, when growing the first layer of polycrystalline silicon film, it is necessary to form an interlayer insulating film, and the underlying insulating film for forming the second layer of polycrystalline silicon film is equal to the thickness (for example, about 0.5 μm). This results in problems such as an increase in thickness, a large base level difference in the subsequent Al wiring process, a large base level difference in the Al wiring process, and a high possibility of disconnection in the Al wiring process.

Purpose of the Invention The present invention relates to the conventional silicon gate MOS
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can eliminate problems in LSI manufacturing methods, that is, the problem of surface steps.

Structure of the Invention The present invention selectively applies a film that is inert to polycrystalline silicon at high humidity and serves as a mask for the dissipation of impurities in the polycrystalline silicon film to the same polycrystalline silicon film that has been doped with ion implantation. After formation, the semiconductor substrate is subjected to high-temperature heat treatment using an infrared radiation heating method in a short time to form a low-resistance polycrystalline silicon layer that will serve as the gate electrode and wiring, and a high-resistance polycrystalline silicon layer. According to this method, the process is simple and a flat structure can be obtained in which steps that are a cause of disconnection in the Al wiring formation process are reduced.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described with reference to step-by-step sectional views of FIGS. 2a to 2h. A thick field SiO ₂ film 2 and a thin gate SiO ₂ film 3 are selectively formed on a p-type silicon substrate 1 (FIG. 2a). Next, a contact window 7 connecting the high resistance layer and the substrate is formed by conventional photolithography and etching methods (FIG. 2b). A polycrystalline silicon film 4 with a thickness of 400 nm is grown on the surface at a low temperature of 600°C by, for example, the LP/CVD method, and phosphorus (P) ions are implanted at 2×10 ¹⁶ /cm ² at an energy of 40 KeV (Fig. 2). c).
Next, on the surface of the polycrystalline silicon film 4, a film 11 such as a SiO ₂ film or a silicon nitride (Si ₃ N ₄ ) film that is inactive against Si at high temperatures and prevents outward diffusion of impurities in the polycrystalline silicon film 4 is applied. is formed and patterned to cover only the surface of the polycrystalline silicon film that will become the gate electrode/wiring region, and remove the rest. Next, the surface of the polycrystalline silicon layer in the low-resistance gate wiring region is coated with SiO ₂ with a thickness of 0.3 μm formed by, for example, the CVD method.
The surface of the polycrystalline silicon layer having the film 11 and in the high resistance load resistance region is subjected to heat treatment without being covered with the CVD SiO ₂ film 11. For the heat treatment, for example, using a graphite heater, heating is performed for a short time of about 60 seconds at a temperature of 1200° C. in a vacuum (Fig. 2 d). Through this heat treatment, the area where the gate wiring electrode is to be formed, that is, the polycrystalline silicon layer deposited at a low temperature directly under the SiO ₂ film 11, is activated by the implanted phosphorus and recrystallization of the polycrystalline Si. Low resistance can be obtained. Also, inside the board directly under the contact window 7
An n ⁺ type contact region 12 is formed. on the other hand,
The region of the polycrystalline silicon layer 4 which does not have the SiO ₂ film 11 on its surface is heated for a short time at a high temperature by infrared radiation, so that phosphorus in the polycrystalline silicon evaporates by outward diffusion and a high resistance layer is obtained.

Figure 3 shows a sample on which a 400 nm polycrystalline silicon film was formed using the LPCVD method.
FIG. 2 is a correlation diagram obtained experimentally showing the relationship between the annealing time and the sheet resistance value of the polycrystalline silicon layer after annealing when heating is performed for 10 seconds to 60 seconds in a high vacuum of 10 ⁻⁵ torr. In FIG. 3, A shows a sample in which the polycrystalline silicon layer is coated with a CVD SiO ₂ film of 0.3 μm, and B shows the relationship in which nothing is coated on the polycrystalline silicon layer. From FIG. 3, under the annealing condition of 1200° C. for 60 seconds, there is a difference in resistance value of approximately 200 times depending on the presence or absence of the coating film. Next, boron ions in the region of the high-resistance polycrystalline silicon layer are heated to 1 to 2 × 10 ¹⁴ at 30 KeV.
The sheet resistance value ^is 10 ³ to 10 ⁵ Ω/□.
Form a high-resistance polycrystalline silicon layer (second
Figure e). Next, unnecessary portions of the polycrystalline silicon film 4 are removed by patterning technology (FIG. 2f). Next, about 0.3 μm thick film is applied on the polycrystalline silicon film 4.
A SiO ₂ film 13 is grown by the CVD method to cover only the surface of the high-resistance polycrystalline silicon region, the remaining part is removed by patterning, and then the n ⁺ type source/drain region 5 is grown by As ion implantation. form (Fig. 2g). At this time, one drain region 5 is made to overlap the contact region 12.

Thereafter, after activation annealing of the source/drain regions 5 is performed, the SiO ₂ film 13 is left or removed, and a SiO ₂ film of approximately 0.8 μm is deposited as an interlayer insulating film.
A film 9 is formed, contact windows for the source, drain gate, and load resistance are formed, and an Al wiring electrode 10 is formed to form an n-channel MOS transistor and a load resistance element (FIG. 2h).

In this embodiment, phosphorus and boron were used to dope the polycrystalline silicon layer, but impurities that serve as carriers for silicon, such as As and Sb, may also be used. In addition, the coating film on the polycrystalline silicon layer is made of other than _SiO2 .
Any film that prevents outward diffusion such as Si ₃ N ₄ may be used.

Effects of the Invention As described above, by forming a low-resistance region and a high-resistance region in a single layer of polycrystalline silicon layer as in the present invention, it is possible to simplify the process, and also to form a step difference in the base of the Al wiring layer. By reducing this, we were able to reduce the number of disconnections in the Al wiring.

[Brief explanation of the drawing]

Figures 1a to 1h are cross-sectional schematic diagrams of the steps in manufacturing MOSLSI using the conventional method. Figures 2 a to h are cross-sectional diagrams of the steps in manufacturing MOSLSI by the method of the present invention. Figure 3 shows phosphorus at 40 KeV. When a 400 nm thick polycrystalline silicon film doped with 2×10 ¹⁶ pieces/cm ² is annealed at 1200°C using infrared radiation heating,
FIG. 3 is a characteristic diagram showing the relationship between annealing time and sheet resistance value of a polycrystalline layer. 1... p-type silicon semiconductor substrate, 2... SiO ₂
Membrane (field), 3...SiO ₂ membrane (gate), 4
...Polycrystalline silicon gate electrode, 5...Source/
Drain n ⁺ diffusion region, 9... polycrystalline silicon -
Al wiring interlayer insulating film, 10... Al wiring electrode, 11
...SiO ₂ film, 12...contact diffusion region.

Claims (1)

[Claims] 1. A step of depositing a polycrystalline silicon thin film doped with impurities at a relatively low temperature on the main surface on which the semiconductor element region of the semiconductor substrate is formed, and depositing an impurity-doped polycrystalline silicon thin film on the surface of the polycrystalline silicon film at a high temperature. A method for manufacturing a semiconductor device, comprising the steps of: forming a film that is active and prevents outward diffusion of impurities in a polycrystalline silicon film; and heat-treating the semiconductor substrate using an infrared radiation heating method.