JPS6420768U - - Google Patents
Info
- Publication number
- JPS6420768U JPS6420768U JP11486587U JP11486587U JPS6420768U JP S6420768 U JPS6420768 U JP S6420768U JP 11486587 U JP11486587 U JP 11486587U JP 11486587 U JP11486587 U JP 11486587U JP S6420768 U JPS6420768 U JP S6420768U
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- semiconductor device
- device package
- view
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 3
- 239000011810 insulating material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案の原理平面図、第２図は本考案
による一実施例の説明図で、ａは斜視図、ｂは側
面断面図、ｃは側面図、第３図は本考案の他の実
施例の説明図で、ａは斜視図、ｂは要部側面断面
図、第４図は従来の説明図で、ａ，ｂは斜視図、
ｂは側面断面図、ｃは側面図を示す。
図において、１はチツプ、２はマウンテイング
、３はフラツトリード、４は貫通穴を示す。
Fig. 1 is a plan view of the principle of the present invention, Fig. 2 is an explanatory diagram of an embodiment according to the present invention, where a is a perspective view, b is a side sectional view, c is a side view, and Fig. 3 is a diagram showing the principle of the present invention. FIG. 4 is an explanatory diagram of the embodiment, in which a is a perspective view, b is a side sectional view of main parts, and FIG. 4 is a conventional explanatory diagram; a and b are perspective views;
b shows a side sectional view, and c shows a side view. In the figure, 1 is a chip, 2 is a mounting, 3 is a flat lead, and 4 is a through hole.
Claims (1)
イング２と、該マウンテイング２の外周に突出し
たフラツトリード３とを備えた半導体素子パツケ
ージにおいて、 前記マウンテイング２の表面から裏面に貫通す
る複数の貫通穴４が設けられて成ることを特徴と
する半導体素子パツケージ。[Claims for Utility Model Registration] A semiconductor device package comprising a mounting 2 made of an insulating material in which a chip 1 is buried, and a flat lead 3 protruding from the outer periphery of the mounting 2, from the front surface to the back surface of the mounting 2. A semiconductor device package characterized in that a plurality of through holes 4 are provided to penetrate through the semiconductor device package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11486587U JPS6420768U (en) | 1987-07-27 | 1987-07-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11486587U JPS6420768U (en) | 1987-07-27 | 1987-07-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6420768U true JPS6420768U (en) | 1989-02-01 |
Family
ID=31355998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11486587U Pending JPS6420768U (en) | 1987-07-27 | 1987-07-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6420768U (en) |
-
1987
- 1987-07-27 JP JP11486587U patent/JPS6420768U/ja active Pending