JPS6388908A - Monolithic integrated circuit - Google Patents
Monolithic integrated circuitInfo
- Publication number
- JPS6388908A JPS6388908A JP23504886A JP23504886A JPS6388908A JP S6388908 A JPS6388908 A JP S6388908A JP 23504886 A JP23504886 A JP 23504886A JP 23504886 A JP23504886 A JP 23504886A JP S6388908 A JPS6388908 A JP S6388908A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- terminal
- line
- capacitance
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000001902 propagating effect Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Microwave Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、モノリシック集積回路に関し、特に3端子を
有し、そのうち2端子が容量性結合をもつような構造の
分岐回路を用いるモノリシック集積回路に関するもので
ある。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a monolithic integrated circuit, and particularly to a monolithic integrated circuit using a branch circuit having three terminals, two of which have capacitive coupling. It is related to.
第2図は例えば1986 1EEE MTT−Sマイ
クロウェーブ シンポジウム ダイジェスト13−17
頁(Microeyave Symp、Dig、 P
、13−17)に示された分布型モノリシック増幅器の
1セルの電界効果トランジスタのゲート側入力伝送線路
部分の等価回路、第3図はそのパターン図である。分布
型モノリシック増幅器は、電界効果トランジスタのゲー
ト・ソース間容量、ドレイン・ソース間容量を利用した
もので、ゲート側、ドレイン側を集中インダクタンスま
たは分布定数線路でそれぞれ結線し、擬似的に分布定数
線路にみたてて、広帯域な増幅器を得るものである。Figure 2 shows, for example, 1986 1EEE MTT-S Microwave Symposium Digest 13-17.
Page (Microeyave Symp, Dig, P
, 13-17), and FIG. 3 is a pattern diagram thereof. Distributed monolithic amplifiers utilize the gate-source capacitance and drain-source capacitance of field effect transistors, and connect the gate and drain sides with lumped inductance or distributed constant lines, creating a pseudo distributed constant line. In this way, a broadband amplifier can be obtained.
第2図の等価回路においては、入力端子lから入った信
号は、金属線路によるインダクタンス2゜端子3に接続
される電界効果トランジスタの等測的なゲート・ソース
間容量4.金属線路によるインダクタンス5.入力端子
1と出力端子6とを結ぶ容量7から構成される橋絡T形
回路により増幅される。この回路は、上記構成素子の各
値の選び方によって、出力端子6に伝送される信号の振
幅が周波数に無関係に一定な全域通過回路となることが
わかっている。このため、非常に広帯域な増幅器を構成
できる。In the equivalent circuit of FIG. 2, a signal input from the input terminal l has an inductance of 2° due to the metal line and an isometric gate-source capacitance of the field effect transistor connected to the terminal 3, 4. Inductance due to metal line5. The signal is amplified by a bridging T-shaped circuit composed of a capacitor 7 connecting the input terminal 1 and the output terminal 6. It has been found that this circuit becomes an all-pass circuit in which the amplitude of the signal transmitted to the output terminal 6 is constant regardless of the frequency, depending on how the values of the above-mentioned components are selected. Therefore, an extremely wideband amplifier can be constructed.
第3図は第2図の等価回路を実現した金属配線図であり
、添字の番号が第2図の各素子を構成する部分に対応す
る。7aは下側金属線路2aと上側金属線路5aとの間
に誘電体8を挿入する平行平板容量を利用して、出力端
子6aと入力端子1aとを容量的に結合したものである
。FIG. 3 is a metal wiring diagram that realizes the equivalent circuit of FIG. 2, and the subscript numbers correspond to the parts constituting each element in FIG. 2. 7a, the output terminal 6a and the input terminal 1a are capacitively coupled by using a parallel plate capacitor in which a dielectric 8 is inserted between the lower metal line 2a and the upper metal line 5a.
従来のモノリシック集積回路は以上のように構成されて
いるので、平行平板容M1aの部分の基板の表面荒さ、
エツチングの過程でのピンホールの存在により、絶縁耐
圧が劣化し、信頼性に問題があった。Since the conventional monolithic integrated circuit is configured as described above, the surface roughness of the substrate in the parallel plate volume M1a,
Due to the presence of pinholes during the etching process, the dielectric strength deteriorated, causing reliability problems.
本発明は上記のような問題点を解消するためになされた
もので、金属線路形成時に同時に容量を構成できるとと
もに、絶縁耐圧の劣化をも防止できるモノリシックS積
回路を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and aims to provide a monolithic S product circuit that can simultaneously configure a capacitor when forming a metal line and also prevent deterioration of dielectric strength.
本発明に係るモノリシック集積回路は、半絶縁性半導体
基板の一部表面の同一平面上に3端子を有し、そのうち
2端子間に容量性結合をもつように分岐回路を形成し、
これをモノリシック増幅器として用い、上記2端子をそ
れぞれ入力、出力端子とし、第3の端子をゲート接続端
子としたものである。A monolithic integrated circuit according to the present invention has three terminals on the same plane on a part of the surface of a semi-insulating semiconductor substrate, and a branch circuit is formed so as to have capacitive coupling between two of the terminals,
This is used as a monolithic amplifier, with the two terminals used as input and output terminals, respectively, and the third terminal used as a gate connection terminal.
本発明においては、同一平面上に3端子を有し、そのう
ち、2端子間に容量性結合を有する分岐回路をモノリシ
ック増幅器として用いることにより、ストリップ線路と
同時に容量を構成でき、また絶縁耐圧の劣化をも防止で
きる。In the present invention, by using a branch circuit having three terminals on the same plane and having capacitive coupling between two terminals as a monolithic amplifier, a capacitor can be configured at the same time as a strip line, and the dielectric breakdown voltage may deteriorate. can also be prevented.
以下、本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例を示す金属配線パターン図で
、この等価回路は第2図と同じであり、第1図の添付番
号は各等価回路構成素子と対応する。FIG. 1 is a metal wiring pattern diagram showing one embodiment of the present invention. This equivalent circuit is the same as that in FIG. 2, and the attached numbers in FIG. 1 correspond to each equivalent circuit component.
また、7bは入力端子1bの金属線路と出力端子6bの
金属線路とを隣接させることにより構成したギャップ容
量である。Moreover, 7b is a gap capacitance constructed by making the metal line of the input terminal 1b and the metal line of the output terminal 6b adjacent to each other.
図に示すように、本実施例による半絶縁性半導体基板の
同一平面上に形成された分布型モノリシック増@器の1
セルの電界効果トランジスタのゲート入力線路は、入力
端子1b、金属線路2b。As shown in the figure, one of the distributed monolithic amplifiers formed on the same plane of the semi-insulating semiconductor substrate according to this embodiment.
The gate input line of the field effect transistor of the cell is an input terminal 1b and a metal line 2b.
電界効果トランジスタのゲート側の等測的なゲート・ソ
ース間容量に接続される端子3b、金属線路5b、出力
端子6b、入力端子1bと出力端子6bの金属線路部分
を隣接させたギャップ7bから成り立つ。It consists of a terminal 3b connected to the isometric gate-source capacitance on the gate side of the field effect transistor, a metal line 5b, an output terminal 6b, and a gap 7b where the metal line parts of the input terminal 1b and the output terminal 6b are adjacent to each other. .
このような線路を高周波の波が伝搬するとき、ギャップ
7bは容量として動作し、また、金属線路部分2b、5
bはインダクタンスになるため、等価回路は第2図と同
様の橋絡T形回路となり、各素子値を選ぶことで全帯域
通過回路を構成でき、広帯域な増幅が可能となる。When high-frequency waves propagate through such a line, the gap 7b acts as a capacitor, and the metal line portions 2b, 5
Since b is an inductance, the equivalent circuit becomes a bridging T-type circuit similar to that shown in FIG. 2, and by selecting the values of each element, an all-bandpass circuit can be constructed, and wideband amplification becomes possible.
また、ギャップ容量7bは、これにより結合される2端
子1b、6bが同一平面上にあり、金属線路形成時と同
一プロセスで形成が可能であるので、形成プロセスの軽
減ができ、また、ピンホールなどによる絶縁耐圧の劣化
も防止でき、回路の信頼性の向上も図れる。In addition, the gap capacitance 7b has the two terminals 1b and 6b connected to each other on the same plane and can be formed in the same process as when forming the metal line, so the formation process can be reduced, and pin holes can be eliminated. It is also possible to prevent deterioration of dielectric strength due to such factors, and improve circuit reliability.
なお、上記実施例では金属線路2b、5bを円形状に形
成したものを示したが、この形状は楕円状であってもよ
い。In the above embodiment, the metal lines 2b and 5b are circular, but the metal lines 2b and 5b may have an elliptical shape.
以上のように、この発明に係るモノリシック集積回路に
よれば、同一平面上に3#i子を有し、そのうち2端子
間に容量を有する分岐回路を形成し、これをモノリシッ
ク増幅器として用いるように構成したので、形成プロセ
スが軽減され、絶縁耐圧の劣化の防止もでき、信頼性が
向上する。As described above, according to the monolithic integrated circuit according to the present invention, it is possible to have 3 #i terminals on the same plane, form a branch circuit having a capacitance between two of the terminals, and use this as a monolithic amplifier. With this configuration, the formation process can be reduced, deterioration of dielectric strength voltage can be prevented, and reliability can be improved.
第1図はこの発明の一実施例による分岐回路の全屈配線
パターン図、第2図はこの発明による分岐回路の等価回
路を示す図、第3図は従来の分岐回路の金属配線パター
ン図である。
1bは入力端子、2b、5bは金属線路によるインダク
タンス、3bは電界効果トランジスタのゲート側への接
続端子、6bは出力端子、7bはギャップ容量。
なお、図中、同一符号は同一、又は相当部分を示す。Fig. 1 is a diagram showing a full-bend wiring pattern of a branch circuit according to an embodiment of the present invention, Fig. 2 is a diagram showing an equivalent circuit of a branch circuit according to the invention, and Fig. 3 is a diagram showing a metal wiring pattern of a conventional branch circuit. be. 1b is an input terminal, 2b and 5b are inductances due to metal lines, 3b is a connection terminal to the gate side of the field effect transistor, 6b is an output terminal, and 7b is a gap capacitance. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (2)
成された、3端子を有し、そのうち2端子間に容量性結
合をもつ分岐回路を用い、上記2端子をそれぞれ入力、
出力端子とし、第3の端子をゲート接続端子として構成
したモノリシック増幅器を有することを特徴とするモノ
リシック集積回路。(1) Using a branch circuit having three terminals formed on the same plane on a part of the surface of a semi-insulating semiconductor substrate and having capacitive coupling between two of the terminals, inputting each of the above two terminals,
A monolithic integrated circuit comprising a monolithic amplifier configured as an output terminal and a third terminal as a gate connection terminal.
ことを特徴とする特許請求の範囲第1項記載のモノリシ
ック集積回路。(2) The monolithic integrated circuit according to claim 1, wherein the capacitive coupling is coupling by gap capacitance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23504886A JPS6388908A (en) | 1986-10-01 | 1986-10-01 | Monolithic integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23504886A JPS6388908A (en) | 1986-10-01 | 1986-10-01 | Monolithic integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6388908A true JPS6388908A (en) | 1988-04-20 |
Family
ID=16980313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23504886A Pending JPS6388908A (en) | 1986-10-01 | 1986-10-01 | Monolithic integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6388908A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6392840B1 (en) * | 1997-12-08 | 2002-05-21 | International Business Machines Corporation | Planarized side by side design of an inductive writer and single metallic magnetoresistive reader |
EP1503415A2 (en) | 2003-07-26 | 2005-02-02 | Samsung Electronics Co., Ltd. | On-chip Inductors having interconnect and inductor portions providing combined magnetic fields |
-
1986
- 1986-10-01 JP JP23504886A patent/JPS6388908A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6392840B1 (en) * | 1997-12-08 | 2002-05-21 | International Business Machines Corporation | Planarized side by side design of an inductive writer and single metallic magnetoresistive reader |
EP1503415A2 (en) | 2003-07-26 | 2005-02-02 | Samsung Electronics Co., Ltd. | On-chip Inductors having interconnect and inductor portions providing combined magnetic fields |
EP1503415A3 (en) * | 2003-07-26 | 2011-04-27 | Samsung Electronics Co., Ltd. | On-chip Inductors having interconnect and inductor portions providing combined magnetic fields |
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