JPS6378552A - Formation of throughhole - Google Patents
Formation of throughholeInfo
- Publication number
- JPS6378552A JPS6378552A JP22398186A JP22398186A JPS6378552A JP S6378552 A JPS6378552 A JP S6378552A JP 22398186 A JP22398186 A JP 22398186A JP 22398186 A JP22398186 A JP 22398186A JP S6378552 A JPS6378552 A JP S6378552A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- insulating film
- film
- mask
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000010408 film Substances 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000011229 interlayer Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 239000002904 solvent Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体装置の多層配線技術に関し、特には層間
絶縁膜で隔てられた金属配線に対して電気的導通を取る
ためのスルーホールの形成方法に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to multilayer wiring technology for semiconductor devices, and in particular to the formation of through holes for establishing electrical continuity between metal wiring separated by interlayer insulating films. Regarding the method.
〈従来の技術〉
多層配線構造をもつ半導体装置においては、電気的に隔
てられた上部と下部の導体をつなぐスルーホー／１／を
層間絶縁膜に形成する必要がある。半導体集積回路の大
規模化とともにヌル−ホール数は急増し、一方半導体集
積回路の高密度化のため多層配線は微細化され、それに
伴いヌル−ホールも微小なものが要求されている。<Prior Art> In a semiconductor device having a multilayer wiring structure, it is necessary to form a through hole /1/ in an interlayer insulating film to connect electrically separated upper and lower conductors. As the scale of semiconductor integrated circuits increases, the number of null holes increases rapidly. On the other hand, as semiconductor integrated circuits become more dense, multilayer wiring becomes finer, and as a result, smaller null holes are required.
第２図（ａ）〜（ｄ）に示した工程はスルーホールを形
成するために従来から行われている方法である。The steps shown in FIGS. 2(a) to 2(d) are conventional methods for forming through holes.
即ち、第２図（ａ）に示すように回路素子を形成したＳ
ｉ基板２１上にはＳｉＯ□膜２２が被着され、該５ｉ０
２膜２２上にはＡ１等で配線２３がなされている。こう
して形成した第１の配線層２３と次に形成する第２の配
線層とを絶縁分離するために第１の配線層を形成した半
導体基板上に層間絶縁膜２４を形成する。上記層間絶縁
膜２４としてはポリイミド系樹脂（以下ＰＩＱ）が一般
によく。That is, S with circuit elements formed as shown in FIG. 2(a)
A SiO□ film 22 is deposited on the i-substrate 21, and the 5i0
On the second film 22, a wiring 23 is formed using A1 or the like. An interlayer insulating film 24 is formed on the semiconductor substrate on which the first wiring layer has been formed, in order to insulate and separate the first wiring layer 23 thus formed from the second wiring layer to be formed next. The interlayer insulating film 24 is generally made of polyimide resin (hereinafter referred to as PIQ).
用いられている。It is used.
この層間絶縁膜２４にスルーホールを形成する之めに以
下のような工程を行なう。第２図（ａ）に示すように層
間絶縁膜であるＰＩＱ２４上にホトレジス） ２５’ｅ
塗布する。次にホトリリグラフィを行なって上記ホトレ
ジスト２５のパターニンクヲ行なう（第２図（ｂ））。To form through holes in this interlayer insulating film 24, the following steps are performed. As shown in FIG. 2(a), a photoresist (25'e) is placed on PIQ24, which is an interlayer insulating film.
Apply. Next, photoresist 25 is patterned by photolithography (FIG. 2(b)).
該レジストパターン２５ａ。The resist pattern 25a.
をマスクとしてドライ・エツチングにてＰＩＱ２４をエ
ツチングしく第２図（Ｃ））、最後に上記レジストパタ
ーン２５ａｅ剥離して層間絶縁膜のスルーホールパター
ンを形成する（第２図（ｄ））。Using this as a mask, the PIQ 24 is etched by dry etching (FIG. 2(C)), and finally, the resist pattern 25ae is peeled off to form a through-hole pattern in the interlayer insulating film (FIG. 2(d)).
〈発明が解決しようとする問題点〉
上述する方法で層間絶縁膜にスルーホールを形成すると
、Ｋ２図（Ｃ）に示す如くレジストパターンをマスクと
して眉間絶縁膜であるＰＩＱをエツチングしてパターニ
ングする工程で、マスクであるホトレジストとＰＩＱと
の選択比が低いためエツチングがＰＩＱの最下端に達す
る頃にはレジストパターンもエツチングされて大きくな
り、ＰＩＱはオーバーエッチ状態となる。したがってＰ
ＩＱのスルーホールが所望する大きさに得られないだけ
でなく、微小なスルーホール形成が困難であるという問
題がある。<Problems to be Solved by the Invention> When a through hole is formed in the interlayer insulating film by the method described above, a process of etching and patterning the PIQ, which is the insulating film between the eyebrows, using a resist pattern as a mask, as shown in Figure K2 (C). Since the selectivity between the photoresist as a mask and the PIQ is low, by the time the etching reaches the bottom of the PIQ, the resist pattern is also etched and becomes larger, resulting in an overetched state of the PIQ. Therefore P
There is a problem that not only the IQ through hole cannot be obtained in a desired size, but also that it is difficult to form a minute through hole.
〈問題点を解決するための手段〉
本発明は上述する問題を解決するためになされたもので
、層間絶縁膜上にホトレジストを被着し、該ホトレジス
ト上にＡｌｔ蒸着させてパターニングした後ＡＩを層間
絶縁膜のエツチングマスクとして利用し、ホトレジスト
はリフト・オフ法による。ｌマスクパターンの剥離に用
いるスルーホール形成方法を提供するものである。<Means for Solving the Problems> The present invention has been made to solve the above-mentioned problems, and involves depositing a photoresist on an interlayer insulating film, depositing Alt on the photoresist, patterning it, and then applying AI. It is used as an etching mask for the interlayer insulating film, and the photoresist is processed using the lift-off method. This invention provides a through hole forming method used for peeling off a mask pattern.
く作 用〉
上述の如＜Ａｌｌパターンをマスクとして用いて層間絶
縁膜のエツチングを行なうと、層間絶縁膜とＡｌの選択
比が高いため得られるスルーホールは所望する形状通り
のものとなり、微小なスルーホールの形成が可能になる
。Function> As mentioned above, when etching the interlayer insulating film using the All pattern as a mask, the through holes obtained will have the desired shape because the selectivity between the interlayer insulating film and Al is high, resulting in minute holes. It becomes possible to form through holes.
〈実施例〉
第１図（ａ）〜（ｄ）は本発明による一実施例の工程を
説明するための断面図である。即ち、第１図（ａ）に示
すように半導体回路素子を作シ込んだＳｉ基板１上にＳ
ｉＯ□膜２を被着し、例えばＡ６にて１層目の配線３を
行なう。次に配線導体の１層目と２層目とを電気的に絶
縁分離する次めの層間絶縁膜としてＰＩＱ４を被着し、
このＰＩＱ４上にホトレジスト５を塗布する。更にこの
ホトレジスト５上にＡ１６を蒸着する。<Example> FIGS. 1(a) to 1(d) are sectional views for explaining the steps of an example according to the present invention. That is, as shown in FIG. 1(a), S is deposited on a Si substrate 1 on which semiconductor circuit elements are formed.
An iO□ film 2 is deposited, and the first layer wiring 3 is formed at A6, for example. Next, PIQ4 is deposited as the next interlayer insulating film that electrically isolates the first and second layers of the wiring conductor.
A photoresist 5 is applied on this PIQ4. Furthermore, A16 is deposited on this photoresist 5.
次に第２図（ｂ）に示すようにＡ１６をヌル−ホールの
パターンにドライ・エツチングによりパターニングする
。このＡｌパターン６ａｋマスクとしてホトレジスト５
とＰＩＱ４とをドライ・エツチングによシバターニング
する（第２図（Ｃ））。最後に、マスクに用いたＡｌパ
ターン６ａはＡｌパターン６ａとＰＩＱ４との間に形成
されたホトレジスト４をアセトンで溶解する時同時に剥
離され（リフト・オフ法）、ヌル−ホール７が形成され
る（第１図（ｄ））。Next, as shown in FIG. 2(b), A16 is patterned into a null-hole pattern by dry etching. Photoresist 5 is used as this Al pattern 6ak mask.
and PIQ4 are patterned by dry etching (FIG. 2(C)). Finally, the Al pattern 6a used as a mask is removed at the same time as the photoresist 4 formed between the Al pattern 6a and the PIQ 4 is dissolved with acetone (lift-off method), and a null hole 7 is formed ( Figure 1(d)).
本実施例でばＡｌｋマスク材として用いて層間絶縁膜で
あるＰＩＱのエツチングを行なっており、Ａｌｕホトレ
ジヌトに比べＰＩＱとの選択比が高いためＰＩＱのエツ
チング途中にＡｌマスクパターンの大きさが変わること
はほとんどない。したがって所望する大きさのスルーホ
ールを得られ、また微小なスルーホールの形成が可能に
なるものである。In this example, PIQ, which is an interlayer insulating film, is etched using Alk as a mask material, and because it has a higher selectivity to PIQ than Al photoresin, the size of the Al mask pattern changes during etching of PIQ. There are almost no Therefore, it is possible to obtain a through hole of a desired size, and it is also possible to form a minute through hole.
本発明は、Ａｌと同様に層間絶縁膜との選択比が高い他
の金属薄膜を用いてもよいことは明らかである。It is clear that the present invention may use other metal thin films that have a high selectivity to the interlayer insulating film, similar to Al.
〈効果〉
以上本発明によれば、微小なスルーホールを形成するこ
とができて半導体集積回路の高密度化が図れるため、集
積度の高い多層配線構造金持つ半導体装置を作製するこ
とが可能になる。<Effects> According to the present invention, minute through holes can be formed and the density of semiconductor integrated circuits can be increased, making it possible to fabricate a semiconductor device with a multilayer wiring structure with a high degree of integration. Become.
第１図（ａ）〜（ｄ）は本発明による一実施例の工程を
説明するための断面図、第２図（ａ）〜（ｄ）は従来の
工程を説明するための断面図である。
１、Ｓｉ基板 ２．５ｉ０２膜 ３．１層目配線
４．ＰＩＱ５． ホトレジヌト６ａ、Ａｌパターン
７．スルーホール代理人 弁理士 杉 山 毅
至（他１名）第１ｆｆｌFIGS. 1(a) to (d) are cross-sectional views for explaining the steps of an embodiment of the present invention, and FIGS. 2(a) to (d) are cross-sectional views for explaining the conventional steps. . 1. Si substrate 2.5i02 film 3. 1st layer wiring
4. PIQ5. Photoresinut 6a, Al pattern 7. Through Hole Agent Patent Attorney Takeshi Sugiyama
To (1 other person) 1st ffl
Claims (1)
る方法において、 層間絶縁膜上にリフト・オフのためのホトレジストを塗
布する工程と、 該ホトレジスト上にマスクとなる金属薄膜を蒸着する工
程と、 該金属薄膜をパターニングする工程と、 前記金属薄膜パターンをマスクとして層間絶縁膜とホト
レジストとをエッチングする工程と、リフト・オフ法に
より上記ホトレジストとこの上の金属薄膜パターンを除
去する工程とからなり、微小なスルーホールを形成する
ことを特徴とするスルーホールの形成方法。[Claims] 1. A method for forming a through hole in an interlayer insulating film on a semiconductor substrate, comprising: applying a photoresist for lift-off on the interlayer insulating film; and applying a metal serving as a mask on the photoresist. a step of vapor depositing a thin film; a step of patterning the metal thin film; a step of etching the interlayer insulating film and the photoresist using the metal thin film pattern as a mask; and a lift-off method to remove the photoresist and the metal thin film pattern thereon. A method for forming a through hole, which comprises a step of removing, and forming a minute through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22398186A JPS6378552A (en) | 1986-09-22 | 1986-09-22 | Formation of throughhole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22398186A JPS6378552A (en) | 1986-09-22 | 1986-09-22 | Formation of throughhole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6378552A true JPS6378552A (en) | 1988-04-08 |
Family
ID=16806705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22398186A Pending JPS6378552A (en) | 1986-09-22 | 1986-09-22 | Formation of throughhole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6378552A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5372971A (en) * | 1991-10-02 | 1994-12-13 | Hyundai Electronics Industries Co. Ltd. | Method for forming via hole in multiple metal layers of semiconductor device |
| US5510294A (en) * | 1991-12-31 | 1996-04-23 | Sgs-Thomson Microelectronics, Inc. | Method of forming vias for multilevel metallization |
| US5571751A (en) * | 1994-05-09 | 1996-11-05 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
-
1986
- 1986-09-22 JP JP22398186A patent/JPS6378552A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5372971A (en) * | 1991-10-02 | 1994-12-13 | Hyundai Electronics Industries Co. Ltd. | Method for forming via hole in multiple metal layers of semiconductor device |
| US5510294A (en) * | 1991-12-31 | 1996-04-23 | Sgs-Thomson Microelectronics, Inc. | Method of forming vias for multilevel metallization |
| US5571751A (en) * | 1994-05-09 | 1996-11-05 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
| US5666007A (en) * | 1994-05-09 | 1997-09-09 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
| US5691572A (en) * | 1994-05-09 | 1997-11-25 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
| US5798299A (en) * | 1994-05-09 | 1998-08-25 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
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