JPS6360537A - Metallic laminate and manufacture thereof - Google Patents
Metallic laminate and manufacture thereofInfo
- Publication number
- JPS6360537A JPS6360537A JP20545786A JP20545786A JPS6360537A JP S6360537 A JPS6360537 A JP S6360537A JP 20545786 A JP20545786 A JP 20545786A JP 20545786 A JP20545786 A JP 20545786A JP S6360537 A JPS6360537 A JP S6360537A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- alloy
- metal
- atomic
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000002184 metal Substances 0.000 claims abstract description 65
- 229910052751 metal Inorganic materials 0.000 claims abstract description 65
- 229910008423 Si—B Inorganic materials 0.000 claims abstract description 40
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 36
- 239000000956 alloy Substances 0.000 claims abstract description 36
- 238000010438 heat treatment Methods 0.000 claims abstract description 34
- 229910018098 Ni-Si Inorganic materials 0.000 claims abstract description 30
- 229910018529 Ni—Si Inorganic materials 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 12
- 229910018100 Ni-Sn Inorganic materials 0.000 claims abstract description 7
- 229910018532 Ni—Sn Inorganic materials 0.000 claims abstract description 7
- 229910021484 silicon-nickel alloy Inorganic materials 0.000 claims abstract description 5
- 229910017082 Fe-Si Inorganic materials 0.000 claims abstract 4
- 229910017133 Fe—Si Inorganic materials 0.000 claims abstract 4
- 229910000808 amorphous metal alloy Inorganic materials 0.000 claims abstract 4
- 229910017091 Fe-Sn Inorganic materials 0.000 claims abstract 2
- 229910017142 Fe—Sn Inorganic materials 0.000 claims abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 229910052796 boron Inorganic materials 0.000 claims description 20
- 229910052742 iron Inorganic materials 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 15
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910020900 Sn-Fe Inorganic materials 0.000 claims 1
- 229910019314 Sn—Fe Inorganic materials 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 27
- 229910020220 Pb—Sn Inorganic materials 0.000 abstract description 21
- 238000005476 soldering Methods 0.000 abstract description 17
- 239000000203 mixture Substances 0.000 abstract description 12
- 238000006243 chemical reaction Methods 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 128
- 239000010408 film Substances 0.000 description 45
- 229910021332 silicide Inorganic materials 0.000 description 32
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 32
- 230000015572 biosynthetic process Effects 0.000 description 29
- 229910052718 tin Inorganic materials 0.000 description 16
- 229910000679 solder Inorganic materials 0.000 description 15
- 229910052759 nickel Inorganic materials 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 7
- 238000004458 analytical method Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 230000002265 prevention Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000000053 physical method Methods 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 229910000640 Fe alloy Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 238000010406 interfacial reaction Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910000521 B alloy Inorganic materials 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910020938 Sn-Ni Inorganic materials 0.000 description 1
- 229910008937 Sn—Ni Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012854 evaluation process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Laminated Bodies (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は金属積層体、特にSiチップとリード線とをP
b−Sn系半田付けにより強い接合力でオーミック接触
させるための金属積層体薄膜電極及びその製造方法に関
する。Detailed Description of the Invention (Industrial Field of Application) The present invention provides a metal laminate, especially a Si chip and a lead wire.
The present invention relates to a metal laminate thin film electrode for making ohmic contact with strong bonding force by b-Sn soldering, and a method for manufacturing the same.
(従来の技術)
近年半導体デバイスの開発・応用か盛んになりその信頼
性を確保する為に薄膜・表面・界面の諸物性研究の重要
性が増している。“マイクロソルダリングと言う言葉に
表わされる電子工業に於ける微小部の半田付けはその典
型的な例である。(Prior Art) In recent years, the development and application of semiconductor devices has become active, and in order to ensure their reliability, research on the physical properties of thin films, surfaces, and interfaces has become increasingly important. “Soldering of minute parts in the electronics industry, expressed by the term micro soldering, is a typical example.
マイクロソルダリングにはその応用面から(i)Si等
の半導体素子とリード線等の導体との接続、及び(11
)半導体やICパッケージの接合。Micro-soldering has applications such as (i) connecting semiconductor elements such as Si to conductors such as lead wires, and (11)
) Bonding of semiconductors and IC packages.
等かある。とくにSiに代表される半導体チップのセラ
ミックス基板への接合や、リード線とり出し用の半田付
けはデバイスの高信頼性の為にも最も重要な技術である
。There is something like that. In particular, the bonding of semiconductor chips typified by Si to ceramic substrates and the soldering for taking out lead wires are the most important techniques for achieving high reliability of devices.
Siチップの半田付けにはAu−Si、Au−C;e、
Au−3rr等のAu系共晶半田の他にpb−Sn系共
晶半田が用いられる。安価で生産性に富むことからPb
−Sn系半田の使用か一般的である。しかしPb−Sn
半田は直接S1チツプ上に接合出来ないことから現実に
はNi膜を介在させるか、更に高い信頼性を得る為には
T i / N i/ A u又はCr / N i
/ A u 3層構造膜を介して半田付けしている。こ
れらの電極の各構成元素の役割は、Ti、Cr等はSi
と反応し金属シリサイドを形成しオーミック接触を得る
もので、3層膜中間層のNiは半田中のSnのSiチッ
プ側への拡散を阻止し、Auは酸化防止と良好な半田付
は確保の為である。For soldering Si chips, Au-Si, Au-C; e,
In addition to Au-based eutectic solder such as Au-3rr, pb-Sn-based eutectic solder is used. Pb because it is cheap and highly productive
-Sn-based solder is commonly used. However, Pb-Sn
Since solder cannot be directly bonded onto the S1 chip, in reality, a Ni film is interposed, or in order to obtain even higher reliability, T i / Ni / A u or Cr / Ni
/ A u Soldered through a three-layer structure film. The role of each constituent element of these electrodes is as follows: Ti, Cr, etc.
Ni in the three-layer intermediate layer prevents Sn in the solder from diffusing toward the Si chip, and Au prevents oxidation and ensures good soldering. It is for this purpose.
(発明が解決しようとする問題点)
しかし、いずれの場合も、金属シリサイドとその上の金
属層との接合不良、高温雰囲気中での使用2通電に伴う
自己発熱によりSnのNi層中への拡散、さらには金属
層との界面への偏析によるは″く離2等の問題があった
。さらには多層電極の場合、生産性、コストの面で非常
に高くなるばかりかt隻数の界面を有することから各層
間の接合力不足等の問題が常にあった。その結果、Si
チップ上に金属膜を形成し、熱処理することによりオー
ミック接触を確保出来且つ半田付けにより強い接合力を
得ることの可能な金属積層体電極の出現が強く望まれて
いた。(Problems to be Solved by the Invention) However, in either case, Sn is absorbed into the Ni layer due to poor bonding between the metal silicide and the metal layer thereon, and due to self-heating due to use in a high-temperature atmosphere. There have been problems such as "delamination 2" due to diffusion and further segregation at the interface with the metal layer.Furthermore, in the case of multilayer electrodes, not only is the productivity and cost extremely high, but also the number of interfaces is large. As a result, there have always been problems such as insufficient bonding strength between each layer.
There has been a strong desire for the emergence of a metal laminate electrode that can ensure ohmic contact by forming a metal film on a chip and subjecting it to heat treatment, and can obtain strong bonding force by soldering.
(問題点を解決するための手段)
前述した様な理由から半導体デバイス用電極材、なかん
ずく自動車に搭載可能なS1デバイス用電極材には、(
1)半田層とSiとの間にオーミック接触が得られる。(Means for solving the problem) For the reasons mentioned above, electrode materials for semiconductor devices, especially electrode materials for S1 devices that can be installed in automobiles, are
1) Ohmic contact can be obtained between the solder layer and Si.
(it)少くとも150°C雰囲気下に於ける長時
間使用下でも半田中のSnの拡散が阻止されること、
(ill)強い接合力か?11られること1等の条件が
必要である。Pb−Sn系゛ト山付けか出来る金属とし
てはCu、Ni。(it) the diffusion of Sn in the solder is prevented even during long-term use in an atmosphere of at least 150°C;
(ill) Strong bonding force? 11 is required. Metals that can be plated with Pb-Sn are Cu and Ni.
Fe合金等が挙げられるが、Siとの間でシリサイドを
形成するものとしてはNi、Fe等である。しかしよく
知られているようにFeに1〜2%のCr、Si、Mo
などの不純物が混入すれば半田付けは極めて困難となる
。一方Ni合金のうち発明者らはNi・−Si又はNi
−Si−B合金が半田付は性にすぐれていることを見出
した。さらにこれらの合金はその組成範囲によってSn
の拡散速度に著しいt目迎があることも判明した。また
Ni−Si又はNi−Si−B合金又はFe金属はSi
チップとの間で安定したシリサイドを形成することも実
験的に確かめた。これらの事実からS i J:に特定
の組成領域のNi−Si又はNi−Si−B又はFe層
を形成し、その後の熱処理によるシリサイドの形成後、
半田付けすることによりSiチップからのリード線取り
出しを行えば、 S’iとの間にFe又はNiシリサ
イドが形成出来、Ni−Si若しくはN i−S i−
B合金又はFe金属層かSnの拡散を阻止又は減速し且
つ元来−層だけであったNi−Si又はNi−Si−B
又はFe層の両側からNi(又はFe)−Sn層、
Ni (又はFe)シリサイド層が成長したことにな
り不連続な界面の無い強固な接合を有する金属積層電極
が得られ本発明に至ったのである。Examples include Fe alloys, and materials that form silicide with Si include Ni, Fe, and the like. However, as is well known, 1 to 2% of Cr, Si, and Mo are added to Fe.
If such impurities are mixed in, soldering becomes extremely difficult. On the other hand, among Ni alloys, the inventors found that Ni.--Si or Ni
It has been found that -Si-B alloy has excellent soldering properties. Furthermore, depending on their composition range, these alloys contain Sn
It was also found that there was a significant change in the diffusion rate of t. In addition, Ni-Si or Ni-Si-B alloy or Fe metal is Si
It was also experimentally confirmed that stable silicide is formed between the material and the chip. From these facts, after forming a Ni-Si or Ni-Si-B or Fe layer with a specific composition range on SiJ: and forming silicide by subsequent heat treatment,
If lead wires are taken out from the Si chip by soldering, Fe or Ni silicide can be formed between it and S'i, and Ni-Si or Ni-Si-
B alloy or Fe metal layer or Ni-Si or Ni-Si-B which prevents or slows down the diffusion of Sn and was originally only a layer.
Or a Ni (or Fe)-Sn layer from both sides of the Fe layer,
As a result of the growth of the Ni (or Fe) silicide layer, a metal laminated electrode with strong bonding without discontinuous interfaces was obtained, leading to the present invention.
本発明の金属積層体はSnを含有する第1金属層とNi
(又はFe)とSnとを含有する第2金属層とNi−S
i又はNi−Si−B合金又はFe金属から成る第3金
属層とNi(又はFe)とSiとを含む第4金属層とか
ら成り該N 1−Si若しくはNi−Si−B合金又は
Fe金属から成る第3金属層は第2金属層から第4金属
層へのSnの拡散を阻止する層であることを特徴とする
。The metal laminate of the present invention includes a first metal layer containing Sn and a first metal layer containing Sn.
(or Fe) and a second metal layer containing Sn and Ni-S
a third metal layer comprising Ni or Ni-Si-B alloy or Fe metal; and a fourth metal layer comprising Ni (or Fe) and Si; The third metal layer is characterized in that it is a layer that prevents Sn from diffusing from the second metal layer to the fourth metal layer.
第1金属層C以下単に第1層と記す)とは少くともSn
を含有する金属のことをさす。すなわちSnは第1層の
必須成分である。第1層は少くとも数片子96以上のS
nを含有し、他の成分としてはPb、Cu、Sb、Ni
、In等を含有する半田、青銅、活字合金等の合金をさ
す。半導体分野での電極接合用半田としては通常Pb−
Sn合金が用いられておりSnを5〜90重−%、Pb
を10〜95重量%含有する。また、青銅は通常Cu−
Sn合金が用いられておりSnを2〜35重量%、Cu
を65〜98重量%含有する。また、活字合金は通・常
Pb−3b−Sn合金が用いられておりSnを1〜10
重量%、Pbを70〜94重量%、Sbを3〜20重量
%含有する第2層はNi(又はFe)とSnを必須成分
として含む金属である。第2層にはSnを20〜80原
子%含むほか、Si、B、Cu、Ag。The first metal layer C (hereinafter simply referred to as the first layer) is at least Sn
Refers to metals that contain That is, Sn is an essential component of the first layer. The first layer has at least a few pieces of S of 96 or higher.
Other components include Pb, Cu, Sb, and Ni.
Refers to alloys such as solder, bronze, and type alloys that contain , In, etc. Pb- is usually used as solder for electrode bonding in the semiconductor field.
Sn alloy is used, containing 5 to 90% by weight of Sn and Pb.
Contains 10 to 95% by weight. In addition, bronze is usually Cu-
Sn alloy is used, containing 2 to 35% by weight of Sn and Cu.
Contains 65 to 98% by weight. In addition, the type alloy is usually a Pb-3b-Sn alloy, and the Sn content is 1 to 10.
The second layer containing 70 to 94 weight % of Pb and 3 to 20 weight % of Sb is a metal containing Ni (or Fe) and Sn as essential components. The second layer contains 20 to 80 atomic % of Sn, as well as Si, B, Cu, and Ag.
In、Sb、等を2〜3原子%以下含むことかできる。It may contain 2 to 3 atomic % or less of In, Sb, etc.
第2層はSnを含む第1層とNt又はFeを含む第3層
とを接合する役割を果すものである。The second layer serves to bond the first layer containing Sn and the third layer containing Nt or Fe.
第3層はNi−Si合金又はN i−Si−B合金又は
Fe金属から成り本発明の金属積層体に於ける最も顕著
な技術的特徴である。Ni−Si−B合金がSnの拡散
防止層として働く組成領域を第1図に示す。第1図に於
ける領域■は28原子%≦Si+B≦50原子%且つS
i≧10原子%、領域■は20原子96≦Si+B<2
8原子%、且つSi≧10原子%、領域■は10原子%
≦Si十B<20原子%、且つB≦lO原子%である。The third layer is made of Ni-Si alloy, Ni-Si-B alloy, or Fe metal, and is the most prominent technical feature of the metal laminate of the present invention. FIG. 1 shows the composition range in which the Ni-Si-B alloy acts as a Sn diffusion prevention layer. Region ■ in Figure 1 is 28 atomic %≦Si+B≦50 atomic % and S
i≧10 at%, region ■ is 20 atoms 96≦Si+B<2
8 at%, and Si≧10 at%, region ■ is 10 at%
≦Si+B<20 atomic %, and B≦lO atomic %.
領域■、領域■、領域■はいずれもSnの拡散防止層と
しての役割を果たすがそれらの間の相違はSnの拡散防
止効果の程度である。つまり拡散防止能は■〉■〉■の
順である。Region (2), region (2), and region (2) all serve as Sn diffusion prevention layers, but the difference between them is the degree of Sn diffusion prevention effect. In other words, the diffusion prevention ability is in the order of ■>■>■.
また、Ni−Si合金の場合はSnの拡散防止に有効な
組成範囲はSi≦50原子%でありNi100%の場合
は除く。Further, in the case of a Ni-Si alloy, the effective composition range for preventing Sn diffusion is Si≦50 atomic %, excluding the case of 100% Ni.
さらに領域■、■、■はいずれもPb−Sn半田による
ぬれ性が良好で半田付は可能となる。Furthermore, the areas (1), (2), and (2) all have good wettability with Pb-Sn solder, and can be soldered.
Fe金属はFe又はFe合金(以下Feて代表する)か
ら成り、 C< 0.2重量%、Si<0.5重量
%、Mn<1重量%、 P< 0.03重量%、S
く0.03 mm%、 N i < 3重AM %+
Cr < 2重量%、Mo<Q、5重量%から成るも
のは、Snの拡散防止効果がある。Fe中に含まれる不
純物に関しては、Si基板との間でのシリサイド(Fe
ンリサイド)形成には問題ないが、Pb−Snとの反応
(半田付け)に影響し、各元素か−L、記は以−1−含
まれると十分な半田付は強度か得られない。Fe metal consists of Fe or Fe alloy (hereinafter referred to as Fe), C<0.2% by weight, Si<0.5% by weight, Mn<1% by weight, P<0.03% by weight, S.
0.03 mm%, N i < 3 AM %+
A material containing Cr<2% by weight, Mo<Q, and 5% by weight has an effect of preventing Sn diffusion. Regarding impurities contained in Fe, silicide (Fe
Although there is no problem in the formation of Pb--Sn (soldering), sufficient soldering strength cannot be obtained if each element (L) is included.
第4 FAはNi(又はFe)とSiとを含む金属層で
実質的にはNi(又はFe)シリサイド層である。Si
チップからオーミック接触でリード線をとり出すにはシ
リサイドの介在が不可欠である。Ni−Si−B又はN
i−Si合金層又はFe金属をSi上に成膜しその後の
固相−固相金属拡散によりNi(又はFe)シリサイド
層(第4層)を形成する。Ni−Si又はNi−Si−
B又はFeとSiとの間のシリサイドの成長はその成長
温度・シリサイドの形態に於いて通常の100%N1と
の反応の場合とは若干異なるが。The fourth FA is a metal layer containing Ni (or Fe) and Si, and is substantially a Ni (or Fe) silicide layer. Si
Interposition of silicide is essential in order to take out the lead wires from the chip through ohmic contact. Ni-Si-B or N
An i-Si alloy layer or Fe metal is formed on Si, and then a Ni (or Fe) silicide layer (fourth layer) is formed by solid phase-solid phase metal diffusion. Ni-Si or Ni-Si-
The growth of silicide between B or Fe and Si is slightly different from the normal reaction with 100% N1 in terms of the growth temperature and the form of the silicide.
オーミック性には全く問題なくSiとNi合金層又はF
e金属層との間に強固な接合が得られる。There is no problem with ohmic properties, and Si and Ni alloy layers or F
e A strong bond can be obtained between the metal layer and the metal layer.
本発明の技術的特徴である第3層の厚さは0.05μm
〜20μmとすることが好ましい。The thickness of the third layer, which is a technical feature of the present invention, is 0.05 μm
It is preferable to set it to 20 micrometers.
0.05μm未満ではSnの拡散防止能が不十分であり
20μmを超えると内部応力によりはく離が生じ易い。If it is less than 0.05 μm, the ability to prevent Sn diffusion is insufficient, and if it exceeds 20 μm, peeling is likely to occur due to internal stress.
本発明の金属積層体は次の2通りの方法により製造され
る。第1の方法はまず清浄化されたn形又はn形のSi
基板に物理的手法(例えばスパッタリング、真空蒸着、
イオンブレーティング等)によりNi−Si又はNi−
Si−B又はFe膜を形成し、その後に固相−固相の金
属間相互拡散の生じる温度で焼鈍し、界面にNi(又は
Fe)シリサイドを形成する。この場合焼鈍条件を、未
反応のNi−Si又はNi−Si−B又はFe層が残存
するように選ぶことが肝要である。その後S nを含む
合金L4を物理的手法(スパッタリング、真空蒸石、イ
オンブレーティング等)又は化学的手法(メッキ法等)
により形成しその後に固相−固相又は固相−液相の金属
間相互拡散の生じるm度で焼鈍し界面にNi(又はFe
) −Sn層を形成する。The metal laminate of the present invention is manufactured by the following two methods. The first method is to first use cleaned n-type or n-type Si.
Apply physical methods (e.g. sputtering, vacuum evaporation,
Ni-Si or Ni-
A Si-B or Fe film is formed and then annealed at a temperature at which solid phase-solid intermetallic diffusion occurs to form Ni (or Fe) silicide at the interface. In this case, it is important to select annealing conditions such that an unreacted Ni-Si, Ni-Si-B, or Fe layer remains. After that, alloy L4 containing Sn is applied using physical methods (sputtering, vacuum evaporation, ion blating, etc.) or chemical methods (plating method, etc.).
Ni (or Fe
) - Form a Sn layer.
次いで第2の製造方法を示す。まず清浄化されたn形又
はn形のSi基板上に物理的手法(例えばスパッタリン
グ、2!空蒸着、イオンブレーティング等)によりNi
−Si又はNi−Si−B又はFe膜を形成し、続いて
物理的手法又はメッキ等の化学的手法によりSnを含む
合金層を形成する。その後に固相−固tIj又は固相−
液相の金属間相互拡散の生じる温度で焼鈍し、Si基板
とN1−Si又はNi−Si−B又はFeとの界面にN
i(又はFe)シリサイド層をさらにNi−Si又はN
i−Si−B合金又はFe金属とSnを含む合金層との
界面にNi(又はFe)−Sn層を同時に形成する。こ
こで大切なことはNi(又はFe)シリサイド層及びN
i(又はFe)−S n IAの成長速度を充分考慮し
焼鈍温度を決定することである。Next, a second manufacturing method will be described. First, Ni is deposited on a cleaned n-type or n-type Si substrate by a physical method (e.g., sputtering, empty evaporation, ion blating, etc.).
-Si or Ni-Si-B or Fe film is formed, and then an alloy layer containing Sn is formed by a physical method or a chemical method such as plating. Then solid phase - solid tIj or solid phase -
Annealed at a temperature at which intermetallic interdiffusion occurs in the liquid phase, and N is added to the interface between the Si substrate and N1-Si or Ni-Si-B or Fe.
i (or Fe) silicide layer further Ni-Si or N
A Ni (or Fe)-Sn layer is simultaneously formed at the interface between the i-Si-B alloy or Fe metal and the alloy layer containing Sn. What is important here is the Ni (or Fe) silicide layer and the N
The annealing temperature should be determined by fully considering the growth rate of i (or Fe)-S n IA.
いずれにせよ最終的にはSnを含有する第1層、 Ni
(又はFe)−Sn合金から成る第2層、Ni−S
i又はNi−Si−B又はFeから成る第3層、及びN
i(又はFe)シリサイド層を形成する第4層から成る
ことを特徴とする金属積層体となる。In any case, the final layer containing Sn, Ni
(or Fe)-Sn alloy, Ni-S
a third layer consisting of i or Ni-Si-B or Fe, and N
The metal laminate is characterized by comprising a fourth layer forming an i (or Fe) silicide layer.
第1層がPb−Sn合金で第2層がNi−Si−B合金
の場合、Pbは両合金層間の反応に関与せず2反応層度
はNi−Si−B膜中のSiとBの量の増加に1′1′
って減少する。P b −S n / N 1−Si−
B界面反応は150℃以上の温度で生じ得るが、半田の
ぬれ性などの理由から2通常330°C以上で行うのが
よい。When the first layer is a Pb-Sn alloy and the second layer is a Ni-Si-B alloy, Pb does not participate in the reaction between the two alloy layers, and the degree of reaction between Si and B in the Ni-Si-B film is 1'1' for increase in quantity
It decreases. Pb-Sn/N1-Si-
Although the interfacial reaction (B) can occur at a temperature of 150° C. or higher, it is usually preferably carried out at a temperature of 330° C. or higher for reasons such as solder wettability.
また、Ni−Si−B合金層とSi基板との界面反応で
Niシリサイドを得るには2合金組成により若干異なる
が1通常300℃以」二の温度にするのがよい。しかし
、400〜450°C以上ではNi−Si−Bが結晶化
し、SiデバイスてはAで配線の断線も生じるので、結
局300〜450℃の反応温度が好ましい。Further, in order to obtain Ni silicide through an interfacial reaction between the Ni-Si-B alloy layer and the Si substrate, the temperature is preferably 1, usually 300° C. or higher, although it varies slightly depending on the composition of the two alloys. However, at temperatures above 400 to 450°C, Ni-Si-B crystallizes and disconnection of wiring occurs at A in Si devices, so a reaction temperature of 300 to 450°C is preferable.
以上の理由から、Ni−Si−B合金の組成は半田付は
最適71u度(330〜400°C)てpb−8n/N
i−Si−B界面で適当に(あまり反応が進み形成層が
厚くなるともろくなる)反応層が形成されるように選択
する必要があり、シリサイドの形成温度は300〜45
0°Cが望ましい。For the above reasons, the composition of the Ni-Si-B alloy is pb-8n/N for soldering at 71u degrees (330-400°C).
It is necessary to select so that a reaction layer is appropriately formed at the i-Si-B interface (the layer becomes brittle as the reaction progresses and the layer becomes thicker), and the silicide formation temperature is 300 to 45°C.
0°C is desirable.
従って、第1の製造法ではそれぞれの独立に最適熱処理
して第2層及び第4層を形成すれば良いが、第2の製造
法ではその処理温度とNi−Si−Bの組成を適切に選
択する必要がある。Therefore, in the first manufacturing method, it is sufficient to form the second and fourth layers by performing optimal heat treatment on each layer independently, but in the second manufacturing method, the treatment temperature and the Ni-Si-B composition are appropriately adjusted. You need to choose.
例えば、第2の製造法で熱処理温度T−320℃の時シ
リサイド層形成速度D とSn−1−9j
Ni層形成速度D とを比較すると、−役に1−S
n
Ni−Si N1−Snとなる。ここでNi−Si
−D くくD
B合金中のSt、Buを増加させるとD が1−S
n
遅くなるのでD <D 又はDNi−3t
Ni−Sn Ni−Si ’DNi−S
nとすることができる。For example, when comparing the silicide layer formation rate D and the Sn-1-9j Ni layer formation rate D when the heat treatment temperature is T-320°C in the second manufacturing method, it is found that -1-S
n Ni-Si N1-Sn. Here, Ni-Si
-D KukuD When St and Bu in B alloy are increased, D becomes 1-S
n becomes slower, so D < D or DNi-3t
Ni-Sn Ni-Si 'DNi-S
It can be n.
又T−400℃とするとD も速くなるがNi−S
i
D も極めて速くなる。そこでSi、BQNi−S
n
を更に増加させD の反応を押えDNi−Si ”
1−8n
D と出来る。Also, when T-400℃, D becomes faster, but Ni-S
i D also becomes extremely fast. Therefore, Si, BQNi-S
By further increasing n and suppressing the reaction of D, DNi-Si”
It can be done as 1-8n D.
1−Sn
本発明の用途例としては大電流を流すパワートランジス
タ又はダイオード用Siチップからの半田付けによるリ
ード線のとり出しに用いることができる。これらの半導
体デバイスは、具体的には自動車用ICとしてイグナイ
ター制御用又はオールタネータ制御用等に利用される。1-Sn As an example of the application of the present invention, it can be used to take out lead wires by soldering from Si chips for power transistors or diodes that conduct large currents. These semiconductor devices are specifically used as automotive ICs for controlling an igniter or an alternator.
(作用及び効果)
Snを含む第1金属層とNi(又はFe)−Sn合金か
ら成る第2金属層とN i−Si又はNi−Si−B又
はFe合金から成る第3層とNi(又はFe)シリサイ
ドから成る第4層とから成る金属積層体の作用効果につ
いて記述する。(Operations and Effects) A first metal layer containing Sn, a second metal layer consisting of a Ni (or Fe)-Sn alloy, a third layer consisting of Ni-Si, Ni-Si-B, or Fe alloy, and a Ni (or The effects of the metal laminate including the fourth layer made of Fe) silicide will be described.
本発明の金属積層体における最も顕著な技術的特徴であ
るNi−Si又はNi−Si−B又はFe層(第3層)
の役割を中心に説明する。Si基板からのPb−8n系
半田によるリード線の取り出しには通常Ni膜が用いら
れる。しかしSnはNi中を比較的低温(約150’C
)で拡散することからSiデバイスの使用lH度環境に
よってはSnの拡散がlヒまらす進行し、トラブルを誘
発する。Ni膜にSi又はSi+Bを添加することによ
り膜のミクロな構造が著しく変化しSnとの相互拡散に
影響することが判明した。さらにSiとBの合計量を5
0原子%以下にすればPb−Sn系半田とのぬれ性も良
好でNi膜のSi+B又はSiQを、’l!14iする
ことによりSn−Ni反応層の成長が制御出来る。また
Fe膜においても類似の効果が見られた。一方Si基板
との間でNi(又はFe)シリサイドを形成しオーミッ
ク性を確保することが必要であるがNi−Si又はNi
−Si−B又はFe膜とSiとの界面反応により安定し
たシリサイドを形成し、Bは反応に関与しない。この様
にNi−Si又はNi−Si−B又はFe層はSiとの
間でのNi(又はFe)シリサイド形成、Sn−Ni(
又はFe)合金層の形成、及びSnの拡散を阻IL又は
制御すると言う合513つの役割を単一層で同時に実現
するものである。また、 Ni (又はFe)−Sn
層、Ni−Si又はNi−Si−B又はFe層及びNi
(又はFe)シリサイド層は元来単一層から成るもので
不連続な界面は存在せず接合性は万全である。Ni-Si or Ni-Si-B or Fe layer (third layer) which is the most remarkable technical feature of the metal laminate of the present invention
We will mainly explain the role of A Ni film is usually used to take out lead wires from a Si substrate using Pb-8n solder. However, Sn exists in Ni at a relatively low temperature (approximately 150'C).
), so depending on the temperature environment in which the Si device is used, the diffusion of Sn may slow down and cause trouble. It has been found that by adding Si or Si+B to a Ni film, the microstructure of the film changes significantly, which affects interdiffusion with Sn. Furthermore, the total amount of Si and B is 5
If the content is 0 atomic % or less, the wettability with Pb-Sn solder is good, and the Si+B or SiQ of the Ni film is 'l! 14i, the growth of the Sn--Ni reaction layer can be controlled. A similar effect was also observed in the Fe film. On the other hand, it is necessary to form Ni (or Fe) silicide between the Si substrate and ensure ohmic properties.
- A stable silicide is formed by an interfacial reaction between Si--B or Fe film and Si, and B does not participate in the reaction. In this way, the Ni-Si, Ni-Si-B, or Fe layer forms Ni (or Fe) silicide with Si, and Sn-Ni (
A single layer simultaneously fulfills three roles: forming an alloy layer (or Fe) and inhibiting or controlling Sn diffusion. Also, Ni (or Fe)-Sn
layer, Ni-Si or Ni-Si-B or Fe layer and Ni
The (or Fe) silicide layer is originally composed of a single layer, so there is no discontinuous interface and the bonding property is perfect.
この様に本発明の金属積層体及びその製造方法によりコ
スト、生産性、特性(熱安定性)のいずれも従来品に比
して著しく改善することが可能となった。As described above, the metal laminate and the method for producing the same of the present invention have made it possible to significantly improve cost, productivity, and properties (thermal stability) compared to conventional products.
(実施例)
本発明の金属積層体の作製法・評価プロセスについてそ
の共通した条件を以下に示す。用いたSi基板は10
”’am−3程度にボロンをドープしたp形(111)
ウェハーでその表面は鏡面に仕上げられ抵抗率は約12
0Ω・cmである。Si基基土上室温にてDC又はRF
マグネトロンスパッタ法によりNi−Si又はNi−S
i−8合金膜を約10000人層する。その後は二通り
の方法により処理される。つまり第1の方法はNf−S
i又はNi−Si−B又はFe膜形成後、300℃〜4
50℃の範囲で膜組成に応じた温度を選び。(Example) Common conditions for the manufacturing method and evaluation process of the metal laminate of the present invention are shown below. The Si substrate used was 10
``p type (111) doped with boron to about am-3
The surface of the wafer is mirror-finished and the resistivity is approximately 12.
It is 0Ω·cm. DC or RF on Si-based substrate at room temperature
Ni-Si or Ni-S by magnetron sputtering method
Approximately 10,000 layers of i-8 alloy film will be applied. Thereafter, it is processed in two ways. In other words, the first method is Nf-S
After forming i or Ni-Si-B or Fe film, 300℃~4
Select a temperature within the range of 50°C according to the film composition.
真空中で約1時間の熱処理を施こしNi−Si/Si又
はNi−Si−B/Si又はFe/Si界而にN界面S
iの拡散(Niシリサイドの拡散層)又はFeシリサイ
ドの拡散層を形成する。次いでPb−Sn合金膜を約1
0000人の厚さにDC又はRFマグネトロンスパッタ
法により形成し、再び300℃〜450°Cの温度範囲
で真空中で10分〜60分の熱処理を施こしPb−Sn
合金/ N i −S i又はNi−Si−B又はFe
界面1:、Ni(叉はFe)−Snの拡散層を形成する
。Heat treatment is performed in vacuum for about 1 hour to form an N interface between Ni-Si/Si or Ni-Si-B/Si or Fe/Si.
A diffusion layer of i (Ni silicide diffusion layer) or Fe silicide diffusion layer is formed. Next, the Pb-Sn alloy film is
Pb-Sn was formed to a thickness of 0,000 mm by DC or RF magnetron sputtering, and then heat-treated in a vacuum for 10 to 60 minutes at a temperature range of 300°C to 450°C.
Alloy/Ni-Si or Ni-Si-B or Fe
Interface 1: Form a Ni (or Fe)-Sn diffusion layer.
第2の方法はNi−Si又はNi−Si−B又はFe膜
上に続いてPb−Sn膜を形成し、その後に一括して熱
処理を施こしPb−Sn合金/Ni−Si又はNi−S
i−B又はFe界面にNi(又はFe)−Snの拡散層
を、またNi−Si又はNi−Si−B又はF e /
S i界面にNi(又はFe)シリサイドの拡散層を
形成するものである。The second method is to form a Pb-Sn film on the Ni-Si, Ni-Si-B, or Fe film, and then perform heat treatment all at once to form a Pb-Sn alloy/Ni-Si or Ni-S
A Ni (or Fe)-Sn diffusion layer is provided at the i-B or Fe interface, and a Ni-Si or Ni-Si-B or Fe/
A diffusion layer of Ni (or Fe) silicide is formed at the Si interface.
尚熱処理方法の詳細は以下に示す通りである。つまり3
00 ’C〜450°Cに保持された10−”Torr
以下の真空雰囲気中に試料を挿入し10〜60分保持し
、その後室温に戻る迄同一真空中に保持しその後大気中
にとり出した。この方法では試料が所定の温度に達する
のに2−3分を要すことから実際には熱処理時間がその
分だけ若干短くなる。The details of the heat treatment method are as shown below. That is 3
10-” Torr held at 00’C to 450°C
A sample was inserted into the following vacuum atmosphere and held there for 10 to 60 minutes, then held in the same vacuum until the temperature returned to room temperature, and then taken out into the atmosphere. In this method, it takes 2-3 minutes for the sample to reach a predetermined temperature, so the heat treatment time is actually slightly shorter by that amount.
上記方法により作製した本発明の金属積層体の断面構造
を第2図に示す。又対応するオージェ電子分析によりP
b−Sn合金表面から内部への深さ方向元素分布分析結
果の線図を第3図に例示する。第3図から第2層はNi
−Snから又第4層はNi−Si(Niシリサイド)か
ら成っていることが判る。FIG. 2 shows the cross-sectional structure of the metal laminate of the present invention produced by the above method. Also, by corresponding Auger electron analysis, P
FIG. 3 illustrates a diagram of the results of depth direction element distribution analysis from the surface of the b-Sn alloy to the inside. From Figure 3, the second layer is Ni.
It can be seen from -Sn that the fourth layer is made of Ni-Si (Ni silicide).
電極としての評価はオーミック性(5に、良。The evaluation as an electrode is ohmic (5, good).
可、不可で評価)、Pb−Sn膜又は半田のぬれ性(優
、Q、可、不可で評価)、及び接着力(優、良、可、不
可で評価)とで行った。オーミック性の良ψ不良はNi
−Si層(第4層Niシリサイド層)の形成と、又ぬれ
性はNi−Sn層(第2層)の形成と対応している。Pb-Sn film or solder wettability (evaluated as excellent, Q, fair, poor), and adhesive strength (evaluated as excellent, good, fair, poor). Good and bad ohmic properties are Ni
The formation of the -Si layer (fourth Ni silicide layer) and the wettability correspond to the formation of the Ni--Sn layer (second layer).
優、良、可、不可の基準はそれぞれ次のようである。The criteria for excellent, good, fair, and poor are as follows.
■オーミック性に関しては、電流と電圧とのりニアリテ
ィと、接触抵抗との関連について述べる必要があるが、
ここでは、接触抵抗で判定した。■ Regarding ohmic properties, it is necessary to discuss the relationship between current, voltage, linearity, and contact resistance.
Here, the determination was made based on contact resistance.
接触抵抗 数m07口以下 、 優
数10mΩ/口程度: 良
数Ω/口程度 : rIJ
10Ω/口以」−二 不可
■ハンダのぬれに関しての評価は、接触角により判定し
た。Contact resistance: Several meters or less, about 10 mΩ/mouth: Good number: about 10 mΩ/mouth: rIJ 10 Ω/mouth: rIJ 10Ω/mouth”-2 Not possible ■Evaluation of solder wetting was determined based on the contact angle.
接触角 10’以下 : 優 10〜300:良 30〜80’:可 80’以上 : 不可 ■接着力についての判定は 接着力 7 kg / mm 以上: 優2゜ 7〜4kg/+++n+ 、良 2゜ 4〜1kg/m+a 、可 1 kg / mm 以下: 不可 とした。Contact angle 10' or less: Excellent 10-300: Good 30-80': Possible 80' or above: Not possible ■Judgment about adhesive strength Adhesive strength 7 kg/mm or more: Excellent 2° 7-4kg/+++n+, good 2゜ 4-1kg/m+a, possible 1 kg / mm or less: Not possible And so.
以下に実施例1〜12及びNi−Snの拡散層が形成さ
れていない比較例1.Niシリサイドの拡散層とNi−
Snの拡散層が形成されていない比較例2を示す。また
、これらの評価結果は第1表に示す。Examples 1 to 12 and Comparative Example 1 in which a Ni-Sn diffusion layer was not formed are shown below. Ni silicide diffusion layer and Ni-
Comparative Example 2 in which a Sn diffusion layer is not formed is shown. Moreover, these evaluation results are shown in Table 1.
実施例1
第3層製j漠:N1−15原子%Si−25原子%B、
5000人↓
熱処理:400°C,1時間、真空中
↓
Pb−Sn層製膜:Pb−10屯W%Sn、 too
oo人↓
熱処理=300°C230分、真空中
実施例2
第3層製膜:Ni−15原子%Si−25原子%r3.
5000人↓
Pb−Sn層製膜、Pb−10重QXSn、 100
00人↓
熱処理・350℃、1時間、真空中
実施例3
第3層製膜:Nj−35原子%Si−10原子%B、
5000人↓
熱処理:450°C,1時間、真空中
↓
Pb−Sn層製膜:Pb−10重Q%Sn、 100
00人ハ処理:300°C130分、真空中
実施例4
第3層製膜:Ni−15原子%Si−10原子%B、
5000人↓
熱処理:380℃、1時間、真空中
Pl)−8n層製膜:Pb−10市H%Sn、 10
000人↓
熱処理=300°C130分、真空中
実施例5
第3層製膜:Nj−20原子%Si−5原子%B、 5
000人↓
Pb−Sn層製膜:Pb−10重量%Sn、 100
00人↓
熱処理:330°C,1時間、真空中
実施例6
第3層装膜:Ni−12原子%Si−4原子%B、 5
000人↓
熱処理=350°C,1時間、真空中
Pb −Snn層膜膜 Pb−10重u%sn、 1
0000人↓
熱処理、300℃、30分、真空中
実施例7
第3層装膜:Ni−7原子96Si−7原子%B、 5
000人↓
Pb −Snn層膜膜Pb−10重二%Sn、 100
00人↓
熱処理:300℃、30分、真空中
実施例8
第3層製膜:Ni−42原子%Si、5000人↓
熱処理:400℃、1時間、真空中
↓
Pb−8n層裂膜:Pb−10重Q%Sn、 100
00人↓
熱処理、300℃、30分、真空中
実施例9
第3層製膜:Nl−251皇子%St、5000人熱処
理=350℃、1時間、真空中
↓
Pb −Snn層膜膜Pb−10iT+fa%Sn、
10000人↓
熱処理=300°C130分、真空中
実施例10
第3層製膜:Ni−15原子%Si
↓
熱処理:300℃、1時間、真空中
↓
Pb−Sn層製膜:Pb−10重量%Sn、toooo
入善
熱処理=300℃、30分、真空中
実施例11
第3層製膜:Ni−15原子%S!、5000人↓
Pb−Sn層製膜:Pb−10重−%Sn、 100
00人↓
熱処理=300°C,1時間、真空中
実施例12
第3層製膜: FQ 5000人
↓
Pb−Sn層製膜: Pb−10重u%sn、 10
000人工
熱処理:300’C,1時間、真空中
比較例1
第3層製膜・Ni−15原子%Si−15原子%B、
5000人↓
熱処理:400°C,1時間、真空中
↓
Pb−Sn層製膜:Pb−10重量%Sn、10000
人比較例2
第3層製膜:N1−15原子%Si−15原子%13.
5000人↓
Pb−Sn層製膜:Pb−10重量%Sn、 1000
0人尚実施例1〜12の金属績iA体を150°Cの大
気中に4週間放置しNi−Si、又はNi−Si−B又
はFe層の拡散防止効果をオージェ電子分析により、凋
べたところSnの拡散は全く見られず1本発明の実施例
はいずれも高温耐久性を宵することが判った。Example 1 Third layer composition: N1-15 atomic% Si-25 atomic% B,
5000 people ↓ Heat treatment: 400°C, 1 hour, in vacuum ↓ Pb-Sn layer film formation: Pb-10 tons W%Sn, too
oo person ↓ Heat treatment = 300°C, 230 minutes, in vacuum Example 2 Third layer film formation: Ni-15 atomic% Si-25 atomic% r3.
5000 people ↓ Pb-Sn layer film formation, Pb-10 heavy QXSn, 100
00 people ↓ Heat treatment, 350°C, 1 hour, in vacuum Example 3 3rd layer film formation: Nj-35 atomic% Si-10 atomic% B,
5000 people ↓ Heat treatment: 450°C, 1 hour, in vacuum ↓ Pb-Sn layer film formation: Pb-10 weight Q%Sn, 100
00 people Processing: 300°C, 130 minutes, in vacuum Example 4 Third layer film formation: Ni-15 atomic% Si-10 atomic% B,
5000 people ↓ Heat treatment: 380°C, 1 hour, in vacuum Pl)-8n layer film formation: Pb-10 city H%Sn, 10
000 people ↓ Heat treatment = 300°C, 130 minutes, in vacuum Example 5 3rd layer film formation: Nj-20 at.% Si-5 at.% B, 5
000 people ↓ Pb-Sn layer film formation: Pb-10wt%Sn, 100
00 people ↓ Heat treatment: 330°C, 1 hour, in vacuum Example 6 Third layer coating: Ni-12 atomic%Si-4 atomic%B, 5
000 people ↓ Heat treatment = 350°C, 1 hour in vacuum Pb-Snn layer film Pb-10w%sn, 1
0,000 people ↓ Heat treatment, 300°C, 30 minutes, in vacuum Example 7 Third layer film: Ni-7 atoms 96 Si-7 atoms % B, 5
000 people ↓ Pb-Snn layer film Pb-10 double% Sn, 100
00 people ↓ Heat treatment: 300°C, 30 minutes, in vacuum Example 8 Third layer film formation: Ni-42 atomic % Si, 5000 people ↓ Heat treatment: 400°C, 1 hour, in vacuum ↓ Pb-8n delaminated film: Pb-10 weight Q%Sn, 100
00 people ↓ Heat treatment, 300°C, 30 minutes, in vacuum Example 9 Third layer film formation: Nl-251 Oji%St, 5000 people Heat treatment = 350°C, 1 hour, in vacuum ↓ Pb -Snn layer film Pb- 10iT+fa%Sn,
10,000 people ↓ Heat treatment = 300°C, 130 minutes, in vacuum Example 10 3rd layer film formation: Ni-15 atomic% Si ↓ Heat treatment: 300°C, 1 hour, in vacuum ↓ Pb-Sn layer film formation: Pb-10 weight %Sn, toooo
Nyuzen heat treatment = 300°C, 30 minutes, in vacuum Example 11 Third layer film formation: Ni-15 atomic% S! , 5000 people ↓ Pb-Sn layer film formation: Pb-10 weight-%Sn, 100
00 people ↓ Heat treatment = 300°C, 1 hour, in vacuum Example 12 3rd layer film formation: FQ 5000 people ↓ Pb-Sn layer film formation: Pb-10w%sn, 10
000 Artificial heat treatment: 300'C, 1 hour, in vacuum Comparative Example 1 Third layer film formation: Ni-15 atomic% Si-15 atomic% B,
5,000 people ↓ Heat treatment: 400°C, 1 hour, in vacuum ↓ Pb-Sn layer film formation: Pb-10 wt% Sn, 10,000
Human Comparative Example 2 3rd layer film formation: N1-15 atomic% Si-15 atomic% 13.
5000 people ↓ Pb-Sn layer film formation: Pb-10wt%Sn, 1000
The metal specimens of Examples 1 to 12 were left in the atmosphere at 150°C for 4 weeks, and the diffusion prevention effect of the Ni-Si, Ni-Si-B, or Fe layer was determined by Auger electron analysis. However, no diffusion of Sn was observed, and it was found that all the examples of the present invention had good high-temperature durability.
また、従来技術との比較例として第3層にN1100%
層(5000人)を採用したところ、シリサイド形成、
Ni−Sn層の形成ノ(に正常であったが、150℃の
大気中で1週間放置すると、SnはNi−Sn層を通過
して未反応Ni領域に拡散しNiシリサイドとSi基板
との界面にまで拡散することがオージェ電子分析によっ
て明らかになった。In addition, as a comparative example with the conventional technology, the third layer contains 1100% N.
layer (5000 people), silicide formation,
The formation of the Ni-Sn layer was normal, but when left in the atmosphere at 150°C for one week, Sn passes through the Ni-Sn layer and diffuses into the unreacted Ni region, causing a bond between the Ni silicide and the Si substrate. Auger electron analysis revealed that it diffuses to the interface.
尚1本発明の実施例1〜12の電極に関してその熱的安
定性を150°Cの大気中にて、放置又は電流の0N1
0FFをくり返しながら1〜2週IHI継続したか、電
極部分のオーミック接触性1層間密也−性ともに全く変
化が見られなかった。これは電極作製時の300°C以
上の熱処理履歴により本発明の電極構造が安定化されて
いることによるものである。1 The thermal stability of the electrodes of Examples 1 to 12 of the present invention was evaluated by leaving them in the atmosphere at 150°C or by applying a current of 0N1.
IHI was continued for 1 to 2 weeks while repeating 0FF, and no change was observed in both the ohmic contact and interlayer density of the electrode portion. This is because the electrode structure of the present invention is stabilized by the history of heat treatment at 300° C. or higher during electrode production.
第1図は本発明の金炙積層体の第3層の組成範囲、第2
図は本発明の金属積層体の断面構造(実施例1〜12)
、第3図は第2図構造に対応するオージェ電子分析結果
の代表例(深さ方向分布)(実施例1〜8)、第4図は
本発明の金属積層体の第1の製造方法、第5図は本発明
の金属積層体の第2の製造方法を示す。Figure 1 shows the composition range of the third layer of the gold-broiled laminate of the present invention, and the composition range of the second layer.
The figure shows the cross-sectional structure of the metal laminate of the present invention (Examples 1 to 12)
, FIG. 3 shows a typical example of Auger electron analysis results (depth direction distribution) corresponding to the structure shown in FIG. 2 (Examples 1 to 8), FIG. 4 shows the first manufacturing method of the metal laminate of the present invention, FIG. 5 shows a second method of manufacturing a metal laminate according to the present invention.
Claims (10)
−Ni合金又はSn−Fe合金から成る第2層と、Ni
−Si若しくはNi−Si−Bアモルファス合金又はF
e金属から成る第3層と、Ni−Si又はFe−Si合
金から成る第4層と、Si基板から成ることを特徴とす
る金属積層体。(1) Sequentially from the surface: a first layer made of Sn alloy;
- a second layer made of Ni alloy or Sn-Fe alloy;
-Si or Ni-Si-B amorphous alloy or F
A metal laminate comprising a third layer made of e-metal, a fourth layer made of Ni-Si or Fe-Si alloy, and a Si substrate.
子%であることを特徴とする特許請求の範囲第1項記載
の金属積層体。(2) The metal laminate according to claim 1, wherein the Ni-Si alloy has a Si content of 10 to 50 atomic %.
子%であることを特徴とする特許請求の範囲第2項記載
の金属積層体。(3) The metal laminate according to claim 2, wherein the Ni-Si alloy has a Si content of 10 to 28 at.%.
0〜50原子%含むことを特徴とする特許請求の範囲第
1項記載の金属積層体。(4) The Ni-Si-B alloy contains Si and B in a total amount of 1
The metal laminate according to claim 1, characterized in that the metal laminate contains 0 to 50 atom %.
8〜50原子%含み、かつSiを10原子%以上含むこ
とを特徴とする特許請求の範囲第4項記載の金属積層体
。(5) The Ni-Si-B alloy contains Si and B in a total amount of 2
The metal laminate according to claim 4, characterized in that the metal laminate contains 8 to 50 atomic % and 10 atomic % or more of Si.
0〜28原子%含み、かつSiを10原子%以上含むこ
とを特徴とする特許請求の範囲第4項記載の金属積層体
。(6) The above Ni-Si-B alloy contains Si and B in a total amount of 2
The metal laminate according to claim 4, characterized in that the metal laminate contains 0 to 28 atomic % and 10 atomic % or more of Si.
0〜20原子%含み、かつBを10原子%以下含むこと
を特徴とする特許請求の範囲第4項記載の金属積層体。(7) The above Ni-Si-B alloy contains Si and B in a total amount of 1
The metal laminate according to claim 4, characterized in that the metal laminate contains 0 to 20 atomic % and 10 atomic % or less of B.
特徴とする特許請求の範囲第1項記載の金属積層体。(8) The metal laminate according to claim 1, wherein the Fe metal does not substantially contain impurities.
アモルファス合金又はFe金属からなる第3層を形成し
、熱処理によりSi基板と第3層の界面に、Ni−Si
又はFe−Si合金からなる第4層を形成し、その後第
3層の表面にSn合金からなる第1層を形成し、熱処理
により第1層と第3層の界面に、Ni−Sn又はFe−
Sn合金層からなる第2層を形成することを特徴とする
金属積層体の製造方法。(9) Ni-Si or Ni-Si-B on a Si substrate
A third layer made of an amorphous alloy or Fe metal is formed, and a Ni-Si layer is formed at the interface between the Si substrate and the third layer by heat treatment.
Alternatively, a fourth layer made of Fe-Si alloy is formed, and then a first layer made of Sn alloy is formed on the surface of the third layer, and Ni-Sn or Fe is added to the interface between the first and third layers by heat treatment. −
A method for manufacturing a metal laminate, comprising forming a second layer made of an Sn alloy layer.
Bアモルファス合金又はFe金属からなる第3層を形成
し、その表面にSn合金からなる第1層を形成し、その
後、熱処理により第1層と第3層の界面にNi−Sn又
はFe−Sn合金からなる第2層、および第3層とSi
基板の界面に、Ni−Si又はFe−Si合金層からな
る第4層を形成することを特徴とする金属積層体の製造
方法。(10) Ni-Si or Ni-Si-
A third layer made of B amorphous alloy or Fe metal is formed, a first layer made of Sn alloy is formed on the surface thereof, and then Ni-Sn or Fe-Sn is formed at the interface between the first layer and the third layer by heat treatment. A second layer made of an alloy and a third layer made of Si
A method for manufacturing a metal laminate, comprising forming a fourth layer made of a Ni-Si or Fe-Si alloy layer at an interface of a substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20545786A JPS6360537A (en) | 1986-09-01 | 1986-09-01 | Metallic laminate and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20545786A JPS6360537A (en) | 1986-09-01 | 1986-09-01 | Metallic laminate and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6360537A true JPS6360537A (en) | 1988-03-16 |
Family
ID=16507195
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20545786A Pending JPS6360537A (en) | 1986-09-01 | 1986-09-01 | Metallic laminate and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6360537A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5306950A (en) * | 1991-12-26 | 1994-04-26 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Electrode assembly for a semiconductor device |
US5635764A (en) * | 1992-12-10 | 1997-06-03 | Nippondenso Co., Ltd. | Surface treated structure for solder joint |
JP2009016468A (en) * | 2007-07-03 | 2009-01-22 | Sony Corp | Solder joint structure and solder bump forming method |
JP2011187782A (en) * | 2010-03-10 | 2011-09-22 | Mitsubishi Electric Corp | Semiconductor element, semiconductor device using the same, and method of manufacturing semiconductor device |
WO2017086324A1 (en) * | 2015-11-16 | 2017-05-26 | 株式会社豊田中央研究所 | Joining structure and method for manufacturing same |
-
1986
- 1986-09-01 JP JP20545786A patent/JPS6360537A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5306950A (en) * | 1991-12-26 | 1994-04-26 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Electrode assembly for a semiconductor device |
US5635764A (en) * | 1992-12-10 | 1997-06-03 | Nippondenso Co., Ltd. | Surface treated structure for solder joint |
JP2009016468A (en) * | 2007-07-03 | 2009-01-22 | Sony Corp | Solder joint structure and solder bump forming method |
JP2011187782A (en) * | 2010-03-10 | 2011-09-22 | Mitsubishi Electric Corp | Semiconductor element, semiconductor device using the same, and method of manufacturing semiconductor device |
WO2017086324A1 (en) * | 2015-11-16 | 2017-05-26 | 株式会社豊田中央研究所 | Joining structure and method for manufacturing same |
JPWO2017086324A1 (en) * | 2015-11-16 | 2018-05-31 | 株式会社豊田中央研究所 | Junction structure and manufacturing method thereof |
US11094661B2 (en) | 2015-11-16 | 2021-08-17 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Bonded structure and method of manufacturing the same |
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