JPS6349938A - Instruction prefetch control device - Google Patents

Abstract

PURPOSE:To attain rapid processing by setting up the number of instruction prefetch bytes in an instruction prefetch buffer and setting up data for the optimum number of instruction prefetch bytes to be applied to a setting means for the number of instruction prefetch bytes at timing obtained after the execution of a jump instruction. CONSTITUTION:Various instructions in a main storage device 7 are read out through a bus interface unit 4 or the like and executed by an instruction executing unit 2 and some of the instructions are stored in an instruction prefetch buffer 6 by an instruction prefetch control unit and then read out. The unit 5 is provided with the 1st and 2nd setting means 51, 52 for the number of prefetch bytes and data for the optimum number of instruction prefetch bytes determined based on the number of bits in a data bus or the frequency of a jump instruction executed by the unit 2 are applied from the unit 2 to the means 51 and set up in the means 51 and the data set up in the means 51 are set up in the means 51 at timing obtained after the execution of the jump instruction.

Description

[Detailed Description of the Invention] [Summary] The instruction execution unit is composed of a calculation control unit (CPIJ) including an instruction execution unit and an instruction prefetch buffer, and a main memory connected to this. This is an instruction prefetch control device that prefetches and reads several instructions stored in the main memory and executes the instructions sequentially. It is possible to automatically set the optimum value according to the frequency of jump commands.

[Industrial Field of Application] The present invention relates to an instruction preemption control device, and more specifically,
The present invention relates to a device for performing two-instruction prefetch control in a microprocessor device that includes an arithmetic control unit including an instruction execution unit and an instruction prefetch buffer, and a main memory connected thereto.

Instruction prefetch control is an effective method for speeding up processing, in which some of the instructions to be executed by the instruction execution unit are read out from the main memory in advance, and stored in an instruction prefetch buffer. The instruction execution unit executes the instruction stored in the instruction prefetch buffer every time one instruction is completed. Therefore, the instruction execution unit does not need to read the next instruction from the main memory every time it completes one instruction, allowing high-speed processing.

[Prior Art] FIG. 4 is a block diagram showing a configuration example of a conventional Il device that preempts instructions. In the figure, 1 is the cast control 2iI
For example, an 8086 (16-bit microprocessor) is used as the device (CPU). This calculation control jD device 1
, 2 is an instruction execution unit, 3 is an address conversion unit that inputs a logical address from the instruction execution unit 2 and converts it into an object 1!17 address, 4 is a bus interface unit, and 5 is an instruction prefetch control unit that performs instruction prefetch control. , 6 is an instruction prefetch buffer that temporarily stores prefetched instructions. 7 is a main 2ii device in which program steps are stored, 8 is an I/O1iII 11II adapter, and these are connected to the bus interface unit 4 in the CPU via a bus.

In the device configured in this manner, the instruction execution unit 2 transfers various instructions stored in the main memory 7 to the bus interface unit 4. Read and execute via the bus. The instruction prefetch ti control unit 5 has a main storage device 7.
Some of the instructions stored in the memory are stored in the instruction prefetch buffer 6 in advance, and each time the instruction execution unit 2 executes one instruction, control is performed so as to save the trouble of reading out the instructions to the main memory 7. It is something to do.

[Problems to be Solved by the Invention] In such a conventional instruction prefetch control device, the number of bytes of the instruction prefetch buffer 76 is fixed, for example, 6 bytes. The optimum value was selected in consideration of the number of bytes per instruction, <b), the V1 degree of the jump instruction that disables frI instruction prefetching, (C) the bus performance of the bus interface unit (bus width, bus cycle time), etc. be done.

However, the frequency of the jump instruction that disables instruction prefetching and the bus cycle time vary depending on the contents of the program stored in the main storage device 7, the configuration of external hardware, and the like. Furthermore, in a processor that takes into consideration the 32-bit processor and bus interface compatibility (16 bits), the bus width (number of bits) of the bus interface unit 4 is variable during initialization.

For this reason, if the number of bytes in the instruction prefetch buffer 6 is fixed, the instruction prefetch function may not work effectively depending on the program content or the configuration of external hardware, resulting in problems that impede high-speed processing.

The present invention has been made in view of these points, and includes a programmable setting means that can vary the number of bytes of the instruction destination IR rebuffer, and can be adjusted depending on the environment such as the frequency of jump instructions and the number of bits of the data bus. The purpose of the present invention is to provide an instruction prefetch control device that allows the number of bytes in the instruction prefetch buffer to be set to an optimal value automatically after execution of a jump instruction, and that enables high-speed processing of the processor at all times. Means for Solving the Problem] FIG. 1 is a block diagram of the principle of instruction prefetch control 2'0 according to the present invention (the same parts as in FIG. 4 are denoted by the same reference numerals). In the instruction prefetch control unit 5, 51
is a first prefetched byte number setting means, which is composed of a programmable register, for example, and the data set here is given from the instruction execution unit 2. 52
is a second prefetched byte number setting means, which is composed of, for example, a register, and is configured to set the data given from the first prefetched byte number setting means 51 at a timing after execution of a jump instruction.

[Operation] The first number of prefetched bytes 51 contains data on the optimal number of instruction prefetched bytes determined according to the number of bits of the data bus and the frequency of jump instructions executed by the instruction execution unit 2. is given and set from. Second
The prefetch byte number setting means 52 sets the data to be programmably set in the first prefetch byte number setting means 51 at the timing after execution of the jump instruction. The instruction prefetch control unit 5 includes a second prefetch byte number setting means 5
Instruction prefetch control is performed based on the number of bytes set to 2.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as in FIG. 1 are designated by the same reference numerals. In the bus interface unit 4 that connects the instruction execution unit 2 and the main storage device 7, 41 is a bus control section that performs bus control, to which a control line 4 and a response line 12 are connected. 42
43 is a transceiver/receiver that sends and receives data, and 43 is a driver that transfers the code in the data to an instruction prefetch buffer 6.
Output to. All of these are connected to the data line io.

44 is an operand output from the instruction execution unit 2.
This is a conflict determination unit that determines a conflict between the access request signal and the code fetch request signal output from the instruction prefetch control unit 5, and outputs an access request to the bus control unit 41 from here. 45 is a code address register that temporarily stores a code address, and the address signal from this register is switched by a multiplexer (MPX) and sent to the address line! A
is output to.

In the instruction prefetch control unit 5 which controls instruction prefetching depending on whether the instruction prefetch buffer 6 is empty or not, 51 is a first prefetch byte number setting means which sets the data given from the instruction execution unit 2 to programmer full. 52 is a second preemptive byte number setting means;
The data set in the prefetch byte number setting means 51 of
Set at the timing after executing a jump instruction. Reference numeral 53 designates a buffer 7 counter which uses a response outputted from the bus control unit 41 as a count-up signal and uses a response signal outputted from a comparing means 54, which will be described later, as a count-down signal. Further, it is cleared by the jump instruction execution signal output from the instruction execution unit 2.

The comparison means 54 compares the number of code fetch request bytes output from the instruction execution unit 2 and the buffer counter 53.
The result of the comparison is provided to the instruction execution unit 2 as a response signal and also to the buffer counter 53 as a countdown signal.

55 is a comparison means, and '
The set value is compared with the count number of the buffer counter 53, and the comparison result is provided to the conflict determination section 44 as a code fetch request signal.

The instruction prefetch buffer 6 temporarily stores the code from the driver 43 and outputs it to the instruction execution unit 2.

The operation of the apparatus configured as described above will be explained below with reference to the time chart shown in FIG.

First, as shown in (a), the instruction execution unit 2 sets the instruction prefetch byte number setting data Da, which is determined by taking into consideration the frequency of jump instructions in the program it executes, into the first prefetch byte. The strobe signal is output from here to the number setting means 51 (B).
Data [)a is set (latched) in the first prefetch byte number setting means 51 as shown in FIG. As a result, the first pre-fetch byte number setting means 51 successively outputs pre-fetch byte-loss data Db corresponding to data Da as shown in (c).

After such a state, when a jump instruction is executed by the instruction execution unit 2, a jump instruction execution signal is outputted from here as shown in (d), and the second prefetch byte number setting means 52 Using the instruction execution signal, the preemption byte number data Db output from the first preemption byte number setting means 51 is latched at the timing after the execution of the jump instruction (at the rising edge of the jab instruction execution signal), and this setting information 1sB is then output as shown in (e).

The operation after the optimal instruction prefetch byte number data is set in the second prefetch byte number setting means 52 will be explained by dividing it into instruction prefetch, code fetch by the instruction execution unit, and operand access.

[Instruction prefetching] The buffer counter 53 counts the number of bytes of instructions prefetched in the instruction prefetching buffer 6, and is cleared to "0" immediately after the jump instruction is executed. Second preemptive buy 1 to number setting means 5
2, the number of bytes SB to be taken first is compared with the count value BC of the buffer 7 counter 53, and the count value B is calculated.
When C is small (BC<SB), a code fetch request is output to the conflict determination section 44 of the bus interface unit 4. The conflict determination unit 44 determines a conflict between an operand access request from the instruction execution unit 2 and a code fetch request, and executes a code fetch if no operand access request has been output.

In the first code fetch after executing a jump instruction, the bus interface unit 4 latches the contents of the code register 31 provided in the address translation unit 3 into the code address register 45 in the bus interface unit 4, and at the same time transfers this address. to fetch the code. When the food fetch is completed, the value of the code address register 45 and the count value BC of the buffer counter 53 are respectively counted up.

On the other hand, in the case of a code fetch that is not the first after execution of a jump instruction, the bus interface unit 4 accesses the bus using the contents set in the code address register 45 as an address.

[Code fetch by instruction execution unit] The instruction execution unit 2 uses the comparison means 54 of the instruction prefetch control unit 5.
Outputs a signal indicating the number of code fetch request bytes,
Request code fetch. The comparison means 54 compares this requested byte number R8 with the count value BC of the buffer counter 53, and if the buffer count value BC is large (BC>
RB), notifies the instruction execution unit 2 of the response, and counts down the count value BC of the buffer counter 53. When the instruction execution unit 2 receives the response from the instruction prefetch control unit 5, it reads the code from the instruction prefetch buffer 76 and fetches the code. The instruction execution unit 2 also sends the jump instruction execution signal to the buffer counter 53 and the second prefetch byte number setting means 5.
2, the buffer counter 53 is cleared to O'', and the second prefetched byte number setting means 52 receives the first
The data from the prefetch byte number setting means 51 is loaded.

[Operand Access] For operand access by the instruction execution unit 2, an operand access request signal is notified to the conflict determination unit 44 of the bus interface unit 4, and the interval determination unit 44
determines a conflict with a code fetch request, and if it is determined that there is no instruction request to be fetched in advance, requests access to the bus control unit 41 and notifies the instruction execution unit 2 of response data.

[Effects of the Invention] As described in detail above, according to the present invention, the optimum instruction prefetch byte number data output from the instruction execution unit to the prefetch byte number setting means can be programmable at the timing after the jump instruction is executed. It is configured so that it is set. Therefore, according to the present invention, instruction prefetch control can be performed with an optimum number of prefetch bytes at all times in accordance with the program environment (jump instruction frequency, etc.) executed by an instruction execution unit, and the instruction prefetch system can perform high-speed processing. equipment can be provided.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of an instruction prefetch control device of the present invention, FIG. 2 is a configuration block diagram showing an embodiment of the present invention, and FIG. FIG. 4 is a time chart showing the latch timing of each second prefetch byte number setting means Q, and FIG. 4 is a block diagram showing an example of the configuration of a conventional instruction prefetch control device. 1 and 2, 1... Arithmetic control unit 2... Instruction execution unit 3... Address translation unit 4... Bus interface unit 5... Instruction prefetch control unit 6... Instruction Prefetch buffer 7...Main storage device 51...First prefetch byte/number 59 fixed hand "Q52...
...Second prefetch byte number setting means. Uninvented, 8 "King V Frotsukuro Palm Introduction 1"
=ko〉(D) Nuto O-1-Ichiri-- ↓ Latch↓ Latch t? Time f SEIT showing the benefits of one work Figure 3

Claims (1)

[Claims] Instruction execution unit (2) and instruction prefetch buffer (6)
a control device (1) including a main storage device (7) connected to this arithmetic and control device (1);
The instruction execution unit (2) preemptively reads some instructions stored in the main storage device (7) via the instruction prefetch buffer (6) and executes the instructions sequentially. In the instruction prefetch control device, a prefetch byte number setting means (52) is provided for setting the number of instruction prefetch bytes in the instruction prefetch buffer (6), and the prefetch byte number setting means (52) is provided with a prefetch byte number setting means (52). An instruction prefetch control device characterized in that data on the optimum number of instruction prefetch bytes to be prefetched is set at a timing after execution of a jump instruction.