JPS6346777A - Semiconductor element and manufacture thereof - Google Patents
Semiconductor element and manufacture thereofInfo
- Publication number
- JPS6346777A JPS6346777A JP19075586A JP19075586A JPS6346777A JP S6346777 A JPS6346777 A JP S6346777A JP 19075586 A JP19075586 A JP 19075586A JP 19075586 A JP19075586 A JP 19075586A JP S6346777 A JPS6346777 A JP S6346777A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- silicon thin
- silicon
- film
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 239000010409 thin film Substances 0.000 claims abstract description 68
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 58
- 239000010703 silicon Substances 0.000 claims abstract description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 55
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 7
- 239000011574 phosphorus Substances 0.000 claims abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052796 boron Inorganic materials 0.000 claims abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 230000000737 periodic effect Effects 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 24
- 230000007547 defect Effects 0.000 abstract description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052733 gallium Inorganic materials 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 2
- 229910021478 group 5 element Inorganic materials 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 239000005350 fused silica glass Substances 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 150000003376 silicon Chemical class 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、薄膜トランジスタ等の半導体素子およびその
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices such as thin film transistors and methods of manufacturing the same.
従来の技術
絶縁基板上へのシリコン薄膜形成（ｓｏ工；５ｉｌｉｃ
ｏｎ ｏｎ Ｉｎ５ｕｌａｔｏｒ ）は、シリコ７（Ｔ
Ｉ格子定数とほぼ等しいサファイア基板上にシリコ／を
エピタキシャル成長させたり（ＳＯＳ）、三次元ＩＣの
ようにシリコン酸化膜上に多結晶シリコンを形成した後
、レーザーアニールあるいは電子ビームアニール等で再
結晶化したシしている。これらの方法で、シリコン単結
晶と同等あるいはそれ以上の移動度をもつシリコン薄膜
も得られている。Conventional technology Silicon thin film formation on an insulating substrate (SO process; 5ilic
on on In5lator) is Silico 7 (T
Silicon is epitaxially grown on a sapphire substrate with approximately the same lattice constant as I (SOS), or polycrystalline silicon is formed on a silicon oxide film like a three-dimensional IC, and then recrystallized by laser annealing or electron beam annealing. I'm doing it. Using these methods, silicon thin films with a mobility equal to or higher than that of silicon single crystals have been obtained.
しかし、ＳＯ５ではサフアイヤとシリコンの界面で固定
電荷が発生するため、リーク電流がシリコン単結晶の場
合と比較して大きい。そのため、界面付近に不純物をイ
オン注入して固定電荷を減らし、リーク電流を減少させ
ている。However, in SO5, fixed charges are generated at the interface between sapphire and silicon, so the leakage current is larger than in the case of silicon single crystal. Therefore, impurity ions are implanted near the interface to reduce fixed charges and reduce leakage current.
最近、１次元イメージセンナや液晶デイスプレィのスイ
ッチング素子・駆動回路としてシリコン薄膜トランジス
タを、センサや液晶と同一基板上に形成するようになっ
てきた。このような場合基板としては光学的に透明でな
くてはならない。薄膜トランジスタとしてアモルファス
シリコンを用いる場合、移動度が０．１〜１ ｃｙＪ／
Ｖ−ｓｅｃと小さいため、高速動作ができない。このた
め機器の高速化ニハ、アモルファスシリコンよりも移動
度の大きい多結晶シリコンを用いなければならない。Recently, silicon thin film transistors have been formed on the same substrate as sensors and liquid crystals as switching elements and drive circuits for one-dimensional image sensors and liquid crystal displays. In such cases, the substrate must be optically transparent. When using amorphous silicon as a thin film transistor, the mobility is 0.1 to 1 cyJ/
Since it is as small as V-sec, high-speed operation is not possible. For this reason, in order to increase the speed of equipment, polycrystalline silicon, which has higher mobility than amorphous silicon, must be used.
多結晶シＩＪ コアは、Ｌ Ｐ ＣＶ Ｄ （Ｌｏｗ
ＰｒｅｓｓｕｒｅＣｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅ
ｐｏｓｉｔｉｏｎ）法で、基板温度が６００°Ｃ前後で
形成される。このため基板として溶融石英ガラスが主に
使われている。The polycrystalline IJ core is L P CV D (Low
Pressure Chemical Vapor De
The substrate temperature is around 600°C using the position method. For this reason, fused silica glass is mainly used as a substrate.
多結晶シリコン薄膜トランジスタは、例えば次のような
手順で作られる（第４図参照）。溶融石英ガラス１上に
ＬＰＣＶＤ法でシリコン薄膜２２を形成し、エツチング
あるいはＬＯＧＯＳによってこのシリコン薄膜を島状シ
てする。次にゲート絶縁膜４．ゲート電極５を形成した
後、セルフアライメントでシリコン薄膜２２にイオン注
入を行いソース・ドレイン領域を形成する。眉間絶縁膜
６形成後、９００°Ｃ前後でアニールを行う。コンタク
トホールを開け、アルミニウム等の金属配線７の形成を
行う。最後にプラズマＣｖＤ法でシリコン窒化膜８を形
成し４５０°Ｃ前後で約１時間アニールする。A polycrystalline silicon thin film transistor is manufactured, for example, by the following procedure (see FIG. 4). A silicon thin film 22 is formed on the fused silica glass 1 by the LPCVD method, and this silicon thin film is formed into an island shape by etching or LOGOS. Next, gate insulating film 4. After forming the gate electrode 5, ions are implanted into the silicon thin film 22 by self-alignment to form source/drain regions. After forming the glabellar insulating film 6, annealing is performed at around 900°C. A contact hole is opened and a metal wiring 7 made of aluminum or the like is formed. Finally, a silicon nitride film 8 is formed by plasma CVD and annealed at around 450° C. for about 1 hour.
発明が解決しようとする問題点
以上のような方法で形成した多結晶シリコン薄膜トラン
ジスタの電流電圧特性を第３図の■に示す。横軸はゲー
ト電圧、縦軸はドレイン電流でありゲート長１０μｍ
、ゲート幅が１００μｍの場合である。第 図に参考と
して、シリコン基板の表面を酸化した絶縁膜上に、同一
のプロセスで形成した多結晶シリコン薄膜の電気特性を
第３図の■に示す。図から明らかなように、溶融石英ガ
ラス上に形成した多結晶シリコン薄膜トランジスタのリ
ーク電流は、シリコン基板を酸化した絶縁膜上の場合と
比較して１〜２桁程大きく、数ｎＡ程度もある。Problems to be Solved by the Invention The current-voltage characteristics of a polycrystalline silicon thin film transistor formed by the method described above are shown in (■) in FIG. The horizontal axis is the gate voltage, the vertical axis is the drain current, and the gate length is 10 μm.
, when the gate width is 100 μm. 3. For reference, the electrical characteristics of a polycrystalline silicon thin film formed by the same process on an insulating film obtained by oxidizing the surface of a silicon substrate are shown in FIG. As is clear from the figure, the leakage current of a polycrystalline silicon thin film transistor formed on fused silica glass is about one to two orders of magnitude larger than that of a polycrystalline silicon thin film transistor formed on an insulating film formed by oxidizing a silicon substrate, and is on the order of several nA.
一次元イメージセンサのセンサとしてアモルファスシリ
コンを用いた場合、光電流は数ｎ人、暗電流が数ｐＡ程
度である。したがって、センサーの駆動回路として溶融
石英ガラス上の多結晶シリコン薄膜トランジスタは、リ
ーク電流が大きいため使用することができない。When amorphous silicon is used as a sensor of a one-dimensional image sensor, the photocurrent is several nanometers and the dark current is approximately several pA. Therefore, a polycrystalline silicon thin film transistor on fused silica glass cannot be used as a sensor drive circuit because of its large leakage current.
溶融石英ガラス上の多結晶シリコン薄膜トランジスタの
リーク電流が、シリコン基板の表面を酸化した絶縁膜上
に形成した場合と比較して大きい理由として、溶融石英
ガラスとシリコンでは格子定数が異なり熱膨張係数が約
１指貫なるため、多結晶シリコン膜中にシリコン基板上
と比べて大きなストレスが発生し、石英ガラスと多、結
晶シリコンの界面付近で欠陥密度が多数存在し、それが
リーク電流の増大をもたらしている。The reason why the leakage current of a polycrystalline silicon thin film transistor formed on fused silica glass is larger than that when the transistor is formed on an oxidized insulating film on the surface of a silicon substrate is that fused silica glass and silicon have different lattice constants and thermal expansion coefficients. Because it is about 1 finger, a larger stress occurs in the polycrystalline silicon film than on the silicon substrate, and a large number of defects exist near the interface between the quartz glass and the polycrystalline silicon, which causes an increase in leakage current. ing.
問題点を解決するための手段
本発明は、石英ガラスと多結晶シリコンの界面付近の欠
陥密度（固定電荷）を減少させるため、不純物によって
その欠陥を補償させる。ｎ−ＭＯＳを作製する場合は、
周期律表■族のたとえばホウ素、ガリウム、アルミニウ
ム等の不純物を、ｐ −ＭＯＳの場合には、周期律表Ｖ
族のたとえばヒ素。Means for Solving the Problems The present invention uses impurities to compensate for the defects in order to reduce the defect density (fixed charge) near the interface between quartz glass and polycrystalline silicon. When making n-MOS,
In the case of p-MOS, impurities such as boron, gallium, aluminum, etc. in group I of the periodic table are
For example, arsenic.
リン等の不純物を含むシリコン薄膜を溶融石英ガラス上
に１００〜３０００人形成する。この不純物を含むシリ
コン薄膜の上に、このシリコン薄膜の不純物濃度よりも
少ないシリコン薄膜をＬＰＣＶＤ法でたとえば１００〜
３０００人形成する。A silicon thin film containing impurities such as phosphorus is formed on fused silica glass by 100 to 3,000 people. On top of this impurity-containing silicon thin film, a silicon thin film with an impurity concentration lower than the impurity concentration of this silicon thin film is formed by LPCVD.
Form 3,000 people.
作用
このような構造にすることによって、溶融石英ガラスと
シリコン薄膜との界面付近の欠陥が補償され、この界面
によるリーク電流が減少する。また、不純物を含むシリ
コン薄膜上に、不純物を含まない第２シリコン薄膜を形
成し、この第２のシリコン薄膜中にＭＯＳ）う／ジスタ
を形成するため、非常にリーク電流の小さい薄膜トラン
ジスタを形成することができる。Effect: By adopting such a structure, defects near the interface between the fused silica glass and the silicon thin film are compensated for, and leakage current due to this interface is reduced. In addition, a second silicon thin film containing no impurities is formed on the silicon thin film containing impurities, and a MOS transistor is formed in this second silicon thin film, thereby forming a thin film transistor with extremely low leakage current. be able to.
実施例
第１図に本発明の第１の実施例による薄膜トランジスタ
の構造を示す。溶融石英ガラス基板１上にＬＰＣＶＤ法
でシリコン薄膜２を約１００〜２００Ｑ人形成する。こ
のシリコン薄膜２中に、イオン注入法で、界面付近の欠
陥を補償するため、ｎ−ＭＯＳには周期律表■族元素例
えばホウ素あるいはガリウムあるいはアルミニウムを、
ｐ−ＭＯＳの場合には周期律表Ｖ族の元素例えばヒ素あ
るいはリンを、１０１１〜１０１５コ／ｃＩ注入する。Embodiment FIG. 1 shows the structure of a thin film transistor according to a first embodiment of the present invention. A silicon thin film 2 of about 100 to 200 layers is formed on a fused silica glass substrate 1 by the LPCVD method. In order to compensate for defects near the interface, an element of Group I of the periodic table, such as boron, gallium, or aluminum, is added to the n-MOS by ion implantation into the silicon thin film 2.
In the case of p-MOS, an element of Group V of the periodic table, such as arsenic or phosphorus, is implanted at 1011 to 1015 atoms/cI.
このシリコン薄膜２の上に、同じ（’ＬＰＣＶＤ 法で
シリコン薄膜３を１００〜３ｏ０〇人形成する。On this silicon thin film 2, a silicon thin film 3 of 100 to 3000 times is formed using the same LPCVD method.
これら２層のシリコン薄膜２，３をエツチングあるいは
ＬＯＧＯ３によって島状にする。These two silicon thin films 2 and 3 are made into island shapes by etching or LOGO3.
次にゲート酸化膜４を５００〜１０００人、ゲートポリ
シリコンロを形成する。ゲートポリシリコンｓをマスク
トシてシリコン薄膜３にセルフアライメントでイオン注
入を行いソース・ドレイ／領域３ｇ、３ｄを形成する。Next, a gate oxide film 4 is formed by 500 to 1000 people to form a gate polysilicon film. Using a gate polysilicon s as a mask, ions are implanted into the silicon thin film 3 in self-alignment to form source/drain/regions 3g and 3d.
次に層間絶縁膜ｅ形成後、活性化のための熱処理を９０
０°Ｃ前後で約３０分間行う。この熱処理中によシリコ
ン窒膜２中に存在する不純物がシリコン薄膜３中に拡散
する。この拡散によって溶融石英ガラス１とシリコン薄
膜２の界面だけでなく、シリコン薄膜２とシリコン薄膜
３との界面での欠陥も補償する。シリコン薄膜２中のイ
オン注入量は、すべての熱処理が終了した後、シリコン
薄膜が導通状態にならない程度である。Next, after forming the interlayer insulating film e, heat treatment for activation was performed for 90 minutes.
Do this for about 30 minutes at around 0°C. During this heat treatment, impurities present in the silicon nitride film 2 diffuse into the silicon thin film 3. This diffusion compensates for defects not only at the interface between fused silica glass 1 and silicon thin film 2, but also at the interface between silicon thin film 2 and silicon thin film 3. The amount of ions implanted into the silicon thin film 2 is such that the silicon thin film does not become conductive after all the heat treatments are completed.
層間絶縁膜６にコンタクトホールを［、アルミニウム７
配線を行う。最後にプラズマＣＶＤ法でシリコン窒化膜
８を形成し４５０°Ｃで６０分間熱処理して水素化を行
う。A contact hole is formed in the interlayer insulating film 6 [, aluminum 7
Perform wiring. Finally, a silicon nitride film 8 is formed by the plasma CVD method, and hydrogenated by heat treatment at 450° C. for 60 minutes.
第３図の■は本発明の方法により作成された薄膜トラン
ジスタのＶＧ −ｒＤ特性を示し、従来の■よりもすぐ
れた特性が得られている。3 in FIG. 3 shows the VG-rD characteristics of the thin film transistor produced by the method of the present invention, which shows better characteristics than the conventional pattern 2.
第２図に本発明の第２の実施例を示す。溶融石英ガラス
１上にグロー放電法で、ｎ−ＭＯＳの場合には、周期律
表■族元素例えばホウ素を含む気体状化合物ガス（Ｂ２
Ｈ６）とシラン（ＳｉＨａ）で、ホウ素を１０ｐｐｍ
から５％含むｐ型アモルファスシリコン薄膜１２を、ｐ
−ＭＯＳの場合には、周期律表Ｖ族元素例えばリンを含
む気体状化合物ガス（ＰＨ５）とシランガｘ（ＳｉＨ４
）でリンを１０ｐｐｍから６％含むｎｉアモルファスシ
リコン薄膜１２を形成する。このアモルファスシリコン
薄膜上に ・ＬＰＣＶＤ法でシリコン薄膜３を形成する
。その後の工程は第１の実施例と同じ方法で行い、シリ
コン薄膜トランジスタを作製する。FIG. 2 shows a second embodiment of the invention. In the case of n-MOS, a gaseous compound gas (B2
H6) and silane (SiHa) with 10 ppm of boron.
A p-type amorphous silicon thin film 12 containing 5% from p
- In the case of MOS, a gaseous compound gas (PH5) containing a group V element of the periodic table, such as phosphorus, and silanga x (SiH4
) to form a ni amorphous silicon thin film 12 containing 10 ppm to 6% phosphorus. A silicon thin film 3 is formed on this amorphous silicon thin film by the LPCVD method. The subsequent steps are performed in the same manner as in the first embodiment to fabricate a silicon thin film transistor.
第３の実施例として、非結晶性絶縁基板としてホウケイ
酸ガラスを用いる。このガラスは温度が５５０°Ｃ以下
で用いなければならないので、シリコン薄膜の形成その
他プロセス温度を５６０°Ｃ以下でシリコン薄膜トラン
ジスタを作製する。In a third embodiment, borosilicate glass is used as the amorphous insulating substrate. Since this glass must be used at a temperature of 550° C. or lower, a silicon thin film transistor is manufactured at a silicon thin film formation and other process temperatures of 560° C. or lower.
発明の効果
本発明によって溶融石英ガラス上にリーク電流の非常に
少ない多結晶シリコ／薄膜トランジスタを容易に安価に
形成することができるため、−次元イメージセンサや液
晶デイスプレィのスイッチング素子・駆動回路に用いる
ことができる。したがって高速で薄くて小型の一次元イ
メージセ／すや液晶デイスプレィを作製することができ
る。またリーク電流が小さくなるため、ＯＮ１０ Ｆ
Ｆ 比が大きくなるので、センサやデイスプレィのカラ
ー化・高階調も容易に行なえるようになる。Effects of the Invention The present invention allows polycrystalline silicon/thin film transistors with very low leakage current to be easily and inexpensively formed on fused silica glass, and therefore can be used in switching elements and drive circuits of -dimensional image sensors and liquid crystal displays. Can be done. Therefore, a thin and small one-dimensional image sensor/liquid crystal display can be manufactured at high speed. Also, since the leakage current becomes smaller, ON10 F
Since the F ratio becomes large, colorization and high gradation of sensors and displays can be easily performed.
第１図は本発明の第１の実施例による薄膜トランジスタ
の断面図、第２図は本発明の第２の実施例の同トランジ
スタの断面図、第３図は本発明による石英ガラス上のシ
リコン薄膜トランジスタ。
シリコン基板の表面を酸化した上に作製したシリコン薄
膜トランジスタ、および従来技術による石英ガラス上の
シリコン薄膜トランジスタの電気特性を示す図、第４図
に従来例のトランジスタを示す断面図である。
１ ・・・・非結晶性絶縁基板（溶融石英ガラス）、２
・・・・・・不純物を１０１１〜１０１３コ／ｄイオ／
注入したシリコン薄膜、３・・・・・・ＬＰＣＶＤで作
製したシリコン薄膜、４・・・・ゲート酸化膜、６・・
・・・ゲートポリシリコン、６ ・・層間絶縁膜、了・
・・・・アルミニウム配線、８・・・・・・プラズマシ
リコンチッ化膜、１２・・・グロー放電法で作製した不
純物を含むアモルファスシリコン薄膜。
第３図
３−・・μ体りＫＪＨ１％プラスよ−ＪｇｔＬランシ又
タゲートｃ７Ｅ（ｖ）
１−・−溶量π、ｂ芙や゛う入
第
Ｇ’−一一層聞耗絃７煤
７−−−ア１しζこラムｂ、Ｊ’）ｓＬ計−−ブラフ、
７’ｒｔづ゛６月４
２２−ｔｐｃｖｖシリソ薄長FIG. 1 is a cross-sectional view of a thin film transistor according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of the same transistor according to a second embodiment of the present invention, and FIG. 3 is a silicon thin film transistor on quartz glass according to the present invention. . FIG. 4 is a diagram showing electrical characteristics of a silicon thin film transistor fabricated on an oxidized surface of a silicon substrate and a silicon thin film transistor on quartz glass according to a conventional technique, and FIG. 4 is a cross-sectional view showing a conventional transistor. 1...Amorphous insulating substrate (fused silica glass), 2
・・・・・・1011 to 1013 impurities/d io/
Injected silicon thin film, 3... Silicon thin film produced by LPCVD, 4... Gate oxide film, 6...
...Gate polysilicon, 6 ...Interlayer insulating film, finished...
. . . Aluminum wiring, 8 . . . Plasma silicon nitride film, 12 . . . Amorphous silicon thin film containing impurities prepared by glow discharge method. Fig. 3 3--μ body KJH 1% plus JgtL runci or tagate c7E (v) 1---molten amount π, b and ゛input No. G'-11 wear-out string 7 soot 7 --- A1 and ζ column b, J') sL total -- Bluff,
7'rtzu゛June 4 22-tpcvv siliso thin length
Claims (4)
素の少なくとも１種類の不純物を含む第１のシリコン薄
膜を形成し、前記第１のシリコン薄膜より不純物濃度の
低い第２のシリコン薄膜を形成してなることを特徴とす
る半導体素子。(1) A first silicon thin film containing at least one type of impurity of an element of Group III or V of the periodic table is formed on an insulating substrate, and a second silicon thin film having an impurity concentration lower than that of the first silicon thin film is formed on an insulating substrate. A semiconductor device characterized by forming a thin film.
形成した後、減圧気相成長法で第２のシリコン薄膜を形
成することを特徴とする半導体素子の製造方法。(2) A method for manufacturing a semiconductor device, which comprises forming a first silicon thin film containing impurities on an insulating substrate, and then forming a second silicon thin film by low pressure vapor deposition.
素、リン、ホウ素の少なくとも１種類の不純物を注入す
ることを特徴とする特許請求の範囲第２項記載の半導体
素子の製造方法。(3) The method for manufacturing a semiconductor device according to claim 2, characterized in that at least one type of impurity of arsenic, phosphorus, and boron is implanted into the first silicon thin film using an ion implantation method.
コンを含む気体状化合物ガスと、リンあるいはホウ素を
含む気体状化合物ガスを用いて形成したアモルファスシ
リコンを用いることを特徴とする特許請求の範囲第２項
記載の半導体素子の製造方法。(4) The first silicon thin film is characterized in that amorphous silicon formed by a glow discharge method using a gaseous compound gas containing silicon and a gaseous compound gas containing phosphorus or boron is used. 2. The method for manufacturing a semiconductor device according to item 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19075586A JPS6346777A (en) | 1986-08-14 | 1986-08-14 | Semiconductor element and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19075586A JPS6346777A (en) | 1986-08-14 | 1986-08-14 | Semiconductor element and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6346777A true JPS6346777A (en) | 1988-02-27 |
Family
ID=16263192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19075586A Pending JPS6346777A (en) | 1986-08-14 | 1986-08-14 | Semiconductor element and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6346777A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993002468A1 (en) * | 1991-07-16 | 1993-02-04 | Seiko Epson Corporation | Chemical vapor deposition apparatus, method of semiconductor film formation, and method of producing thin film semiconductor device |
| US5238857A (en) * | 1989-05-20 | 1993-08-24 | Fujitsu Limited | Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure |
| US5318919A (en) * | 1990-07-31 | 1994-06-07 | Sanyo Electric Co., Ltd. | Manufacturing method of thin film transistor |
-
1986
- 1986-08-14 JP JP19075586A patent/JPS6346777A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5238857A (en) * | 1989-05-20 | 1993-08-24 | Fujitsu Limited | Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure |
| US5318919A (en) * | 1990-07-31 | 1994-06-07 | Sanyo Electric Co., Ltd. | Manufacturing method of thin film transistor |
| WO1993002468A1 (en) * | 1991-07-16 | 1993-02-04 | Seiko Epson Corporation | Chemical vapor deposition apparatus, method of semiconductor film formation, and method of producing thin film semiconductor device |
| US5510146A (en) * | 1991-07-16 | 1996-04-23 | Seiko Epson Corporation | CVD apparatus, method of forming semiconductor film, and method of fabricating thin-film semiconductor device |
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