JPS6337268A - Tester of semiconductor device - Google Patents
Tester of semiconductor deviceInfo
- Publication number
- JPS6337268A JPS6337268A JP61180491A JP18049186A JPS6337268A JP S6337268 A JPS6337268 A JP S6337268A JP 61180491 A JP61180491 A JP 61180491A JP 18049186 A JP18049186 A JP 18049186A JP S6337268 A JPS6337268 A JP S6337268A
- Authority
- JP
- Japan
- Prior art keywords
- pull
- resistor
- state
- level
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 230000003068 static effect Effects 0.000 claims abstract description 19
- 238000012360 testing method Methods 0.000 claims abstract description 15
- 230000002950 deficient Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は半導体装置の試験装置において、ある論理状態
でのスタティック電源電流を測定し得ない等の従来装置
の問題点を解決するため、プルアップ抵抗及びプルダウ
ン抵抗をＭ ＯＳ ＦＥＴで構成することにより、
試験時、該ＦＥＴをオフ状態にしてプルアップ抵抗及び
プルダウン抵抗の影響なくスタティック電源電流を測定
し得るようにしたものである。[Detailed Description of the Invention] [Summary] The present invention uses a pull-up resistor and a pull-down resistor in a test equipment for semiconductor devices in order to solve the problems of conventional devices such as the inability to measure static power supply current in a certain logic state. By configuring the resistor with a MOS FET, the FET can be turned off during testing so that the static power supply current can be measured without the influence of the pull-up resistor and pull-down resistor.
第３図はプルアップ抵抗及びプルダウン抵抗を内蔵され
た従来の半導体装置の一例の回路図を示す。同図中、Ａ
、Ｂは入力端子、Ｒｕはプルアップ抵抗、ＲＤはプルダ
ウン抵抗、１はＣ−ＭＯＳＦＥＴにて構成されている例
えばインバータ１ａ及びプントゲート１ｂよりなる論理
回路、Ｘは出力端子である。FIG. 3 shows a circuit diagram of an example of a conventional semiconductor device incorporating a pull-up resistor and a pull-down resistor. In the same figure, A
, B is an input terminal, Ru is a pull-up resistor, RD is a pull-down resistor, 1 is a logic circuit composed of C-MOSFETs, for example, an inverter 1a and a Punto gate 1b, and X is an output terminal.
ここで、Ｃ−ＭＯＳＦＥＴにて構成される半導体装ｄは
、一般に、良品においては入力端子Ａ。Here, the semiconductor device d composed of a C-MOSFET is generally the input terminal A in a non-defective product.
Ｂが１−ルベルのいかなる状態であってもスタティック
電源電流は流れない。そこで、Ｃ−ＭＯＳＦＥＴにて構
成される半導体装置では、出荷試験としてスタティック
電源電流を測定することが行なわれている。No static power supply current flows in any state where B is 1-Level. Therefore, in a semiconductor device configured with a C-MOSFET, static power supply current is measured as a shipping test.
スタティック電源電流を測定する場合、第３図においで
、端子Δ、Ｂを開ｔＪり状態にして電源及びアース間に
電源電Ｂ−を印加して測定するｈ法、又は、端子Ａを電
源と同電位に１」る−７５端ｆＢをアース電位として測
定するｈ法がある。When measuring static power supply current, in Figure 3, use the h method, in which terminals Δ and B are left open, and power supply voltage B- is applied between the power supply and ground, or terminal A is connected to the power supply. There is an h method in which the -75 end fB, which is at the same potential, is measured with the ground potential.
（発明が解決しようとする問題貞〕
上記のように従来装置は、プルアップ抵抗１’＜ ｕ及
びプルダウン抵抗ｒ＜ｒ＋が接続されている状態でスタ
ティック電源電流を測定しているので、例えば、インバ
ータ１ａの出ツノ端子とアースどの間、又は、ナンドグ
ー１・１ｂの出力端子と電源との間に夫々抵抗成分子、
、ｒ２が存７Ｉする如き不良品を、入力端子Ａが１ルベ
ル、入力端子１３が１．−レベル以外の論理状態におい
て試験した場合、この抵抗成分子、、ｒ２のためにスタ
ティック電源電流が流れているのかくリーク電流）、プ
ルアップ抵抗Ｒｕ及びプルダウン抵抗Ｒｏのためにスタ
ティック電源電流が流れているのか分らず、特に、リー
ク電流がプルアップ抵抗及びプルダウン抵抗を流れる電
流に比して小さいと不良品であるにも拘らず良品と判断
してしまう等の問題点があった。(Problem to be Solved by the Invention) As described above, the conventional device measures the static power supply current in a state where the pull-up resistor 1'<u and the pull-down resistor r<r+ are connected. Resistance elements between the output terminal of the inverter 1a and the ground, or between the output terminals of the Nandogoos 1 and 1b and the power supply, respectively.
, r2 exists 7I, input terminal A is 1 level, input terminal 13 is 1 level. - When tested in a logic state other than level, a static power supply current flows due to this resistor element, r2 (leakage current), a static power supply current flows due to the pull-up resistor Ru and the pull-down resistor Ro. In particular, if the leakage current is smaller than the current flowing through the pull-up resistor and the pull-down resistor, the product may be judged to be good even though it is defective.
因に、入力端子Ａが１ルベル、入力端子Ｂが１−レベル
の論理状態の時は、プルアップ抵抗Ｒｕ及びプルダウン
抵抗Ｒｏの有無に関係なく、不良品では上記抵抗成分子
ｌ 、ｒ２のためにスタティック電源電流が流れるので
不良品と確実に判断でき、この論理状態の場合は特に問
題ない。Incidentally, when the input terminal A is in the logic state of 1 level and the input terminal B is in the 1-level logic state, regardless of the presence or absence of the pull-up resistor Ru and pull-down resistor Ro, in a defective product, due to the above resistance components l and r2. Since a static power supply current flows through the device, it can be determined with certainty that it is a defective product, and there is no particular problem in this logic state.
このように、従来装置では、ある論理状態の時は良品、
不良品の判断ができない問題点があった。In this way, with conventional equipment, when a certain logic state is present, a good product or
There was a problem in that it was not possible to determine which products were defective.
（問題点を解決するための手段）
本発明になる半導体装置の試験装置は、第１図に示す如
く、プルアップ抵抗及びプルダウン抵抗を大々ＦＥＴ２
Ｐ、２ＮＴ：構成し、スタティック電源電流試験時にＦ
ＥＴ２Ｐ、２Ｎをオフ状態に切換える構成としてなる。(Means for Solving the Problems) As shown in FIG.
P, 2NT: Configured and F during static power supply current test
The configuration is such that ET2P and ET2N are switched to the off state.
本発明装置は、スタティック電源電流試験時、ＦＥＴ２
ｐ 、２Ｎをオフにして青価的にブルアツブ抵抗及びプ
ルダウン１ｍ ｔｉｉが無いのと同じ状態にし得るので
、特に、入力端子△が１−ルベル、入力端子ＢがＬレベ
ル以外の論理状態をはじめとしたいかなる論理状態の時
でもスタティック電源電流を正確に測定し得る。The device of the present invention is capable of detecting FET2 during a static power supply current test.
P, 2N can be turned off and the state can be the same as if there were no pull-up resistor and pull-down 1mtii, so in particular, input terminal △ is 1-level, input terminal B is in a logic state other than L level, etc. Static power supply current can be accurately measured in any logic state.
第１図は本発明装置の一実施例の回路図を示し、同図中
、第３図と同一構成部分には同一番号、同一符号を付す
。同図中、２ＰはＰヂャンネルＭＯ８ＦＥＴにて構成さ
れたプルアップへ゛価低抗であり、電源と端子へとの間
に接続されている。、２ＮはＮチャンネルＭＯ８ＦＥＴ
に−Ｃ構成されたプルダウン等価抵抗であり、端子１３
どアースとの間に接続されている。３は試ｗＡ′Ｕニー
ド切換信号入力端子で、ＮヂャンネルＭＯ８ＦＥＴ２Ｎ
のゲートに接続されていると共に、インバータ４を介し
゛（１〕チャンネルＭＯ８ＦＥＴのゲートに１８続され
ている。FIG. 1 shows a circuit diagram of an embodiment of the apparatus of the present invention, in which the same components as those in FIG. 3 are given the same numbers and symbols. In the figure, 2P is a pull-up low voltage resistor composed of a P channel MO8FET, and is connected between the power supply and the terminal. , 2N is N-channel MO8FET
-C is configured as a pull-down equivalent resistance, and terminal 13
which is connected between the ground and ground. 3 is the test wA'U needle switching signal input terminal, N channel MO8FET2N
It is also connected to the gate of a (1) channel MO8FET via an inverter 4.
いま、スタティック電源電流試験ニードに１−るに際し
、端子３にトルベル信号を供給する。これにより、Ｐヂ
ャンネルＭＯ８ＦＥＴ２ｐはそのＨレベルゲート入力に
よってカットオフ状態どされる一方、ＮチャンネルＭＯ
３ＦＥＴ２ＮはそのＬレベルゲート入力によってカット
オフ状態とされ、どちらら無限大の抵抗が接続されたの
と同じ状態となり、等価的に第２図に示す如く、プルア
ップ抵抗及びプルダウン抵抗が無いのと同じ回路になる
。Now, when turning on the static power supply current test need, a torque signal is supplied to terminal 3. As a result, the P-channel MO8FET2p is returned to the cutoff state by its H-level gate input, while the N-channel MO8FET2p
3FET2N is cut off by its L level gate input, which is the same state as if an infinite resistor were connected, and equivalently, as shown in Figure 2, there is no pull-up resistor and no pull-down resistor. It will be the same circuit.
従って、第３図に示す従来装置のようにプルアップ抵抗
及びプルダウン抵抗に電流が流れることはないので、入
力端子ＡがＨレベル、入力端子ＢがＬレベル以外の論理
状態の時、不良品の場合は、抵抗成分子ｌ 、ｒ２の存
在によってのみスタティック電源電流が流れることにな
り、不良品を正確にＹ１１断じ得る。Therefore, unlike the conventional device shown in Fig. 3, current does not flow through the pull-up resistor and pull-down resistor, so when input terminal A is in a logic state other than H level and input terminal B is in a logic state other than L level, defective products may be detected. In this case, the static power supply current will flow only due to the presence of the resistance elements l and r2, and it is possible to accurately identify the defective product as Y11.
次に、第１図には図示しないノリツブフロップ等地の回
路を試験するモードにするに際し、端子３にトルベル信
号を供給する。これにより、ＰチャンネルＭＯ３ＦＥＴ
２ｐ及びＮチャンネルＭＯ５ＦＥＴは共にオン状態とさ
れ、夫々、等価的にプルアップ抵抗、プルダウン抵抗が
接続されたのと同じ状態となる。この状態で、ノリツブ
フロップ等の試験を行なう。Next, when setting the mode for testing a circuit such as a Noritz flop (not shown in FIG. 1), a torque signal is supplied to the terminal 3. This allows P-channel MO3FET
Both the 2p and N-channel MO5FETs are turned on, and are equivalently in the same state as if a pull-up resistor and a pull-down resistor were connected, respectively. In this state, tests such as Noritsubu flop are performed.
なお、上記実施例は、論理回路の１の入力端にプルアッ
プ等価抵抗及びプルダウン等価抵抗を接続したものであ
るが、これに限定されるものではなく、出力側に接続し
ても同様である。In addition, in the above embodiment, a pull-up equivalent resistor and a pull-down equivalent resistor are connected to the input terminal of the logic circuit 1, but the present invention is not limited to this, and the same can be done even if they are connected to the output side. .
又、上記実施例は論理回路−系統についてのみの説明で
あるが、複数系統並列に接続された論理回路にも同様に
適用し得る。Furthermore, although the above embodiments are only about logic circuit systems, they can be similarly applied to logic circuits in which multiple systems are connected in parallel.
本発明によれば、スタデイツク電源電流試験ｆｆ、’＋
、ＦＥＴをオフにして新価的にプルアップ抵抗及びプル
ダウン抵抗が無いのと同じ状（ぶにし４ｒ７るので、特
に、プルアップ側の入力端子がト］レベル、プルダウン
側の入力端子が１−レベル以外の論理状態をはじめとし
たいかなる論理状態の時でもスタデイツク電源電流を正
確に測定し１ｑ１これにより、論理回路に不良がある場
合、リーク電流が小さくてもこの不良を確実に判断し得
る等の特長を有する。According to the invention, the study power supply current test ff,'+
, when the FET is turned off, the state is the same as when there is no pull-up resistor and no pull-down resistor (because the input terminal on the pull-up side is set to 1-level), and the input terminal on the pull-down side is set to 1- level. Accurately measure the study power supply current in any logic state, including logic states other than level1q1.Thus, if there is a defect in the logic circuit, this defect can be reliably determined even if the leakage current is small. It has the following features.
第１図は本発明装置の一実施例の回路図、第２図は本発
明装置のスタティック電源電流試験時の等価回路図、
第３図は従来装買の一例の回路図である、。
第１図、第２図において、
１は論理回路、
１ａ、４はインバータ、
１ｂはナントゲート、
２ＰはＰヂャンネルＭＯ８ＦＥＴ。
２ＮはＮヂャンネルＭＯ８ＦＥＴ。
３は試験モード切換信号入力端子、
Ａ、Ｂは入力端子、
ｒｌ 、ｒ２は不良品における抵抗成分、Ｘは出力端子
である。FIG. 1 is a circuit diagram of an embodiment of the device of the present invention, FIG. 2 is an equivalent circuit diagram of the device of the present invention during a static power supply current test, and FIG. 3 is a circuit diagram of an example of a conventional device. In FIGS. 1 and 2, 1 is a logic circuit, 1a and 4 are inverters, 1b is a Nant gate, and 2P is a P channel MO8FET. 2N is N channel MO8FET. 3 is a test mode switching signal input terminal, A and B are input terminals, rl and r2 are resistance components in a defective product, and X is an output terminal.
Claims (1)
アップ抵抗及びプルダウン抵抗を接続された半導体装置
のスタティック電源電流を試験する装置において、 上記プルアップ抵抗及びプルダウン抵抗を夫々ＦＥＴ（
２＿Ｐ、２＿Ｎ）で構成し、上記スタティック電源電流
試験時に該ＦＥＴ（２＿Ｐ、２＿Ｎ）をオフ状態に切換
える構成としてなることを特徴とする半導体装置の試験
装置。[Claims] In an apparatus for testing the static power supply current of a semiconductor device in which a pull-up resistor and a pull-down resistor are connected to a logic circuit (1) composed of a C-MOSFET, the pull-up resistor and pull-down resistor are Each FET (
2_P, 2_N), and is configured to switch the FETs (2_P, 2_N) to an off state during the static power supply current test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61180491A JPS6337268A (en) | 1986-07-31 | 1986-07-31 | Tester of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61180491A JPS6337268A (en) | 1986-07-31 | 1986-07-31 | Tester of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6337268A true JPS6337268A (en) | 1988-02-17 |
Family
ID=16084164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61180491A Pending JPS6337268A (en) | 1986-07-31 | 1986-07-31 | Tester of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6337268A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04120484A (en) * | 1990-09-10 | 1992-04-21 | Sharp Corp | Integrated circuit device |
| US5475330A (en) * | 1991-09-04 | 1995-12-12 | Sharp Kabushiki Kaisha | Integrated circuit with voltage setting circuit |
| KR100450659B1 (en) * | 1997-08-28 | 2004-11-26 | 삼성전자주식회사 | Gate driving circuit for thin film transistor liquid crystal display and driving integrated circuit provided with the same, especially reducing test time for testing current driving capability |
-
1986
- 1986-07-31 JP JP61180491A patent/JPS6337268A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04120484A (en) * | 1990-09-10 | 1992-04-21 | Sharp Corp | Integrated circuit device |
| US5475330A (en) * | 1991-09-04 | 1995-12-12 | Sharp Kabushiki Kaisha | Integrated circuit with voltage setting circuit |
| KR100450659B1 (en) * | 1997-08-28 | 2004-11-26 | 삼성전자주식회사 | Gate driving circuit for thin film transistor liquid crystal display and driving integrated circuit provided with the same, especially reducing test time for testing current driving capability |
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