JPS63285941A - Electronic circuit substrate, manufacture of said substrate and electronic circuit device - Google Patents
Electronic circuit substrate, manufacture of said substrate and electronic circuit deviceInfo
- Publication number
- JPS63285941A JPS63285941A JP62121593A JP12159387A JPS63285941A JP S63285941 A JPS63285941 A JP S63285941A JP 62121593 A JP62121593 A JP 62121593A JP 12159387 A JP12159387 A JP 12159387A JP S63285941 A JPS63285941 A JP S63285941A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- layer
- electronic circuit
- conductive substrate
- electrical insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 56
- 150000002500 ions Chemical class 0.000 claims abstract description 24
- -1 nitrogen ions Chemical class 0.000 claims abstract description 21
- 238000004544 sputter deposition Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- 229910052786 argon Inorganic materials 0.000 claims abstract description 5
- 239000001307 helium Substances 0.000 claims abstract description 4
- 229910052734 helium Inorganic materials 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 22
- 238000007740 vapor deposition Methods 0.000 claims description 13
- 230000007423 decrease Effects 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 11
- 238000005219 brazing Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 claims 1
- 229910052754 neon Inorganic materials 0.000 claims 1
- 229910052724 xenon Inorganic materials 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000002513 implantation Methods 0.000 abstract description 6
- 239000007789 gas Substances 0.000 abstract description 5
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011261 inert gas Substances 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 3
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 166
- 239000000919 ceramic Substances 0.000 description 15
- 239000002245 particle Substances 0.000 description 15
- 239000010949 copper Substances 0.000 description 11
- 239000010408 film Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 238000010292 electrical insulation Methods 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000011148 porous material Substances 0.000 description 5
- 238000007751 thermal spraying Methods 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 229910020220 Pb—Sn Inorganic materials 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000975 Carbon steel Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910002065 alloy metal Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000010962 carbon steel Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000007750 plasma spraying Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高熱伝導性基板上に電気絶縁層が形成され、
電気絶縁層上に金属層が形成された電子回路基板、その
製造方法及び電子回路装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an electrically insulating layer formed on a highly thermally conductive substrate,
The present invention relates to an electronic circuit board in which a metal layer is formed on an electrically insulating layer, a manufacturing method thereof, and an electronic circuit device.
従来、絶縁型素子等の電子回路基板としては、焼成した
アルミナ板等のセラミックス板からなる電気絶縁層が高
台伝導性基板に接合されて使用されている。この電気絶
縁層は高熱伝導性基板との電気絶縁性及び素子あるいは
回路から発生する熱を高熱伝導性基板へ伝達する役割を
果たしている。BACKGROUND ART Conventionally, an electrically insulating layer made of a ceramic plate such as a fired alumina plate is bonded to an elevated conductive substrate and used as an electronic circuit board for an insulated element or the like. This electrically insulating layer serves to provide electrical insulation with the highly thermally conductive substrate and to transmit heat generated from elements or circuits to the highly thermally conductive substrate.
電子回路部品において回路素子性能を十分に発揮させる
には、電気絶縁層の熱抵抗をできる限り少なくして放熱
特性を高くすることが望ましい。この点から電気絶縁層
であるセラミックス板の厚さは必要とする耐電気絶縁性
の得られる範囲内で薄くする必要がある。しかし、焼成
したセラミックス板は、板厚が薄くなると機械的強度が
低下し、回路製造の際の僅かな外力により亀裂を生じて
信頼性の点で問題になるので、厚さを薄くするには限界
があり、一般には0.25〜1.0Iのものが多用され
ている。一方、焼成したセラミックス板を用いる場合に
は、高熱伝導性基板との接合は通常半田付けによって行
なわれるため、接合面に熱抵抗を大きくする・気孔等の
欠陥を少なくする表面仕上げが必要となる。更に、セラ
ミックスは半田との漏れ性が悪く、半田で高熱伝導性基
板と直接接合することが困難なため1通常はセラミック
ス板にメタライジング処理を施すなど製造工程が複雑に
なっている。また、セラミックス板と高熱伝導性基板と
は半田で接合するために接合強度が低く、セラミックス
板と高熱伝導性基板の熱膨張差によるセラミックス板の
剥離や割れの心配もある。In order to fully exhibit circuit element performance in electronic circuit components, it is desirable to reduce the thermal resistance of the electrical insulating layer as much as possible to improve heat dissipation characteristics. From this point of view, the thickness of the ceramic plate serving as the electrically insulating layer must be made as thin as possible within a range that provides the required electrical insulation resistance. However, as the thickness of fired ceramic plates decreases, their mechanical strength decreases, and even slight external forces during circuit manufacturing can cause cracks, which poses problems in terms of reliability. There is a limit, and in general, those of 0.25 to 1.0I are often used. On the other hand, when using fired ceramic plates, the bonding with a highly thermally conductive substrate is usually done by soldering, so the bonding surface must have a surface finish that increases thermal resistance and reduces defects such as pores. . Furthermore, ceramics have poor leakage with solder, and it is difficult to directly bond them to a highly thermally conductive substrate with solder.1 The manufacturing process is complicated, such as metallizing treatment usually applied to the ceramic plate. Furthermore, since the ceramic plate and the highly thermally conductive substrate are joined by solder, the bonding strength is low, and there is also a concern that the ceramic plate may peel or crack due to the difference in thermal expansion between the ceramic plate and the highly thermally conductive substrate.
一方、電気絶縁層の形状あるいは耐圧は回路の使用目的
に応じて選定されるが、焼成したセラミックス板を用い
る場合には、その大きさ、形状、厚さ等を任意に変えて
製造することは取扱上あるいは価格上不利になるので、
ある一定の規格品を使用しているのが現状である。On the other hand, the shape or withstand voltage of the electrical insulating layer is selected depending on the intended use of the circuit, but when using a fired ceramic plate, it is not possible to manufacture it by arbitrarily changing its size, shape, thickness, etc. Because it is disadvantageous in terms of handling or price,
Currently, certain standard products are used.
一方、電気絶縁層に導体及び電子部品等を接合する場合
もセラミックス板にメタライジング処理を施して半田で
接合する必要があるため、製造工程を更に複雑化し、製
造コストが高くなっている。On the other hand, when bonding conductors, electronic components, etc. to the electrically insulating layer, it is necessary to subject the ceramic plate to metallization treatment and to bond them with solder, which further complicates the manufacturing process and increases manufacturing costs.
これら現状の問題点を解決すべく種々の提案がなされて
いる0例えば、特開昭53−107665号公報及び特
開昭55−36915号公報等には高熱伝導性基板にセ
ラミックス粉末をプラズマ溶射して電気絶縁層を形成す
る方法が配穀されている。この方法は、高熱伝導性基板
に直接電気絶縁層を形成でき、半田による接合が不要と
なるため工数低減できる6更に、従来の焼成したアルミ
ナ板を高熱伝導性基板に接合するものに比べれば薄い電
気絶縁層を形成でき、ある程度熱抵抗を小さくできる。Various proposals have been made in order to solve these current problems. There is a method of forming an electrically insulating layer. This method enables the formation of an electrically insulating layer directly on a highly thermally conductive substrate, which eliminates the need for soldering and reduces the number of man-hours.6 Furthermore, it is thinner than the conventional method of bonding a fired alumina plate to a highly thermally conductive substrate. An electrical insulating layer can be formed and thermal resistance can be reduced to some extent.
しかしながら、近年、電子回路部品の高出力化に伴う熱
抵抗の小さい電気絶縁層及び集積回路の薄型化の要求が
増々高くなっており、プラズマ溶射法による絶縁層は気
孔等を皆無にすることは困難で、気孔等による熱抵抗の
面からこの技術でも対応できなくなったものも出てきて
いる。However, in recent years, as the output of electronic circuit components has increased, there has been an increasing demand for electrical insulating layers with low thermal resistance and thinner integrated circuits. This is difficult, and there are some cases where even this technology cannot be used due to thermal resistance caused by pores, etc.
〔発明が解決しようとする問題点〕
上記従来技術は高出力化、薄型化の要請に対応できなく
なったものである。すなわち、高出力化に伴って素子あ
るいは回路の発熱量が多くなり、放熱特性を高める必要
があるが、それが低かった。[Problems to be Solved by the Invention] The above-mentioned conventional techniques are unable to meet the demands for higher output and thinner devices. That is, as the output increases, the amount of heat generated by elements or circuits increases, and it is necessary to improve heat dissipation characteristics, but the heat dissipation characteristics have been low.
その対策としては電気絶縁層の厚さを電気絶縁性が保た
れる範囲で薄く、かつ1層を緻密に形成して熱抵抗を小
さくすることがよい、更に、高熱伝導性基板と電気絶縁
層とは機械的な結合状態ではなく、原子的結合状態にす
ることがよい。すなわち、境界が明確でなく、熱伝達の
障害となる境界がない状態がよい。また、高熱伝導性基
板と電気絶縁層間及び電気絶縁層内には熱抵抗を大きく
する気孔等の欠陥のない緻密な層が形成されていること
がよい。As a countermeasure, it is best to reduce the thickness of the electrical insulating layer to the extent that electrical insulation is maintained, and to form one layer densely to reduce thermal resistance. should be in an atomic bonded state rather than a mechanical bonded state. In other words, it is preferable that the boundaries are not clear and that there are no boundaries that impede heat transfer. Further, it is preferable that a dense layer without defects such as pores that increase thermal resistance be formed between the highly thermally conductive substrate and the electrical insulating layer and within the electrical insulating layer.
一方、電子回路基板を作製する場合、温度を極力低く抑
えることが望ましい。例えば、電気絶縁層の接合あるい
は層形成時、電気絶縁層のメタライジング処理及び電子
回路部品や導体の接合時には温度を上げる必要があり、
この温度を極力低くすることが必要である。それは、高
温で処理すると、電気絶縁層(セラミックス)と高熱伝
導性基板は熱膨張係数が異なるため、加熱あるいは冷却
時に剥離や割れを生ずることがあるからである。On the other hand, when manufacturing an electronic circuit board, it is desirable to keep the temperature as low as possible. For example, it is necessary to raise the temperature when bonding or forming electrical insulating layers, metallizing processing of electrical insulating layers, and bonding electronic circuit components and conductors.
It is necessary to keep this temperature as low as possible. This is because when processed at high temperatures, the electrical insulating layer (ceramic) and the highly thermally conductive substrate have different coefficients of thermal expansion, which may cause peeling or cracking during heating or cooling.
また、変形も生じ易く、後加工によって表面を平にして
電子部品及び導体を接合しなければならないことにもな
る。上述したプラズマ溶射法で電気絶縁層上への金属薄
層を形成する場合には、密着性を高めるために高温にす
る必要があり、ある程度の変形はさけられなかった。ま
た、セラミックス粉末を使用するため、その粒子径によ
って電気絶縁層の厚さも左右される0粒子の形状、大き
さを一定にすることは多大な工数と技術が必要である。In addition, deformation is likely to occur, and the surface must be flattened through post-processing to bond electronic components and conductors. When forming a thin metal layer on an electrically insulating layer by the plasma spraying method described above, it is necessary to raise the temperature to improve adhesion, and some degree of deformation is unavoidable. Furthermore, since ceramic powder is used, a large amount of man-hours and technology are required to make the shape and size of the zero particles constant, since the thickness of the electrically insulating layer is also influenced by the particle diameter.
したがって、ある程度不均一な粒子径のセラミック粉末
を使用するため層の厚さも不均一となり、粒子径をある
程度の大きさ以上にしないと溶射時の粒径流れが悪くな
ることもある0粒子によっては1個の径が数十μmのも
のもあり、これらの粒子を積み重ねて層を形成するため
、電気絶縁層の厚さを薄くすることは困難であり、かつ
、溶射法では空孔を皆無にすることは極めてむすかしく
1゜
本発明の目的は、高熱伝導性基板の所望部分に高熱伝導
性基板との境界が明確でない緻密な電気絶縁層を形成す
ることができ、密着性に優れ、放熱特性に優れ、これに
より電子部品の高出力化の要請にも対処することができ
る電子回路基板及びその製造方法を提供することにある
。Therefore, since ceramic powder with a somewhat non-uniform particle size is used, the layer thickness will also be non-uniform, and if the particle size is not made larger than a certain level, the particle size flow during thermal spraying may deteriorate. Some particles have a diameter of several tens of micrometers, and because these particles are piled up to form a layer, it is difficult to reduce the thickness of the electrical insulation layer, and thermal spraying eliminates all pores. It is extremely difficult to do so.1゜An object of the present invention is to be able to form a dense electrical insulating layer with no clear boundary between the highly thermally conductive substrate and the desired portion of the highly thermally conductive substrate. An object of the present invention is to provide an electronic circuit board and a method for manufacturing the same which have excellent characteristics and can meet the demands for higher output of electronic components.
本発明の他の目的は、電気絶縁層の所望部分に電気絶縁
物との境界が明確でなく、密着性に優れ、電子部品ある
いは導体を直接接合でき、放熱特性に優れた金属層が形
成された電子回路基板及びその製造方法を提供するにあ
る。Another object of the present invention is to form a metal layer in a desired portion of the electrical insulating layer that has no clear boundary with the electrical insulating material, has excellent adhesion, allows direct bonding of electronic components or conductors, and has excellent heat dissipation properties. An object of the present invention is to provide an electronic circuit board and a method for manufacturing the same.
本発明の更に他の目的は、金属層と電気絶縁層。Yet another object of the invention is a metal layer and an electrically insulating layer.
及び電気絶縁層と高熱伝導性基板との各境界を明確でな
くすることにより金属層上に配設された電子部品からの
発熱に対する放熱特性に優れた電子回路装置を提供する
にある。Another object of the present invention is to provide an electronic circuit device that has excellent heat dissipation characteristics for heat generated from electronic components disposed on a metal layer by making the boundaries between an electrically insulating layer and a highly thermally conductive substrate unclear.
〔問題点を解決するための手段・作用〕第1発明(特許
請求の範囲第1項)は、高熱伝導性基板に電気絶縁層が
形成された電子回路基板において、電気絶縁層及び高熱
伝導性基板がその接合面にてそれぞれ他方の部材側に向
って濃度が減少する濃度勾配を有する電子回路基板であ
る。[Means/effects for solving the problem] The first invention (Claim 1) provides an electronic circuit board in which an electrically insulating layer is formed on a highly thermally conductive substrate. This is an electronic circuit board in which the substrate has a concentration gradient in which the concentration decreases toward the other member at its bonding surface.
これにより、電気絶縁層と高熱伝導性基板との明確な境
界がなくなり、連続的に素材が一方から他方に変わるた
め熱抵抗が小さくなる。As a result, there is no clear boundary between the electrically insulating layer and the highly thermally conductive substrate, and the material changes continuously from one side to the other, reducing thermal resistance.
第2発明(特許請求の範囲第3項)は、高熱伝導性基板
に蒸着法又はスパッタリング法による蒸着層の形成と、
この蒸着層へ該蒸着層との反応により電気絶縁層を生成
する反応イオン種の注入とを同時に又は交互に行なって
高熱伝導性基板に電気絶縁層を形成する電子回路基板の
製造方法である。The second invention (Claim 3) includes forming a vapor deposition layer on a highly thermally conductive substrate by vapor deposition or sputtering;
This is a method of manufacturing an electronic circuit board in which an electrically insulating layer is formed on a highly thermally conductive substrate by simultaneously or alternately implanting reactive ion species that generate an electrically insulating layer by reaction with the vaporized layer.
蒸着法又はスパッタリング法により粒径を小さくして蒸
着層が形成されるため、空孔なく極薄層を形成できる。Since the vapor deposited layer is formed by reducing the particle size by vapor deposition or sputtering, an extremely thin layer can be formed without voids.
また、反応イオン種の注入により発熱し蒸着層はセラミ
ックス等の電気絶縁層に変わり、かつ注入イオン種の有
する運動エネルギーによって高熱伝導性基板の表面部分
にてその素材成分がスパッタリングされて蒸着層側に飛
び出し、全体として電気絶縁層と高熱伝導性基板の境界
は明確でなくなる。すなわち混合層の状態となる。In addition, the injection of reactive ion species generates heat and transforms the vapor deposited layer into an electrically insulating layer such as ceramics, and the material components are sputtered on the surface of the highly thermally conductive substrate due to the kinetic energy possessed by the implanted ion species, so that the vapor deposition layer side The boundary between the electrically insulating layer and the highly thermally conductive substrate becomes unclear as a whole. In other words, it becomes a mixed layer state.
第3発明(特許請求の範囲第5項)は、高熱伝導性基板
に電気絶縁層が形成され、この電気絶縁層上に金属層が
形成された電子回路基板において、金属層及び電気絶縁
層がその接合面にてそれぞれ他方の部材側に向って濃度
が減少する濃度勾配を有する電子回路基板である。A third invention (Claim 5) provides an electronic circuit board in which an electrically insulating layer is formed on a highly thermally conductive substrate, and a metal layer is formed on the electrically insulating layer. The electronic circuit board has a concentration gradient in which the concentration decreases toward the other member at the bonding surface.
これにより、金属層と電気絶縁層との明確な境界がなく
なり、連続的に素材が一方から他方に変わるため熱抵抗
が小さくなる。As a result, there is no clear boundary between the metal layer and the electrically insulating layer, and the material changes continuously from one to the other, reducing thermal resistance.
第4発明(特許請求の範囲第8項)は、高熱伝導性基板
に形成された電気絶縁層上に蒸着法又はスパッタリング
法による金属層の形成と、この金属層へ該金属とは反応
しない非反応イオン種の注入とを同時又は交互に行なう
電子回路基板の製造方法である。The fourth invention (Claim 8) is to form a metal layer by vapor deposition or sputtering on an electrical insulating layer formed on a highly thermally conductive substrate, and to add a non-reactive material to the metal layer that does not react with the metal. This is a method of manufacturing an electronic circuit board in which implantation of reactive ion species is performed simultaneously or alternately.
蒸着法又はスパッタリング法により粒径小さくして金属
層が形成されるため、空孔なくかつ極薄な金属層を形成
できる。また、非反応イオン種の注入により、その有す
る運動エネルギーによって電気絶縁層の表面部分にてそ
の素材成分がスパッタリングされて金属層側に飛び出し
、全体として金属層と電気絶縁層の境界は明確でなくな
る。すなわち混合層の状態となる。Since the metal layer is formed by reducing the particle size by vapor deposition or sputtering, it is possible to form an extremely thin metal layer without voids. In addition, due to the implantation of non-reactive ion species, the material components are sputtered on the surface of the electrically insulating layer due to the kinetic energy of the non-reactive ion species and ejected to the metal layer side, making the boundary between the metal layer and the electrically insulating layer unclear as a whole. . In other words, it becomes a mixed layer state.
第5発明(特許請求の範囲第10項)は、高熱伝導性基
板に電気絶縁層が形成され、この電気絶縁層上に金属層
が形成され、前記電気絶縁層及び高熱伝導性基板がその
接合面にてそれぞれ他方の部材側に向って濃度が減少す
る濃度勾配を有し、前記金属層及び電気絶縁層がその接
合面にてそれぞれ他方の部材側に向って濃度が減少する
濃度勾配を有し、この金属層上に電子部品及び必要な導
体が配設された電子回路装置である。A fifth invention (Claim 10) provides that an electrical insulating layer is formed on a highly thermally conductive substrate, a metal layer is formed on the electrically insulating layer, and the electrically insulating layer and the highly thermally conductive substrate are bonded together. The metal layer and the electrical insulating layer each have a concentration gradient in which the concentration decreases toward the other member at the bonding surface thereof, and the metal layer and the electrical insulating layer each have a concentration gradient in which the concentration decreases toward the other member at the bonding surface thereof. However, it is an electronic circuit device in which electronic components and necessary conductors are arranged on this metal layer.
これより、電子部品の高出力化に対して、金属層から電
気絶縁基板を経て高熱伝導性基板への熱放出が各境界が
連続的な混合層となっていることにより良好となる。As a result, when increasing the output of electronic components, heat can be released from the metal layer to the highly thermally conductive substrate via the electrically insulating substrate because each boundary is a continuous mixed layer.
本発明の電子回路基板は高熱伝導性基板上に直接電気絶
縁層の薄層が形成され、この電気絶縁層は高熱伝導性基
板の材料との混合層によって結合されている。電気絶縁
層の形成方法は金属の蒸着法もしくはスパッタリング法
による蒸着層の形成と窒素イオンあるいは酸素イオン等
の前記蒸着層との反応により電気絶縁層を形成する反応
イオン種の注入との組合わせによって形成される。すな
わち1本発明の電子回路基板は電気絶縁層が高熱伝導性
基板側から当該電気絶縁層側に向って増加する濃度勾配
をもち、高熱伝導性基板との明確な境界をもたない状態
になっている。また、電気絶縁層が蒸着法あるいはスパ
ッタリング法と1反応イオン注入法との組合わせにより
形成するため、粒径が小さくでき緻密で薄い層が形成で
きる。したがって、高熱伝導性基板との密着性に優れ、
熱抵抗が極めて小さく、電子部品の高出力化にも対処で
きるものである。The electronic circuit board of the present invention has a thin electrically insulating layer formed directly on a highly thermally conductive substrate, and this electrically insulating layer is bonded by a mixed layer with the material of the highly thermally conductive substrate. The method for forming the electrically insulating layer is a combination of forming a vaporized layer by metal vapor deposition or sputtering and implanting reactive ion species such as nitrogen ions or oxygen ions that form the electrically insulating layer by reacting with the vaporized layer. It is formed. In other words, in the electronic circuit board of the present invention, the electrical insulating layer has a concentration gradient increasing from the high thermal conductive substrate side to the electrical insulating layer side, and has no clear boundary with the high thermal conductive substrate. ing. Further, since the electrical insulating layer is formed by a combination of a vapor deposition method or a sputtering method and a one-reaction ion implantation method, the grain size can be reduced and a dense and thin layer can be formed. Therefore, it has excellent adhesion with high thermal conductivity substrates,
It has extremely low thermal resistance and can handle high output electronic components.
電気絶縁層の形成方法であるが、高熱伝導性基板の所望
部分に形成したい窒化物あるいは酸化物の原料である金
属等を蒸着法あるいはスパッタリング法によって蒸着層
を形成しながら窒素イオンあるいは酸素イオンを注入す
る。すなわち、加速された窒素イオンあるいは酸素イオ
ンは高熱伝導性基板及び蒸着層へ注入されて発熱し、こ
の蒸着層と注入されたイオンとの反応により電気絶縁層
となる窒化物あるいは酸化物を形成する。この時、高熱
伝導性基板は反応イオン種が注入されるため、それ自身
スパッタリングされて飛び出し、蒸着金属粒子と混合さ
れた状態となって混合層が形成される。しかし、この現
象は成膜初期段階のみであり、成膜厚さの増加とともに
高熱伝導性基板まで反応イオン種は注入されなくなり、
高熱伝導性基板のスパッタリングは起こらなくなる。反
応イオン種の加速電圧にもよるが、成膜した窒化物ある
いは酸化物がスパッタリングされることもあり、望まし
くは混合層を形成する時には加速電圧を高5<シ、混合
層が形成されたら加速電圧を低くしてスパッタリングを
さけることがよい。また、反応イオン種の加速電圧及び
蒸着層の成膜厚さにもよるが、蒸着層形成と反応イオン
種の注入とを交互に行なっても同様の結果が得られる。The method for forming an electrically insulating layer is to form a vapor deposited layer using a vapor deposition method or a sputtering method while applying nitrogen ions or oxygen ions to a desired portion of a highly thermally conductive substrate. inject. That is, accelerated nitrogen ions or oxygen ions are injected into a highly thermally conductive substrate and a vapor deposited layer to generate heat, and the vapor deposited layer reacts with the implanted ions to form a nitride or oxide that becomes an electrically insulating layer. . At this time, since the highly thermally conductive substrate is injected with reactive ion species, it is sputtered and sputtered, and is mixed with the deposited metal particles to form a mixed layer. However, this phenomenon occurs only at the initial stage of film formation, and as the film thickness increases, reactive ion species are no longer implanted into the highly thermally conductive substrate.
Sputtering of highly thermally conductive substrates no longer occurs. Depending on the accelerating voltage of the reactive ion species, the formed nitride or oxide may be sputtered, so it is preferable to set the accelerating voltage to a high level of 5 < 5 when forming the mixed layer, and then accelerate once the mixed layer is formed. It is better to lower the voltage to avoid sputtering. Further, although it depends on the accelerating voltage of the reactive ion species and the thickness of the deposited layer, similar results can be obtained even if the formation of the deposited layer and the implantation of the reactive ion species are performed alternately.
しかし、蒸着層の膜厚が厚く、加速電圧が低い場合には
混合層が形成されず密着力は極めて弱い。したがって、
加速電圧及び蒸着層厚を適切に選定する必要がある。However, if the thickness of the deposited layer is thick and the accelerating voltage is low, no mixed layer is formed and the adhesion is extremely weak. therefore,
It is necessary to appropriately select the accelerating voltage and the thickness of the deposited layer.
電気絶縁層の膜質であるが、蒸着粒子あるいはスパッタ
リング粒子は非常の微細であり、これらの粒子が積み重
なって層を形成するため5層は非常に緻密なものになる
。したがって、空孔等の介在しない熱抵抗の小さい電気
絶縁層が得られる。Regarding the film quality of the electrical insulating layer, the vapor deposited particles or sputtered particles are very fine, and since these particles are piled up to form a layer, the five layers are extremely dense. Therefore, an electrical insulating layer with low thermal resistance without intervening holes or the like can be obtained.
また1粒子径が小さいため、電気絶縁層の厚さを人オー
ダーで自由に調整でき、必要に応じて膜厚を任意に形成
できる。In addition, since the single particle size is small, the thickness of the electrical insulating layer can be freely adjusted according to human orders, and the film thickness can be formed as desired.
一方、電気絶縁層上に金属層を形成する場合には、金属
層形成金属と反応しない非反応イオン種であるアルゴン
ガス、ヘリウムガスあるいは窒素ガス等の不活性ガスを
用いる。金属層形成金属と反応するガスを用いた場合に
は化合物層が形成されて好ましくない、また、金属層は
純金属あるいは合金を蒸着法あるいスパッタリング法で
膜を形成するかあるいは二種以上の金属を同時に蒸着法
もしくはスパッタリング法で形成する方法でも同じよう
な結果が得られる。この際、非反応イオン種の注入によ
り、その有する運動エネルギーによって電気絶縁層上で
スパッタリングが起こり、それ自身粒子となって飛び出
すため、金属層内に電気絶縁層の材料が混入した混合層
となり、両者の境界は不明確となる。濃度勾配は金属層
及び電気絶縁層がその接合面にてそれぞれ他方の部材側
に向って濃度が減少するようになっている。On the other hand, when forming a metal layer on an electrically insulating layer, an inert gas such as argon gas, helium gas, or nitrogen gas, which is a non-reactive ion species that does not react with the metal forming the metal layer, is used. Metal layer formation If a gas that reacts with the metal is used, a compound layer will be formed, which is undesirable.Also, the metal layer may be formed by vapor deposition or sputtering of a pure metal or an alloy, or by using a mixture of two or more types of metal. Similar results can be obtained by simultaneously forming metal by vapor deposition or sputtering. At this time, due to the implantation of non-reactive ion species, sputtering occurs on the electrical insulating layer due to the kinetic energy of the non-reactive ion species, which themselves fly out as particles, resulting in a mixed layer in which the material of the electrical insulating layer is mixed into the metal layer. The boundary between the two becomes unclear. The concentration gradient is such that the concentration of the metal layer and the electrically insulating layer decreases toward the other member at the bonding surface thereof.
上述したような方法で電気絶縁層及び金属層を形成する
が、加速されたイオンの運動エネルギーが熱エネルギー
に変換されて発生する熱は極表面層のみであり、したが
って、高熱伝導性基板の変質がなく、変形も極めて少な
い。万一温度が上がるような場合には高熱伝導性基板を
冷却するかもしくはイオン注入を断続的に行う方法で解
決できる。冷却あるいは断続的注入でも絶縁物形成に何
ら影響はない。Although the electrical insulating layer and the metal layer are formed by the method described above, the kinetic energy of accelerated ions is converted into thermal energy and the heat generated is only in the extreme surface layer, so that the highly thermally conductive substrate may be deteriorated. There is no deformation, and there is very little deformation. If the temperature should rise, this can be solved by cooling the highly thermally conductive substrate or by intermittent ion implantation. Cooling or intermittent implantation has no effect on insulator formation.
電気絶縁層上に形成する金属層であるが、高融点ろう材
では電子部品及び導体を接合する場合に高温にする必要
があり、電子部品の機能損傷あるいは変形等が生じて好
ましくない。したがって。This is a metal layer formed on an electrical insulating layer, and high melting point brazing filler metal requires high temperatures when bonding electronic components and conductors, which is undesirable as it may cause functional damage or deformation of the electronic components. therefore.
低融点のろう材すなわち軟ろう材が好ましく、望ましく
はPb−5n系合金(半田)等の導体や電子部品等との
漏れ性の良好な低融点のろう材が特に望ましい。A low melting point brazing filler metal, that is, a soft brazing filler metal is preferable, and a low melting point brazing filler metal having good leakage properties with conductors such as Pb-5n alloy (solder) and electronic parts is particularly desirable.
一方、高熱伝導性基板上に形成する電気絶縁層である窒
化物あるいは酸化物としては、熱伝導性。On the other hand, nitrides or oxides, which are electrically insulating layers formed on highly thermally conductive substrates, are thermally conductive.
電気絶縁性の点から窒化アルミニウム、酸化アルミニウ
ム、窒化硅素、窒化ホウ素等が特に望ましい。但し、こ
れら上記した窒化物及び酸化物に限定するものではなく
、熱伝導性、電気絶縁性の優れたものであればよい。From the viewpoint of electrical insulation, aluminum nitride, aluminum oxide, silicon nitride, boron nitride, etc. are particularly preferred. However, the material is not limited to the above-mentioned nitrides and oxides, and any material having excellent thermal conductivity and electrical insulation may be used.
以上のような方法で形成した高熱伝導性基板上の電気絶
縁層及び該電気絶縁層上の金属層はそれぞれ境界が明瞭
でなく濃度勾配があり、かつ、層は緻密であるため、密
着性、電気絶縁性に優れ、熱抵抗が小さく電子回路基板
の具備すべき条件を十分満足するものである。すなわち
、本発明の電子回路基板は熱抵抗を大きくする高熱伝導
性基板と電気絶縁物層及び電気絶縁物層と金属層との境
界が明確でない。明確な境界がない場合には高熱伝導性
基板に熱伝達がスムーズに行なえるが、明確な境界があ
る場合には境界が熱伝達の障害となり高熱伝導性基板へ
の放熱がスムーズに行なえず熱が蓄積され、電子部品等
の損傷の原因となる。The electrical insulating layer on the highly thermally conductive substrate formed by the method described above and the metal layer on the electrical insulating layer have indistinct boundaries and concentration gradients, and the layers are dense, so the adhesion and It has excellent electrical insulation and low thermal resistance, fully satisfying the requirements for electronic circuit boards. That is, in the electronic circuit board of the present invention, the boundaries between the highly thermally conductive substrate and the electrical insulating layer, which increase thermal resistance, and the electrical insulating layer and the metal layer are not clear. If there is no clear boundary, heat can be transferred smoothly to the highly thermally conductive substrate, but if there is a clear boundary, the boundary becomes an obstacle to heat transfer and heat cannot be dissipated smoothly to the highly thermally conductive substrate. can accumulate and cause damage to electronic components, etc.
また、本発明の電気絶縁層は熱抵抗の障害となる空孔の
介在もなく、緻密な層であるため高熱伝導性基板への熱
伝達がスムーズに行なえ熱の蓄積もない。更に、電気絶
縁性の必要に応じて膜厚を調整でき、熱抵抗を小さくす
ることが可能であり、かつ、電子回路基板の薄型化へも
寄与できる。また、密着性に優れることから1層形成時
及び電子部品や導体接合時に剥離等の心配もない。Furthermore, the electrical insulating layer of the present invention has no intervening pores that would impede thermal resistance, and since it is a dense layer, heat can be smoothly transferred to the highly thermally conductive substrate and there is no accumulation of heat. Furthermore, the film thickness can be adjusted as required for electrical insulation, thermal resistance can be reduced, and it can also contribute to thinning of electronic circuit boards. Furthermore, since it has excellent adhesion, there is no fear of peeling when forming a single layer or when bonding electronic components or conductors.
以上のように、本発明の電子回路基板は電子回路基板と
しての具備すべき条件を満足し、熱抵抗が極めて小さく
、高出力化にも十分対処できるものである。As described above, the electronic circuit board of the present invention satisfies the requirements for an electronic circuit board, has extremely low thermal resistance, and can sufficiently handle high output.
実琥例1
高熱伝導性基板として無酸素銅板(厚さ0 、8 rm
。Miyu Example 1 Oxygen-free copper plate (thickness 0, 8 rm
.
30X30mm)を用い、真空容器内の水冷ターゲット
に取付け、容器内を10−BTorr以下に排気した後
、高熱伝導性基板上にアルミニウム、ボロン。30 x 30 mm) was attached to a water-cooled target in a vacuum container, and after evacuating the inside of the container to 10-B Torr or less, aluminum and boron were placed on a highly thermally conductive substrate.
硅素をそれぞれの、基板上に蒸着させながら窒素イオン
を注入し、窒化アルミニウム、窒化ボロン。Implant nitrogen ions while depositing silicon, aluminum nitride, and boron nitride onto the substrate, respectively.
窒化硅素の膜を50μm厚さに形成した。成膜条件は蒸
着速度11人/S、加速電圧:20kV。A silicon nitride film was formed to a thickness of 50 μm. The film forming conditions were a deposition rate of 11 people/s, and an acceleration voltage of 20 kV.
電流:0.LA、窒素イオン注入量:2X10’δ個イ
オン/dである。次に、このようにして成膜した各々の
窒化物である電気絶縁物の薄層上に、電子部品及び導体
に対応した形状以外の部分にマスキングを施し、電気絶
縁層の形成時と同様の方法でPb−Sn合金を蒸着しな
がらアルゴンイオンを注入した。これによりマスキング
を施さない部分にPb−Sn合金の金属層を形成した。Current: 0. LA, nitrogen ion implantation amount: 2×10′δ ions/d. Next, on each of the thin layers of nitride electrical insulators formed in this way, areas other than the shapes corresponding to the electronic components and conductors are masked, and the same process as when forming the electrical insulating layer is applied. Argon ions were implanted while depositing the Pb-Sn alloy using the method. As a result, a Pb-Sn alloy metal layer was formed in the portions that were not masked.
膜厚は25μmである。このようにして作成した基板の
Pb−Sn合金薄膜上に電子部品及び導体を載せて約3
00℃に加熱して接合し、更に公知の方法によりリード
線を接続して第1図に示す電子回路装置を作製した。な
お比較のため第2図にAQzOsの電気絶縁層を溶射法
で形成した従来の電子回路装置を示す。この電気絶縁層
の膜厚は0.1膣である。本発明の電子回路装置は高熱
伝導性基板1上に金属等の蒸着層の形成と窒素イオン注
入との組合わせによって形成した電気絶縁層2が形成さ
れ、この電気絶縁層2上にはpb−Sn合金の金属層3
が形成されている。4はメタライジング層、5は半導体
素子(Si素子)、6はCuリード線である。比較例で
は電気絶縁層2上に半田3が直接接合できないためメタ
ライジング層4が形成されている。高熱伝導性基板1と
電気絶縁層2とも直接接合できないため、メタライジン
グ層4が形成されている。これら第1図に示す電子回路
装置と第2図に示す従来の電子回路装置の高熱伝導性基
板1と電気絶縁層2との密着力を調べた。第1表はその
結果であり、比較例では1 、5〜3 、0 kg /
m 2程度の密着力であるが、本発明の電子回路装置
の密着力はいずれも7kg/nu”以上で極めて高い密
着力を示し、信頼性の高い絶縁層2が得られた。The film thickness is 25 μm. Electronic components and conductors were placed on the Pb-Sn alloy thin film of the substrate created in this way.
The electronic circuit device shown in FIG. 1 was fabricated by heating to 00° C. for bonding, and then connecting lead wires by a known method. For comparison, FIG. 2 shows a conventional electronic circuit device in which an electrical insulating layer of AQzOs is formed by thermal spraying. The thickness of this electrically insulating layer is 0.1 mm. In the electronic circuit device of the present invention, an electrical insulating layer 2 is formed on a highly thermally conductive substrate 1 by a combination of forming a vapor deposited layer of metal or the like and implanting nitrogen ions. Sn alloy metal layer 3
is formed. 4 is a metallizing layer, 5 is a semiconductor element (Si element), and 6 is a Cu lead wire. In the comparative example, a metallizing layer 4 is formed on the electrical insulating layer 2 because the solder 3 cannot be directly bonded thereto. Since the highly thermally conductive substrate 1 and the electrical insulating layer 2 cannot be directly bonded, a metallizing layer 4 is formed. The adhesion between the highly thermally conductive substrate 1 and the electrical insulating layer 2 of the electronic circuit device shown in FIG. 1 and the conventional electronic circuit device shown in FIG. 2 was investigated. Table 1 shows the results, and in the comparative example, 1, 5 to 3, 0 kg/
Although the adhesion force was about 2 m2, the adhesion force of the electronic circuit devices of the present invention was all 7 kg/nu'' or more, showing extremely high adhesion force, and a highly reliable insulating layer 2 was obtained.
第 1 表
また、従来の電子回路装置及び本発明の電子回路装置の
電気絶縁層2を厚さ方向にオージェ電子分光分析により
掘り下げながら高熱伝導性基板1まで分析した結果第3
図に示すような結果が得られた。すなわち、本発明の電
子回路基板は電気絶縁層2であるAQNの濃度が高熱伝
導性基板1側に向って徐々に減少し、逆にその基板1の
基材である銅が徐々に増加している。これに比し、従来
のものは急激な変化を示している。すなわち、本発明の
電子回路基板は高熱伝導性基板と電気絶縁層の接合面に
混合層が形成されていることがわかる。したがって、明
確な境界がないため、密着力も高い値を示したものであ
る。また、このように、境界が明確でないことから放熱
特性もおのずから優れることが容易に推察できる。Table 1 also shows the results of analyzing the electrical insulating layer 2 of the conventional electronic circuit device and the electronic circuit device of the present invention down to the highly thermally conductive substrate 1 while digging in the thickness direction by Auger electron spectroscopy.
The results shown in the figure were obtained. That is, in the electronic circuit board of the present invention, the concentration of AQN, which is the electrical insulating layer 2, gradually decreases toward the highly thermally conductive substrate 1, and conversely, the concentration of copper, which is the base material of the substrate 1, gradually increases. There is. In comparison, the conventional one shows a rapid change. That is, it can be seen that in the electronic circuit board of the present invention, a mixed layer is formed on the bonding surface between the highly thermally conductive substrate and the electrical insulating layer. Therefore, since there is no clear boundary, the adhesion force also shows a high value. Furthermore, since the boundaries are not clear, it can be easily inferred that the heat dissipation properties are naturally excellent.
実験例2
高熱伝導性基板として炭素鋼(C量0.06%)板(4
0mX40田X1.6mm)を用い、実験例1と同様の
方法でアルミニウムを蒸着しながら酸素イオンを注入し
基材上に約50μmの酸化アルミニウム層を形成した。Experimental Example 2 Carbon steel (C content 0.06%) plate (4
Using the same method as in Experimental Example 1, oxygen ions were implanted while depositing aluminum to form an aluminum oxide layer of about 50 μm on the base material.
次いで実験例1と同様に不必要な部分にマスキングを施
し、銅を蒸着しながらヘリウムイオンを注入して酸化ア
ルミニウム層上に銅よりなる金属層を約50μm形成し
た。Next, as in Experimental Example 1, unnecessary portions were masked, and helium ions were implanted while copper was being deposited to form a metal layer of copper with a thickness of about 50 μm on the aluminum oxide layer.
次に公知の方法により電子部品及びリード線を半田付け
して電子回路装置を作成した。比較例として実験例1と
同様に溶射法によってAQzOsの絶縁層を形成したも
のを用いた。またA Q z Osの絶縁層上に銅を溶
射し、次いで電子部品及びリード線を半田付けして電子
回路装置を作成した。これら本発明及び従来の電子回路
装置の絶縁層と銅層の密着力を測定した結果、従来のも
のは2〜3kg/IIfi2であるのに対し、本発明の
ものは8.5〜10kg/1ff112と極めて良好な
密着力を示した。Next, electronic components and lead wires were soldered using a known method to create an electronic circuit device. As a comparative example, an insulating layer of AQzOs was formed by the thermal spraying method in the same manner as in Experimental Example 1. Further, copper was thermally sprayed onto the A Q z Os insulating layer, and then electronic components and lead wires were soldered to create an electronic circuit device. As a result of measuring the adhesion strength between the insulating layer and the copper layer of the electronic circuit devices of the present invention and the conventional electronic circuit devices, the adhesion strength of the conventional device was 2 to 3 kg/IIfi2, while that of the present invention was 8.5 to 10 kg/1ff112. It showed extremely good adhesion.
また、これらの電子回路基板の熱抵抗を測定した結果、
従来のものは1.8℃/Wであるのに対し、本発明のも
のは1.2℃/Wで、従来に比較して約33%改善され
た。これも本発明では境界が混合層となっているからと
考えられる。In addition, as a result of measuring the thermal resistance of these electronic circuit boards,
While the conventional one had a temperature of 1.8°C/W, the one of the present invention had a temperature of 1.2°C/W, which was an improvement of about 33% compared to the conventional one. This is also considered to be because in the present invention, the boundary is a mixed layer.
実験例3
高熱伝導性基板としてFe−42%Ni合金(30mm
X 30mmX 1.6mm ) 香用い実験例1と同
様にアルミニウムをスパッタリングして同基板上に成膜
させながら窒素イオンを注入して約60μmの窒化アル
ミニウム層を形成し、更にその上に実験例1と同様に必
要以外の部分にマスキングを施して銅をスパッタリング
しながらアルゴンイオンを注入して銅よりなる金属層を
形成した。次に銅層上に電子部品及びリード線を公知の
方法で半田付けして電子回路装置を作成した。この電子
回路装置の耐電圧を画定した結果、2000V以上であ
った。一般の絶縁型素子又はモジュールに要求される耐
圧は1500V以上であり、60μm程度の膜厚でも十
分に耐えることができる。Experimental Example 3 Fe-42%Ni alloy (30mm
x 30mm x 1.6mm) Similar to Experimental Example 1, aluminum was sputtered to form a film on the same substrate, while nitrogen ions were implanted to form an aluminum nitride layer of about 60 μm, and on top of that, Experimental Example 1 Similarly, a metal layer made of copper was formed by masking non-essential parts and implanting argon ions while sputtering copper. Next, electronic components and lead wires were soldered onto the copper layer by a known method to create an electronic circuit device. The withstand voltage of this electronic circuit device was determined to be 2000V or more. The withstand voltage required for general insulated elements or modules is 1500 V or more, and even a film thickness of about 60 μm can sufficiently withstand it.
ちなみに溶射法で作製したA Q 20 sの耐電圧は
90μmで約1500Vであり、本発明の電子回路基板
は薄くても耐電圧が高いことがわかる。したがって、同
じ耐電圧を要求される場合には膜厚を薄くすることがで
き、薄型化への要求に応することができる。Incidentally, the withstand voltage of A Q 20 s produced by the thermal spraying method is about 1500 V at 90 μm, indicating that the electronic circuit board of the present invention has a high withstand voltage even though it is thin. Therefore, when the same withstand voltage is required, the film thickness can be made thinner, and the demand for thinner thickness can be met.
以上のように、本発明の電子回路基板は半導体素子、抵
抗、コンデンサなどに応用できる。As described above, the electronic circuit board of the present invention can be applied to semiconductor elements, resistors, capacitors, etc.
第1発明(特許請求の範囲第1項)及び第3発明(特許
請求の範囲第5項)によれば、境界が明確でなくなり連
続的に素材が一方から他方に変わるため、熱抵抗が小さ
くなる。したがって放熱特性を向上することができる。According to the first invention (Claim 1) and the third invention (Claim 5), the boundary is not clear and the material changes continuously from one side to the other, so the thermal resistance is small. Become. Therefore, heat dissipation characteristics can be improved.
第2発明(特許請求の範囲第3項)及び第4発明(特許
請求の範囲第8項)の製造方法によれば、粒径小さく蒸
着層を形成できるため、空孔なく極薄層を容易に形成で
き、全体の薄型化が可能となる。更に注入イオン種の有
する運動エネルギーによって基板側でスパッタリングが
起こるため境界の不明確な連続的混合層を容易に形成す
ることができる。このようにして形成した混合層により
、両者の密着力は高いものとなり、耐熱特性を向上する
こともできる。また、直接接合できない素材同士であっ
ても、本発明方法によれば直接接合できるため、従来の
ようなメタライジング層が不要となり、製造工数を低減
できコスト低下を図ることができる。According to the manufacturing methods of the second invention (Claim 3) and the fourth invention (Claim 8), it is possible to form a deposited layer with a small particle size, so it is easy to form an extremely thin layer without voids. This allows the overall thickness to be reduced. Furthermore, since sputtering occurs on the substrate side due to the kinetic energy of the implanted ion species, a continuous mixed layer with unclear boundaries can be easily formed. The mixed layer formed in this manner provides high adhesion between the two, and can also improve heat resistance properties. Furthermore, even if materials cannot be directly bonded to each other, they can be directly bonded using the method of the present invention, which eliminates the need for a conventional metallizing layer, thereby reducing the number of manufacturing steps and reducing costs.
第5発明(特許請求の範囲第10項)によれば、電子部
品の高出力化に充分対応することができると共に電子回
路装置の信頼性を向上することができる。According to the fifth invention (Claim 10), it is possible to sufficiently cope with the increase in the output of electronic components, and it is also possible to improve the reliability of the electronic circuit device.
第1図は本発明の一実施例を示す電子回路装置の断面図
、第2図は従来の電子回路装置の断面図、第3図は本発
明及び比較例のオージェ電子分光分析結果を示すグラフ
である。
1・・・高熱伝導性基板、2・・・電気絶縁層、3・・
・金属層、4・・・メタライジング層、5・・・Si素
子、6・・・Cuリード線。Fig. 1 is a cross-sectional view of an electronic circuit device showing an embodiment of the present invention, Fig. 2 is a cross-sectional view of a conventional electronic circuit device, and Fig. 3 is a graph showing the results of Auger electron spectroscopy of the present invention and a comparative example. It is. 1... High thermal conductive substrate, 2... Electrical insulating layer, 3...
-Metal layer, 4...Metallizing layer, 5...Si element, 6...Cu lead wire.
Claims (1)
路基板において、電気絶縁層及び高熱伝導性基板がその
接合面にてそれぞれ他方の部材側に向つて濃度が減少す
る濃度勾配を有することを特徴とする電子回路基板。 2、特許請求の範囲第1項において、電気絶縁層が窒化
アルミニウム、酸化アルミニウム、窒化硅素又は窒化ホ
ウ素のいずれかである電子回路基板。 3、高熱伝導性基板上に蒸着法又はスパッタリング法に
よる蒸着層の形成と、この蒸着層へ該蒸着層との反応に
より電気絶縁層を生成する反応イオン種の注入とを同時
に又は交互に行なつて高熱伝導性基板に電気絶縁層を形
成することを特徴とする電子回路基板の製造方法。 4、特許請求の範囲第3項において、蒸着層がアルミニ
ウム、硅素又はホウ素のいずれかであり、反応イオン種
が窒素イオン又は酸素イオンである電子回路基板の製造
方法。 5、高熱伝導性基板上に電気絶縁層が形成され、この電
気絶縁層上に金属層が形成された電子回路基板において
、金属層及び電気絶縁層がその接合面にてそれぞれ他方
の部材側に向つて濃度が減少する濃度勾配を有すること
を特徴とする電子回路基板。 6、特許請求の範囲第5項において、電気絶縁層及び高
熱伝導性基板がその接合面にてそれぞれ他方の部材側に
向つて濃度が減少する濃度勾配を有する電子回路基板。 7、特許請求の範囲第5項又は第6項において、金属層
が軟ろう材である電子回路基板。 8、高熱伝導性基板上に形成された電気絶縁層上に蒸着
法又はスパッタリング法による金属層の形成と、この金
属層へ該金属層とは反応しない非反応イオン種の注入と
を同時又は交互に行なうことを特徴とする電子回路基板
の製造方法。 9、特許請求の範囲第8項において、金属層が軟ろう材
であり、非反応イオン種がアルゴンイオン、ネオンイオ
ン、クセノンイオン又はヘリウムイオンである電子回路
基板の製造方法。 10、高熱伝導性基板上に電気絶縁層が形成され、この
電気絶縁層上に金属層が形成され、前記電気絶縁層及び
高熱伝導性基板がその接合面にてそれぞれ他方の部材側
に向つて濃度が減少する濃度勾配を有し、前記金属層及
び電気絶縁層がその接合面にてそれぞれ他方の部材側に
向つて濃度が減少する濃度勾配を有し、この金属層上に
電子部品及び必要な導体が配設された電子回路装置。[Claims] 1. In an electronic circuit board in which an electrically insulating layer is formed on a highly thermally conductive substrate, the electrically insulating layer and the highly thermally conductive substrate each have a concentration that decreases toward the other member at their joint surfaces. An electronic circuit board characterized in that it has a decreasing concentration gradient. 2. The electronic circuit board according to claim 1, wherein the electrical insulating layer is made of aluminum nitride, aluminum oxide, silicon nitride, or boron nitride. 3. Forming a vapor deposited layer on a highly thermally conductive substrate by vapor deposition or sputtering, and implanting reactive ion species that generate an electrically insulating layer by reaction with the vapor deposited layer into the vapor deposited layer, either simultaneously or alternately. 1. A method of manufacturing an electronic circuit board, comprising forming an electrical insulating layer on a highly thermally conductive substrate. 4. The method of manufacturing an electronic circuit board according to claim 3, wherein the vapor deposited layer is made of aluminum, silicon, or boron, and the reactive ion species is nitrogen ions or oxygen ions. 5. In an electronic circuit board in which an electrically insulating layer is formed on a highly thermally conductive substrate and a metal layer is formed on this electrically insulating layer, the metal layer and the electrically insulating layer are each on the side of the other member at the bonding surface thereof. An electronic circuit board characterized by having a concentration gradient in which the concentration decreases in the direction of the substrate. 6. An electronic circuit board according to claim 5, in which the electrical insulating layer and the highly thermally conductive substrate each have a concentration gradient at their bonding surface where the concentration decreases toward the other member. 7. The electronic circuit board according to claim 5 or 6, wherein the metal layer is a soft brazing material. 8. Forming a metal layer by vapor deposition or sputtering on an electrical insulating layer formed on a highly thermally conductive substrate and implanting non-reactive ionic species that do not react with the metal layer into this metal layer, either simultaneously or alternately. 1. A method of manufacturing an electronic circuit board, characterized in that the method comprises: 9. The method of manufacturing an electronic circuit board according to claim 8, wherein the metal layer is a soft brazing material and the non-reactive ion species are argon ions, neon ions, xenon ions, or helium ions. 10. An electrically insulating layer is formed on a highly thermally conductive substrate, a metal layer is formed on this electrically insulating layer, and the electrically insulating layer and the highly thermally conductive substrate each face the other member at their joint surfaces. The metal layer and the electrical insulating layer each have a concentration gradient in which the concentration decreases toward the other member at the bonding surface thereof, and electronic components and necessary components are formed on the metal layer. An electronic circuit device equipped with conductors.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62121593A JPS63285941A (en) | 1987-05-19 | 1987-05-19 | Electronic circuit substrate, manufacture of said substrate and electronic circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62121593A JPS63285941A (en) | 1987-05-19 | 1987-05-19 | Electronic circuit substrate, manufacture of said substrate and electronic circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63285941A true JPS63285941A (en) | 1988-11-22 |
Family
ID=14815092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62121593A Pending JPS63285941A (en) | 1987-05-19 | 1987-05-19 | Electronic circuit substrate, manufacture of said substrate and electronic circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63285941A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019135692A (en) * | 2018-02-05 | 2019-08-15 | 東芝ライテック株式会社 | Vehicular lighting system, vehicular lamp fitting, and socket manufacturing method |
-
1987
- 1987-05-19 JP JP62121593A patent/JPS63285941A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019135692A (en) * | 2018-02-05 | 2019-08-15 | 東芝ライテック株式会社 | Vehicular lighting system, vehicular lamp fitting, and socket manufacturing method |
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