JPS63280496A - Manufacture for multilayer circuit board - Google Patents
Manufacture for multilayer circuit boardInfo
- Publication number
- JPS63280496A JPS63280496A JP11351787A JP11351787A JPS63280496A JP S63280496 A JPS63280496 A JP S63280496A JP 11351787 A JP11351787 A JP 11351787A JP 11351787 A JP11351787 A JP 11351787A JP S63280496 A JPS63280496 A JP S63280496A
- Authority
- JP
- Japan
- Prior art keywords
- metal conductor
- layer
- forming
- mask member
- foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000004020 conductor Substances 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000011888 foil Substances 0.000 claims abstract description 30
- 238000009713 electroplating Methods 0.000 claims abstract description 5
- 238000007772 electroless plating Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 13
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005553 drilling Methods 0.000 claims description 2
- 239000011148 porous material Substances 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 15
- 238000007747 plating Methods 0.000 abstract description 10
- 239000010949 copper Substances 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 6
- 239000003054 catalyst Substances 0.000 abstract description 2
- 239000011889 copper foil Substances 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 241001147149 Lucina Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 229910000366 copper(II) sulfate Inorganic materials 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920002457 flexible plastic Polymers 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多層回路板の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a multilayer circuit board.
従来の多層回路板の製造方法では、スルーホール内に金
属メッキ層を形成する際に、基板の表面に形成された導
体層を含めた捲出表面全体にメッキ処理を施すため導体
層の部分は必要以上に厚くなる。そこで、導体層に所定
の回路パターンを形成すべくエツチング処理を施すとエ
ツチング時間が長くなり、所謂サイドエッチが大きくた
る。In the conventional manufacturing method of multilayer circuit boards, when forming a metal plating layer in the through hole, the entire exposed surface including the conductor layer formed on the surface of the board is plated, so the conductor layer part is plated. It becomes thicker than necessary. Therefore, when etching is performed to form a predetermined circuit pattern on the conductor layer, the etching time becomes long and so-called side etching becomes large.
かかる問題を解消するため、微細な回路を形成する場合
、9μm、12μm等の厚さの銅箔を使用する技術があ
るが、材料コストが非常に高くなると共に、このような
薄肉の銅箔の取扱い作業は困難である。このため薄肉の
銅箔を扱う特殊な設備も必要となり、製造コストが高く
なる問題があった。To solve this problem, there is a technique to use copper foil with a thickness of 9 μm, 12 μm, etc. when forming fine circuits, but the material cost is extremely high and it is difficult to use such thin copper foil. Handling is difficult. For this reason, special equipment for handling thin copper foil is also required, which poses a problem of increasing manufacturing costs.
一方、微細な回路の中でもパワー回路等を構成する部分
のように大きな電流容量が必要とされるところでは1回
路の肉厚を大きくしなければならない、tた。高い放熱
性が要求される回路の部分でもその肉厚を大きくする必
要がある。このため。On the other hand, even among minute circuits, where a large current capacity is required, such as in parts constituting power circuits, the thickness of one circuit must be increased. It is also necessary to increase the wall thickness in parts of the circuit that require high heat dissipation. For this reason.
多層回路板の製造方法では、厚肉及び薄肉の導体層から
なる微細な回路を容易かつ高精度・高密度に形成するこ
とが切望されていた。In the manufacturing method of multilayer circuit boards, it has been desired to easily form fine circuits made of thick and thin conductor layers with high precision and high density.
本発明は、かかる点に鑑みてなされたものであり、厚内
及び薄肉の導体層を容易に形成しサイドエツチングを最
少限に抑えると共に、所定の微細な回路を高精度・高密
度に形成することができる多層回路板の製造方法を提供
するものでおる。The present invention has been made in view of these points, and is capable of easily forming thick and thin conductor layers, minimizing side etching, and forming predetermined fine circuits with high precision and high density. The present invention provides a method for manufacturing a multilayer circuit board.
本発明は、絶縁性樹脂体の両面に金属導体箔を貼着して
得た両面金属導体箔張板に所望の孔あけ加工を施す工程
と、前記孔あけ加工を施した両面金属導体箔張板の孔内
を含む全露出表面上に無電解メッキ層を形成した後、少
なくとも孔内を除く露出表面上に所望パターンのマスク
部材を形成するか、もしくは少なくとも孔内を除く露出
表面上に所望パターンのマスク部材を形成した後、孔内
を含む全露出表面上に無電解メッキ層を形成する工程と
、前記無電解メッキ層の露出表面上に電気メッキ層を形
成する工程と、前記マスク部材を除去する工程と、前記
マスク部材除去面及び前記宛気メッキ層形成面の所望部
分に回路を形成する工程とを含むことを特徴とする多層
回路板の製造方法である。The present invention includes a process of forming desired holes in a double-sided metal conductor foil clad plate obtained by pasting metal conductor foil on both sides of an insulating resin body, and a process of forming desired holes in a double-sided metal conductor foil clad plate obtained by pasting metal conductor foil on both sides of an insulating resin body. After forming an electroless plating layer on the entire exposed surface of the plate including the inside of the hole, a mask member having a desired pattern is formed on the exposed surface excluding at least the inside of the hole, or a mask member with a desired pattern is formed on the exposed surface excluding at least the inside of the hole. after forming a patterned mask member, forming an electroless plating layer on the entire exposed surface including inside the holes; forming an electroplating layer on the exposed surface of the electroless plating layer; and forming an electroplated layer on the exposed surface of the electroless plating layer; and forming a circuit in a desired portion of the mask member removal surface and the air plating layer forming surface.
本発明における絶縁性樹脂体としては、エポキシ含浸ガ
ラスクロス積層体、ポリイミド含浸ガラスクロス積層体
等のリジット体、または厚さ25〜150μmのポリイ
ミド、ポリエステル、エポキシ含浸ガラスクロス等のフ
レキシブルプラスチック箔体が用いられる。また、金属
箔としては、銅箔が導電性1機械的強度、化学的性質、
経済性等の面から最適である。In the present invention, the insulating resin body may be a rigid body such as an epoxy-impregnated glass cloth laminate or a polyimide-impregnated glass cloth laminate, or a flexible plastic foil body such as polyimide, polyester, or epoxy-impregnated glass cloth having a thickness of 25 to 150 μm. used. In addition, as a metal foil, copper foil has electrical conductivity, mechanical strength, chemical properties,
It is optimal in terms of economic efficiency, etc.
以下1本発明方法を図面を参照して説明する。Hereinafter, one method of the present invention will be explained with reference to the drawings.
第1図に示す如く、絶縁性樹脂体1を用意し、その両面
に銅箔等からなる金属導体箔2*、2bを貼着して両面
金属導体箔張板3を作る。ここで。As shown in FIG. 1, an insulating resin body 1 is prepared, and metal conductor foils 2* and 2b made of copper foil or the like are adhered to both sides of the body to form a double-sided metal conductor foil-clad board 3. here.
金属導体箔21に、2bの厚さとしては1例えば35μ
m、18μmのものを使用する。The thickness of the metal conductor foil 21 is 1, for example, 35μ.
m, 18 μm is used.
また、金属導体箔2m 、2bの貼着は1例えば接着剤
を介在させて行うか、或いは、直接熱圧着させて行う。Further, the metal conductor foils 2m and 2b are attached by using, for example, an adhesive, or by direct thermocompression bonding.
次に、第2図に示す如く、両面金属導体箔張板30所定
領域にドリリングやパンチングによシ孔あけ加工を施し
、スルーホール4を形成する。Next, as shown in FIG. 2, a predetermined area of the double-sided metal conductor foil clad plate 30 is drilled or punched to form a through hole 4.
次に、第3図に示す如く、孔あけ後の両面金属導体箔張
板3の露出表面をPd触媒で活性化してから銅メッキを
施し、スルーホール4内を含む金属導体箔la、lbの
表面に無電解メッキ層5を形成する。無電解メッキ層5
の厚さ株、5μm以下の薄肉のものにするのが好ましい
。Next, as shown in FIG. 3, the exposed surface of the double-sided metal conductor foil clad plate 3 after drilling is activated with a Pd catalyst, and then copper plating is applied, and the metal conductor foil la, lb including the inside of the through hole 4 is coated with copper. An electroless plating layer 5 is formed on the surface. Electroless plating layer 5
It is preferable to use a thin material with a thickness of 5 μm or less.
次に、第4図に示す如く1表裏面の無電解メッキ層5の
所定領域にメッキレシストからなるマスク部材6を形成
する。ここで、第3図に示す無電解メッキ層5及び第4
図に示すマスク部材6の形成手順は1図示したものとは
逆に先ずスルーホール4を除く露出表面上に例えばホト
Vシストからなるマスク部材6を形成し1次いで、スル
ーホール4を含む全露出表面上に無電解メッキ層5を形
成するものとしても良い。Next, as shown in FIG. 4, mask members 6 made of plating resist are formed in predetermined areas of the electroless plating layer 5 on the front and back surfaces. Here, the electroless plating layer 5 and the fourth layer shown in FIG.
The procedure for forming the mask member 6 shown in the figure is 1. Contrary to what is shown in the figure, first, a mask member 6 made of, for example, photo-V cyst is formed on the exposed surface excluding the through holes 4, and then the entire area including the through holes 4 is exposed. An electroless plating layer 5 may be formed on the surface.
次に、第5図に示す如く、マスク部材6をマスクにして
スルーホール4内を含む無電解メッキ層5の露出表面上
に例えば銅の電気メッキ層1を形成する。Next, as shown in FIG. 5, an electroplated layer 1 of, for example, copper is formed on the exposed surface of the electroless plating layer 5 including the inside of the through hole 4 using the mask member 6 as a mask.
次に、第6図に示す如<、1気メッキ層1.無電解メッ
キ層5及び金属導体箔2aからなる厚肉の導体部13に
大%流用の回路及び放熱部を形成する。Next, as shown in FIG. A circuit and a heat dissipation section for large percentage use are formed in the thick conductor section 13 made of the electroless plating layer 5 and the metal conductor foil 2a.
次に、第7図に示す如く、マスク部材6t−除去した後
、厚肉の導体部13の方をエツチングされないように保
護した状態で、無電解メッキ層5及び金属導体箔2aか
らなる薄肉の導体部11の所定部分に薄肉回路8を形成
する。ここで、厚肉の導体部13の回路形成及び薄肉の
導体部11の薄肉回路8の形成線、先に形成した回路の
方を保護した状態で図示のものと逆の手順としても良い
。Next, as shown in FIG. 7, after removing the mask member 6t, the thin conductor portion 13 made of the electroless plated layer 5 and the metal conductor foil 2a is etched while the thick conductor portion 13 is protected from being etched. A thin circuit 8 is formed in a predetermined portion of the conductor portion 11. Here, the process for forming the circuit on the thick conductor part 13 and forming the thin circuit 8 on the thin conductor part 11 may be performed in a state where the previously formed circuit is protected and the procedure is reversed to that shown in the drawings.
このようにして得た両面2層回路@15は、これを単独
で多層回路板としても良く、また、3層回路以上の多層
回路板とする場合には、前記両面2層回路板の所望部を
多層回路板の一部又は全部としてプリプレグを介して積
層して多層回路板とする。The thus obtained double-sided two-layer circuit @15 may be used alone as a multilayer circuit board, or in the case of forming a multilayer circuit board with three or more layer circuits, a desired portion of the double-sided two-layer circuit board are laminated via prepreg as part or all of a multilayer circuit board to form a multilayer circuit board.
特に高い放熱性を必要とする場合には、第8図に示す如
く、両面二層回路板15の片面側に絶縁層9を介して金
属基板10を貼着して金属ベース多層回路板16として
も良い、金属基板10としては1例えばCu板、Aノ板
、或いはFe板等からなるものやこれらに絶縁処理を施
したものを使用する。また、最終的に得た多層回路板の
最上層の導体表面には回路を未形成としておき、これを
金属基板10に貼着した後に所定の回路を形成して金属
ベース多層回路板16としても良い。When particularly high heat dissipation is required, as shown in FIG. The metal substrate 10 may be made of, for example, a Cu plate, an A plate, or an Fe plate, or may be made of one of these plates subjected to insulation treatment. Further, no circuit is formed on the conductor surface of the top layer of the finally obtained multilayer circuit board, and after this is pasted on the metal substrate 10, a predetermined circuit is formed to form the metal base multilayer circuit board 16. good.
本発明にかかる多層回路板の製造方法によれば、金属導
体箔の捲出表面上に所定パターンのマスク部材を形成し
て、このマスク部材をマスクにして金属箔導体の表面に
電気メッキ層を形成する。According to the method for manufacturing a multilayer circuit board according to the present invention, a mask member having a predetermined pattern is formed on the exposed surface of a metal conductor foil, and the electroplated layer is applied to the surface of the metal foil conductor using this mask member as a mask. Form.
このため基板上に金属導体箔からなる薄肉の導体部と金
属導体箔及び電気メッキ層からなる厚肉の導体部を選択
的にかつ容易に形成することができる。その結果、回路
形成の際のサイドエツチングを最少限に抑えて、薄肉の
導体部に薄肉の回路を容易に形成できる。パワー回路や
ヒートシンクのような厚肉の回路は、厚肉の導体部に容
易に形成することができる。Therefore, a thin conductor portion made of metal conductor foil and a thick conductor portion made of metal conductor foil and an electroplated layer can be selectively and easily formed on the substrate. As a result, side etching during circuit formation can be minimized, and a thin circuit can be easily formed on a thin conductor portion. Thick circuits such as power circuits and heat sinks can be easily formed on thick conductor parts.
以下、本発明の実施例について説明する。 Examples of the present invention will be described below.
ポリイミドからなる厚さ25μmの箔体の両面に、厚さ
35μmの電解Cu箔を貼着して両面鋼箔張板を得た。Electrolytic Cu foil with a thickness of 35 μm was adhered to both sides of a foil body made of polyimide with a thickness of 25 μm to obtain a double-sided steel foil-clad plate.
この両面鋼箔張板にパッチングで孔径0.5〜2茄φの
各種スルーホールを穿設した。次に、これを脱脂、酸洗
してから1%のPdCノ、d()水溶液に浸漬し、続い
て。Various through-holes with diameters of 0.5 to 2 degrees were made in this double-sided steel foil-clad plate by patching. Next, this was degreased and pickled, and then immersed in a 1% PdC() aqueous solution.
これをエンプレー)Cu406(メルテックス社、商品
名)の化学メッキ浴に35℃の温度で、20分間浸漬し
て、厚さ0.5μmの無電解銅メッキ層をスルーホール
を含む表面全面に形成した。次に、無電解銅メッキ処理
後の両面銅箔張板の一部にマスキングテープを貼着した
後h Cu 804120 g /’ tH,So、3
0g/ノ、トップルチナ(奥野製薬社、商品名)5pp
mのCuSO4浴(30°0,5A/dm” )に浸
漬し、厚さ18μmのCu層を全面に電気メッキにょす
形成した。This was immersed in a chemical plating bath of Cu406 (Meltex Co., Ltd., trade name) for 20 minutes at a temperature of 35°C to form an electroless copper plating layer with a thickness of 0.5 μm on the entire surface including the through holes. did. Next, after applying masking tape to a part of the double-sided copper foil clad plate after electroless copper plating,
0g/no, Top Lucina (Okuno Pharmaceutical Co., Ltd., trade name) 5pp
The sample was immersed in a CuSO4 bath (30°0.5 A/dm") of 18 μm in thickness, and a Cu layer with a thickness of 18 μm was electroplated on the entire surface.
次に、マスキングテープをそのままにしてこの電気メッ
キ層形成済の両面鋼箔張板の両面電気メッキ面に感光性
ドライフィルム(DFR、旭化成社。Next, leaving the masking tape as it is, apply a photosensitive dry film (DFR, Asahi Kasei Co., Ltd.) to the electroplated surfaces of both sides of the double-sided steel foil clad plate on which the electroplating layer has been formed.
商品名)を圧着して露光、現像の後、 FeCJ、液で
エツチングしてCu箔層及びメッキ層からなる厚肉の導
体部に厚肉導体回路パターンを形成した。次いで、残存
したドライフィルムを剥離し、更に前記マスキングテー
プも剥離した。(trade name) was crimped, exposed and developed, and then etched with a FeCJ solution to form a thick conductor circuit pattern on the thick conductor portion consisting of the Cu foil layer and the plating layer. Next, the remaining dry film was peeled off, and the masking tape was also peeled off.
次に、マスキングテープ除去面のCu箔と無電解メッキ
層からなる薄肉の導体部に厚肉導体回路の場合と同様に
して厚肉導体回路パターンを形成した。然る後、パッド
部を除いて半田レジスト(HR16、太陽インキ社、商
品名)及び7ラツクスを塗布して多層回路板を得た。Next, a thick conductor circuit pattern was formed on the thin conductor portion made of the Cu foil and the electroless plating layer on the surface from which the masking tape was removed in the same manner as in the case of the thick conductor circuit. Thereafter, solder resist (HR16, Taiyo Ink Co., Ltd., trade name) and 7lux were applied except for the pad portions to obtain a multilayer circuit board.
このようにして得た実施例の多層回路板では。In the multilayer circuit board of the example thus obtained.
予めマスキングをして形成した薄肉の導体部で回路パタ
ーンを、 Q、1Ote の幅で良好な再現性の下
で形成することができた。これに対してマスキング工程
がない従来の方法によるものでは、 0.25〜0.
30語幅の回路パターンを形成するのが限度であった。It was possible to form a circuit pattern with a width of Q, 1 Ote with good reproducibility using a thin conductor portion formed by masking in advance. On the other hand, in the conventional method without a masking step, the difference is 0.25 to 0.
The limit was to form a circuit pattern with a width of 30 words.
また、実施例の多層回路板では、初期に断線事故は見ら
れず、また、一部の回路を切断検鏡したところ割れは全
く認められなかった。更に。Further, in the multilayer circuit board of the example, no disconnection accident was observed in the initial stage, and when some of the circuits were cut and examined under a microscope, no cracks were observed at all. Furthermore.
250℃のオイルと冷水を用いた交互浸漬を50回繰返
したが、電気抵抗の変化は初期値の5チ以内であった。Alternate immersion using 250°C oil and cold water was repeated 50 times, but the change in electrical resistance was within 5 degrees of the initial value.
以上説明した如く、本発明に係る多層回路板の製造方法
によれば、厚肉及び薄肉の導体層を容易に形成し2回路
形成の際のサイドエツチングを最小限に抑えると共に、
所定の微細な回路を高精度・高密度に形成することがで
きる。As explained above, according to the method for manufacturing a multilayer circuit board according to the present invention, thick and thin conductor layers can be easily formed, side etching when forming two circuits can be minimized, and
Predetermined fine circuits can be formed with high precision and high density.
第1図乃至第7図は1本発明方法を工程順に示す説明図
である。第8図は1本発明方法を利用して得られる金属
ベース多層回路板の断面図である。
1・・・プラスチック箔体、2*、2b・・・金属導体
箔、3・・・両面金属導体箔張衣、4・・・スルーホー
ル。
5・・・無電解メッキ層、6・・・マスク部材、1・・
・電気メッキ層、8・・・薄肉回路、9・・・絶縁層、
10・・・金属基叡、1ノ・・・薄肉の導体部、13・
・・厚肉の導体部、15・・・両面二層回路板、16・
・・金属ペース多層回路板。
出願人代理人 弁理士 鈴 江 武 彦第1図
第2図
第3図
第5図FIGS. 1 to 7 are explanatory diagrams showing the method of the present invention in the order of steps. FIG. 8 is a cross-sectional view of a metal-based multilayer circuit board obtained using the method of the present invention. 1...Plastic foil body, 2*, 2b...Metal conductor foil, 3...Double-sided metal conductor foil coating, 4...Through hole. 5... Electroless plating layer, 6... Mask member, 1...
・Electroplated layer, 8... Thin circuit, 9... Insulating layer,
10... Metal substrate, 1... Thin conductor part, 13.
・Thick conductor part, 15 ・Double-sided double-layer circuit board, 16・
...Metal paste multilayer circuit board. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 5
Claims (1)
属導体箔張板に所望の孔あけ加工を施す工程と、前記孔
あけ加工を施した両面金属導体箔張板の孔内を含む全露
出表面上に無電解メッキ層を形成した後、少なくとも孔
内を除く露出表面上に所望パターンのマスク部材を形成
するか、もしくは少なくとも孔内を除く拠出表面上に所
望パターンのマスク部材を形成した後、孔内を含む全露
出表面上に無電解メッキ層を形成する工程と、前記無電
解メッキ層の拠出表面上に電気メッキ層を形成する工程
と、前記マスク部材を除去する工程と、前記マスク部材
除去面及び前記電気メッキ層形成面の所望部分に回路を
形成する工程とを含むことを特徴とする多層回路板の製
造方法。A step of drilling a desired hole in a double-sided metal conductor foil-clad plate obtained by pasting metal conductor foil on both sides of an insulating resin body, and forming holes in the double-sided metal conductor foil-clad plate that has been subjected to the perforation process. After forming an electroless plating layer on the entire exposed surface including the pores, a mask member having a desired pattern is formed on the exposed surface excluding at least the inside of the hole, or a mask member having a desired pattern on the exposed surface excluding at least the inside of the hole. forming an electroless plating layer on all exposed surfaces including inside the holes; forming an electroplating layer on the surface of the electroless plating layer; and removing the mask member. and forming a circuit on a desired portion of the mask member removal surface and the electroplating layer formation surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11351787A JPS63280496A (en) | 1987-05-12 | 1987-05-12 | Manufacture for multilayer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11351787A JPS63280496A (en) | 1987-05-12 | 1987-05-12 | Manufacture for multilayer circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63280496A true JPS63280496A (en) | 1988-11-17 |
Family
ID=14614348
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11351787A Pending JPS63280496A (en) | 1987-05-12 | 1987-05-12 | Manufacture for multilayer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63280496A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02185099A (en) * | 1989-01-12 | 1990-07-19 | Sony Corp | Manufacture of printed wiring board |
JPH1075038A (en) * | 1996-06-28 | 1998-03-17 | Ngk Spark Plug Co Ltd | Wiring board and its manufacture method |
US7726016B2 (en) | 2003-05-07 | 2010-06-01 | International Business Machines Corporation | Manufacturing method of printed circuit board |
US7868464B2 (en) | 2004-09-16 | 2011-01-11 | Tdk Corporation | Multilayer substrate and manufacturing method thereof |
JP2014220304A (en) * | 2013-05-06 | 2014-11-20 | 株式会社デンソー | Multilayer board and electronic device using the same |
-
1987
- 1987-05-12 JP JP11351787A patent/JPS63280496A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02185099A (en) * | 1989-01-12 | 1990-07-19 | Sony Corp | Manufacture of printed wiring board |
JPH1075038A (en) * | 1996-06-28 | 1998-03-17 | Ngk Spark Plug Co Ltd | Wiring board and its manufacture method |
US7726016B2 (en) | 2003-05-07 | 2010-06-01 | International Business Machines Corporation | Manufacturing method of printed circuit board |
US7868464B2 (en) | 2004-09-16 | 2011-01-11 | Tdk Corporation | Multilayer substrate and manufacturing method thereof |
JP2014220304A (en) * | 2013-05-06 | 2014-11-20 | 株式会社デンソー | Multilayer board and electronic device using the same |
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