JPS63266919A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To attain efficient timing adjustment in the stage of checking products and to reduce the product development period by providing a MOSFET whose conductance is changed according to a control voltage supplied externally. CONSTITUTION:When an internal timing signal r1 is brought into a low level in a semiconductor integrated circuit device provided with a delay circuit DL2, a MOSFETQ1 is turned on and a MOSPETQ5 is turned off. In this case, a capacitor C1 is charged to a high level such as a power voltage Vcc via the FETQ1. Thus, an output signal of an inverter circuit N2, that is, an internal timing signal r2 goes to a low level. On the other hand, when the signal r1 is brought into a high level, the FETQ1 is turned off and the FETQ5 is turned on. Thus, the electric charge of the capacitor C1 is discharged via the FETs 5, 6, the potential of the capacitor C1 is lowered less than the logic threshold level of the circuit N2, then the circuit N2 is inverted and the signal r2 goes to a high level.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, for example, a dynamic RAM (random access memory) equipped with a timing control circuit (timing generation circuit) including a delay circuit. ) and other effective techniques.

[Conventional technology]

There is a dynamic RAM that includes a timing control circuit (timing generation circuit). This timing control circuit forms various timing signals and internal control signals for controlling the operation of each circuit block of the dynamic RAM based on a plurality of control signals supplied from the outside.

Regarding dynamic RAM equipped with a timing control circuit, for example, see pages 251 to 259 of "Hitachi IC Memory Data Punk J," published by Hitachi, September 1983.
It is written on the page.

[Problem that the invention seeks to solve]

The timing control circuit of the dynamic RAM as described above forms the timing signal and internal control signal by delaying or combining a plurality of control signals supplied from the outside. For this reason, the timing control circuit is provided with a plurality of delay circuits made of MOSFETs and capacitors formed by the same manufacturing process as the main circuit of the dynamic RAM. The timing conditions necessary for forming the above-mentioned timing signals and internal control signals are satisfied by setting the signal delay times by these delay circuits to be predetermined values.

However, the MOSFETs and capacitors that constitute these delay circuits exhibit process variations in their electrical characteristics. Therefore, it is difficult to set all the delay times of a large number of products to desired delay times. Furthermore, the delay time of a completed product is adjusted by, for example, switching the number of stages through which the delay circuit passes, using a laser fuse, or by selectively adding or deleting circuit elements that make up the delay circuit. , it is not possible to continuously control the delay time, which means that, for example, it is necessary to change the mask several times during the product prototyping stage, which results in a relatively long product development time, and it is difficult to accurately measure the operating margin. This is a cause that hinders the optimal design of equipment.

An object of the present invention is to provide a dynamic RAM that can continuously control delay time according to control signals supplied from the outside.
The object of the present invention is to provide semiconductor integrated circuit devices such as the above. Another object of the present invention is to shorten the product development period of a semiconductor integrated circuit device including a delay circuit and to improve the efficiency of timing adjustment at the product inspection stage.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a MOSF whose conductance is changed according to a predetermined control voltage supplied from the outside to the delay circuit.
By providing a capacitor that is charged or discharged via the ET and the MO3FET, the delay time of the delay circuit can be changed continuously in accordance with the control voltage.

[For production]

According to the above-mentioned means, by continuously changing the delay time, it is possible to accurately measure the operating margin of a semiconductor integrated circuit device including a delay circuit, and to easily understand the I&T timing conditions. In addition to shortening the process, timing adjustment at the product inspection stage can be made more efficient.

〔Example〕

Figure 5 shows a dynamic RA to which this invention is applied.
A block diagram of one embodiment of M is shown. Although not particularly limited, each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.

The dynamic RAM of this embodiment is externally supplied with a row address strobe signal RAS, a column address strobe signal εAS, and a write enable signal WE as control signals. The dynamic RAM is also provided with a timing control circuit TC that forms various timing signals and internal control signals based on these control signals.

The timing control circuit TC includes, but is not particularly limited to, C
A plurality of delay circuits each having a basic configuration of a MOS inverter circuit are provided. In this embodiment, as will be described later, among these delay circuits, the delay time of the delay circuit DL2, which influences the most important timing condition of this dynamic RAM, is adjusted according to the control voltage VC supplied via the external terminal VC. It allows for continuous control. As a result, the product development period for the dynamic RAM can be shortened, and the timing control circuit at the product inspection stage can be made more efficient.

In Figure g45, the memory array M-ARY has a two-intersection (folded bit line) system, although it is not particularly limited, with n+1 sets of complementary data lines arranged in the horizontal direction in the figure, and n+1 sets of complementary data lines arranged in the vertical direction in the figure. It is composed of m+1 word lines arranged and (m+1)×(n+1) dynamic mesoricells arranged in a grid at the intersections of these complementary data lines and word lines.

Each complementary data line constituting the memory array M-ARY is
on the one hand, coupled to a precharge circuit PC;
Furthermore, it is coupled to a corresponding unit circuit of sense amplifier SA. The precharge circuit PC is constituted by fi+1 shorting switches MO5FETs provided between the non-inverted signal line and the inverted signal line of each complementary data line. The gates of these switches MO5FET are commonly connected, and a timing signal φp is supplied from a timing control circuit TC, which will be described later.
c is supplied. This timing signal φpc is set to a high level when the dynamic RAM is in a non-selected state, and is set to a low level when the dynamic RAM is selected. While the dynamic RAM is in the non-selected state, the switch MOS FET on the cover of the precharge circuit PC is simultaneously turned on, shorting both signal lines of the complementary data line and reducing the voltage to about 1/2 of the power supply voltage Vcc. In other words, it is set to a half precharge level. As a result, when the dynamic RAM is put into the selected state, the levels of the non-inverted signal line and the inverted signal line of each complementary data are changed from this half precharge level toward the high level or low level, so that the read operation is performed. It is possible to increase the speed.

Sense amplifier SA is composed of fi+1 unit circuits provided corresponding to each complementary data line. Each unit circuit of the sense amplifier SA has a basic configuration of a flip-flop in which two sets of CMOS inverter circuits are cross-connected, and its input/output nodes are connected to the non-inverted signal line and the inverted signal line of the corresponding complementary data line. Each is combined. The unit circuits of these sense amplifiers SA receive a timing signal φpa supplied from a timing control circuit TC.
1 and φpa2 are set to a high level with a slight time difference, the signals are selectively activated, and a two-stage amplification operation is performed. iiN The corresponding complementary data from the memory cells coupled to the selected word line is The minute reading signal outputted to the line is amplified by the corresponding unit circuit of the sense amplifier SA without sudden level fluctuations, and is converted into a binary signal of high level or low level.

Each complementary data line constituting the memory array M-ARY is
On the other hand, it is coupled to the corresponding switch MO3FET of column switch C5W.

The column switch C8W is composed of n+1 pairs of switches MO5FET provided corresponding to each complementary data line. One of these MO5FET switches is coupled to the corresponding complementary data line, and the other is commonly connected to the non-inverted signal line CD or the inverted signal line τ of the complementary common data line. In addition, switch MO3 of each sentence
The gates of the FETs are connected in common, and the corresponding data line selection signal YO is sent from the column address decoder CDCR.
~Yn are supplied, respectively. This allows Columns
The f edge C5W selectively connects a set of complementary data lines specified by the column address signal 4, that is, the data line selection signal YO-Yn, with the common complementary data line CD.

Column address decoder CDCR receives complementary internal address signal a supplied from column address buffer CADB.
yO~ayi (Here, for example, external address signal A
YO, the in-phase internal address signal aye, and the opposite-phase internal address signal 771 are combined to form a complementary internal address signal ayQ.
(hereinafter the same) is decoded, and in synchronization with the timing signal φy supplied from the timing control circuit TC, the data line selection signals YO to Yn are formed and supplied to the corresponding switch MO3FET of the column switch C5W. do.

Column address buffer CADH connects external terminals AO to A
Y address signals AYO to -AYI supplied via 1
is captured and held, and the complementary internal address signal ay is generated based on these Y address signals AYO to AYi.
Form o~ayi.

These complementary internal address signals ayQ to ayi are supplied to the column address decoder CDCH. The column address buffer CADH includes a timing control circuit T.
A timing signal φac is supplied from C. This timing signal φac is normally set to a low level, and is temporarily set to a high level by changing the column address strobe signal τ■ from a high level to a low level.

In other words, the dynamic RAM of this embodiment employs an address multiplex method, and X address signals AXO to AXi are supplied to external terminals AO to Ai in synchronization with the falling edge of the row address strobe signal rT. Y address signals AYO to AYi are supplied in synchronization with the falling edge of column address strobe signal m. By temporarily setting the timing signal φac to a high level, the column address buffer CADB receives the Y address signal A supplied via the external terminals AO to Ai.
YO~A Y i 4-Intake and retention.

On the other hand, each word line constituting the memory array M-ARY is coupled to a secondary row address decoder RDCR2, and one of them is selected and designated.

Although not particularly limited, the dynamic RA of this embodiment
The M row system selection circuit has a two-stage configuration, including a primary row address decoder RDCRl that decodes the complementary internal address signals axQ and 1x1 of the lower 2 bits, and a secondary row address decoder that decodes the complementary internal address signals ax2 to axi. RDCR2 is provided.

Although not particularly limited, the primary row address decoder RDCRl receives complementary internal address signals axQ and ixl of the lower two bits supplied from the row address buffer RADB.
is decoded to form word line selection timing signals φxO to φx3 in accordance with the timing signal φX supplied from the timing control gBR path TC. These word line selection timing signals φxO to φx3 are supplied to the secondary row address data 2-da RDCR2. The secondary row address decoder RDCR2 is a row address buffer RADB.
The complementary internal address signals x2 to axi supplied from the memory terminals are decoded. Furthermore, a secondary row address decoder RD
By combining this decoding result and the word line selection timing signals φxQ to φx3 output from the primary row address decoder RDCRI, CR2
One word line specified by the row address signal is alternatively set to a high level selected state.

As described above, by configuring the row selection circuit in two stages, it is possible to make the arrangement spacing of the secondary row address decoder RDCR2 and the arrangement spacing of the word lines of the memory array M-ARY approximately the same on the semiconductor substrate. This allows for more efficient board layout.

Row address buffer RADB receives a row address signal transmitted from address multiplexer AMX and forms complementary internal address signals xO to Xi. These complementary internal address signals xO to axi are supplied to the primary row address decoder RDCR1 and the secondary row address decoder RDCR2. As mentioned above, the X address signals AXO to AXi are applied to the external terminals AO to AX in synchronization with the falling edge of the row address strobe signal RAS.
At. Therefore, row address buffer R
ADB is supplied with a timing signal φar generated by detecting the fall of the row address strobe signal RAS from the timing control circuit TC. Row address buffer RADB receives this timing signal φ
By temporarily setting ar to a high level, X address signals AXO to AXL supplied from external terminals AO to AI via address multiplexer AMX are taken in.

In the automatic refresher mode in which the timing signal φref supplied from the timing control circuit TC is at a high level, the address multiplexer AMX selects the refresh address signals rXO to rxlJtc supplied from the refresher address counter REFC, and selects them as row address signals. It is transmitted to the row address buffer RADB. In addition, in normal memory access when the timing signal φref is at a low level, external terminals AO to A
X address signals AXO to AXi supplied via I are selected and transmitted to row address buffer RADB as a row address signal.

The refresher address counter REFC is incremented in accordance with the timing signal -C supplied from the timing control circuit TC in the automatic refresher mode of the dynamic RAM, and receives the refresh address signal rxQ~ for sequentially specifying the word line to be refreshed. rxl
form.

These friend share address signals rxo to rxi are
It is supplied as one input signal of the address multiplexer AMX.

By the way, the complementary common data line CD-' to which one set of complementary data lines is selectively connected by the column switch C8W
The input terminal of main amplifier MA is coupled to e'm, and the output terminal of data input buffer DIB is coupled to e'm. The output terminal of main amplifier MA is further coupled to the input terminal of data output buffer DOB.

The output terminal of B is further coupled to a data output terminal DO. The input terminal of data input buffer DIB is further coupled to data input terminal DI.

Main amplifier MA is selectively brought into operation according to timing signal φma supplied from timing control circuit TC. In this operating state, the main amplifier MA further amplifies the binary read signal output from the selected memory cell of the memory array M-ARY via the corresponding complementary data line and the complementary common data line CD/τ. ,
The data is transmitted to the data output buffer DOB.

The data output buffer DOB is selectively activated in accordance with the timing signal φr supplied from the timing control circuit TC when the dynamic RAM is placed in the read operation mode. In its operating state, data output buffer DOB sends out a memory cell read signal transmitted from main amplifier MA to an external device via data output terminal Do. When the timing signal φr is set to a low level, the output of the data output buffer DOB is set to a high impedance state.

The data input buffer DIB is selectively activated in accordance with the timing signal φW supplied from the timing control circuit TC when the dynamic RAM is placed in the write operation mode. In its operating state, the data input buffer DIB receives data from the data input terminal D from an external device.
The write data supplied via in is made into a complementary write signal and is supplied to the complementary common data line CD-CD. When the timing signal φW is set to a low level, the output of the data input buffer DIB is set to a high impedance state.

The timing control circuit TC forms the various timing signals described above based on the row address strobe signal πAS, the column address strobe signal σx1, and the write enable signal W1. As will be described later, the timing control circuit TC includes a plurality of delay circuits each having a basic configuration of a CMOS inverter circuit, and is not particularly limited. Among these delay circuits, the delay circuit DL2 included in the RAS-based timing generation section is The delay time is continuously controlled according to a control voltage VC supplied via an external terminal VC.
The specific circuit configurations and operations of the timing control circuit TC and delay circuit DL2 will be described in detail later.

FIG. 4 shows a circuit block diagram of an embodiment of the RAi system timing generating section of the timing control circuit TC of the dynamic RAM shown in FIG.

This positive X-ray timing generation section forms internal timing signals rl, r2, and r3 based on the row address strobe signal τ1 supplied as a control signal from the outside.These internal timing signals are used for timing control. For example, the timing signals φpc, φart φX, φpal are supplied to a combinational circuit (not shown) of the circuit TC.
, φpa2, etc. are formed. Timing control circuit TC
In addition to this πn-based timing generator, a timing signal φaC is generated based on the column address strobe signal below τ.
A system timing generation unit is provided which generates a plurality of internal timing signals for forming signals such as Cτ and φy. The write enable signal W1 supplied from the outside is the R
It is used as a mode signal in the AS-based timing generation section and the σx1-based timing generation section, and the various timing signals mentioned above are selectively formed according to the operation mode of the dynamic RAM.

In FIG. 4, a row address strobe signal RAS supplied via an external terminal RAS is supplied to a delay circuit DLI made up of CMOS inverter circuits N5 to N6 via an input protection circuit (not shown), although this is not particularly limited. The delay circuit DLI has a predetermined delay characteristic determined by the signal transmission delay time of the odd number of CMOS inverter circuits N5 to N6.The row address strobe signal positive τI is delayed and inverted by the delay circuit DLI, and then output as an internal timing signal. rl is supplied to the input terminal of the delay circuit DL2. Moreover, this internal timing signal r1 is
The signal is supplied to a combinational circuit (not shown) of the timing control circuit TC, and the above-mentioned timing signal φar and the like are formed.

' The delay circuit DL2 is connected to this dynamic RAM.
An internal timing signal r2 is generated which determines a relatively important tying condition. Therefore, as described later, the delay circuit DL2 has a delay time equal to that of the external terminal V.
The delay time is continuously changed in accordance with the control voltage VC supplied through C, and any delay time can be set within a predetermined range. A pull-amp resistor R1 or a pull-down resistor R3 is selectively provided between the external terminal VC and the power supply voltage Vcc of the circuit or the ground potential of the circuit, depending on the circuit configuration of the delay circuit DL2, as described later.

The output signal of the delay circuit DL2 is the internal timing signal r2.
is supplied to the input terminal of the delay circuit DL3. Further, this internal timing signal r2 is supplied to a combinational circuit (not shown) of the timing control circuit TC, and the above-mentioned timing signal φX and the like are formed.

The specific circuit configuration and operation of the delay circuit DL2 will be explained in detail later.

Although not particularly limited, the delay circuit DL3 is configured by an even number of CMOS inverter circuits N7 to N8 connected in series. The delay circuit DL3 has a predetermined delay characteristic determined by the signal transmission delay time of these inverter circuits N7 to N8.The internal timing signal r2 is further delayed by the delay circuit DL3 to form an internal timing signal r3. The internal timing signal r3 is supplied to a combinational circuit (not shown) of the timing control circuit TC, and the above-mentioned timing signals φpal, φpa2, etc. are formed.

FIG. 1 shows a circuit diagram of an embodiment of the delay circuit DL2 of the timing control circuit TC of FIG. 4. In FIG. In the following figures, the MOS FET whose channel (bank gate) part is marked with an arrow is a P-channel type, and is distinguished from the N-channel MO3FET whose channel (bank gate) part is not marked with an arrow.

In FIG. 1, the delay circuit DL2 is a P-channel MO3FETQI (second %/I
O3FF, T) and N-channel MOSFETQ5 (
A CMOS inverter circuit Nl (first CMOS inverter circuit) consisting of a CMOS inverter circuit Nl (third MOSFET), a resistor R2 and an N-channel MOSFET Q6 (
MO3FETQI and Q
The commonly connected gates of No. 5 are used as input terminals of the inverter circuit N1, and are supplied with an internal timing signal rl from the above-mentioned delay circuit DLI.

A control voltage VC is supplied to the gate of MO8FETQ6 via an external terminal VC. Further, a pull-up resistor R1 is provided between the external terminal VC, that is, the gate of the MO5FETQ6, and the power supply voltage Vcc of the circuit. When the external terminal VC is in a floating state and the control voltage VC is not supplied, the gate of MO3FETQ6 is connected to the power supply voltage Vc.
It is considered to be a high level such as c. At this time, MO5FE
The conductance of TQ6 is assumed to be the largest.

When control voltage VC is supplied to external terminal VC, MO3
The conductance of FETQ6 is changed according to this control voltage VC. In other words, the source-drain current flowing through MO3FETQ6 is controlled according to control voltage VC.

An output terminal of inverter circuit N1 is coupled to one electrode of capacitor C1. The other electrode of this capacitor C1 is coupled to the circuit ground potential. Capacitor C1 is designed to have a predetermined capacitance value depending on the desired delay time of delay circuit DL2.

One electrode of the capacitor C1 is a P-channel MO3F
ETQ2 and Nchi? Input terminals of CMOS inverter circuit N2 (second CMOS inverter circuit) consisting of 7-channel Mo5FETQ7, that is, MO5FETQ2 and Q7
are coupled to commonly connected gates. This inverter circuit N2 has a predetermined logic threshold level determined by the rise of MO3FETs Q2 and Q7.
The output signal of the inverter circuit N2 is supplied as an internal timing signal r2 to a combination circuit (not shown) of the delay circuit DL3 and timing control circuit TC.

Internal timing signal r1 supplied from delay circuit DLI
When is set to low level, MO8FETQI constituting the first CMOS inverter circuit is turned on,
O5FETQ5 is turned off. At this time, the capacitor C1 is charged to a high level such as the power supply voltage Vcc of the circuit via the MO5FET QI. therefore,
The output signal of the inverter circuit N2, that is, the internal timing signal r2 becomes low level.

On the other hand, when the internal timing signal r1 changes from low level to high level, MO5FETQIG;II: goes into the off state, and MO3FETQ5 goes into the on state. As a result, the charge accumulated in the capacitor C1 is transferred to the MO3FE
TQ5. It is discharged through resistor R2 and MO5FET Q6, and the potential of capacitor C1 decreases. Capacitor C1
When the potential of the inverter circuit N2 becomes lower than the logic threshold level of the inverter circuit N2, the inverter circuit N2 is inverted and the internal timing signal r2 becomes high level.

Here, the speed at which the potential of capacitor C1 decreases is MO
3FETQ5. It is determined by the product of the combined conductance of Q6 and resistor R2 and the capacitance value of capacitor C1, that is, the discharge time constant. As mentioned above, MO5FETQ6
The conductance of is controlled by a control voltage VC supplied via an external terminal VC. Therefore, the time from when the internal timing signal qrl changes from a low level to a high level until the internal timing signal r2 becomes a high level, that is, the delay time td with respect to the rising edge change of the delay circuit DL2, is continuously controlled by the control voltage VC. become what is done.

Next, when the internal timing signal rl is changed from high level to low level, MOS FETQl is turned on again, and MO3FETQ5 is turned off.

This causes capacitor C1 to connect to the circuit through MO3FETQI. is charged to the source voltage Vcc, and the internal timing signal r2 becomes low level. At this time, capacitor C
1 is MO3FET, which has a relatively large conductance.
Since it is rapidly charged via QI, the delay time for a falling change of delay circuit DL2 is so small that it can be almost ignored.

FIG. 2 shows a characteristic diagram of an example of the delay time td with respect to the rise change of the fill delay circuit DL2. In the figure, the horizontal axis shows the voltage value of the control voltage VC supplied via the external terminal VC, and the vertical axis shows the delay circuit D.
The delay time td for the rising edge change of L2 is shown.

In FIG. 2, when the external terminal VC is in a floating state and the control voltage VC is not supplied to the delay circuit DL2, the power supply voltage Vcc of the circuit is supplied to the gate of the MO3FETQ6 via the pull-up resistor R2. For this reason,
MO3FETQ6 is brought into an almost completely on state, and its conductance is increased. Therefore, delay circuit D
The delay time td for a high level change of L2 is its minimum direct time tdmin.

On the other hand, as control voltage VC is supplied to external terminal VC and its voltage value is gradually lowered from power supply voltage Vcc, M
The conductance of O5FETQ6 is gradually reduced. As a result, the speed at which the charges accumulated in the capacitor C1 are discharged is slowed down, and the delay time td for the high level change of the delay circuit DL2 is gradually lengthened (i.e.,
Delay time td for high level change of delay circuit DL2
is changed approximately inversely and continuously in accordance with the control voltage VC.

By continuously changing the external control voltage VC,
The delay time Ld of the delay circuit DL2 is the desired delay time tdo
The voltage value VcO of the control voltage VC is determined. Incidentally, the dynamic RAM of this embodiment is provided with a voltage generation circuit close to the external terminal VC to form a desired control voltage, although this is not particularly limited. Further, the output voltage value of this voltage generating circuit can be fixed by, for example, laser haze means. Therefore, the control voltage VC supplied to the delay circuit DL2 is set to the above voltage value Vco.
By fixing the delay time to the desired delay time tdo, the delay time of the delay circuit DL2 can be maintained at the desired delay time tdo even after the external terminal VC is set to a floating state.

As described above, the dynamic RAM of this embodiment is provided with a timing control circuit TC including a plurality of delay circuits. Among these delay circuits, this dynamic type R
Determine the most important timing conditions for AM! The delay time [d] for the high level change of delay circuit DL2 is determined by the control voltage VC supplied via the external terminal VC.
Continuously changed. Therefore, this dynamic type R
In AM, the optimum delay time of the delay circuit DL2 can be easily obtained by changing the control voltage vCt, and the circuit constants at that time can be estimated. Also,
By changing the timing conditions, dynamic type R
The operating margin of AM can be easily measured. As a result, products such as dynamic RAMs can be developed efficiently, and timing adjustment work at the product inspection stage can be made more efficient.

Embodiment 1 As shown in the above, when the present invention is applied to a dynamic RAM or the like having a timing control circuit (timing generation circuit) including a delay circuit, the following effects can be obtained. That is, (1) a MOS F whose conductance is changed according to a control voltage supplied from the outside to a predetermined delay circuit included in a timing control circuit such as a dynamic RAM;
By providing a capacitor that is charged or discharged via the ET and the MO3FET, it is possible to obtain the effect that the delay time of the delay circuit can be continuously changed in accordance with the control voltage.

(2) According to the above (11), it is possible to accurately and efficiently grasp the optimum timing conditions of the timing control circuit including the delay circuit.

(3) According to the above item (1), it is possible to accurately and efficiently measure the operating margin of a dynamic RAM or the like having a timing control circuit including the delay circuit.

(4) According to the above item (3), it is possible to easily determine the operating limit of a dynamic RAM, etc., and furthermore, it is possible to achieve the effect that the speed of the dynamic RAM, etc. can be increased.

(5) Items (1) to (3) above have the effect that the development period for products such as dynamic RAMs can be shortened, and the delay time adjustment work at the product inspection stage can be made more efficient.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the delay circuit DL2 shown in FIG. 1, a series resistor R2 and a MOSFET Q6 are provided between the inverter circuit N1 and the ground potential of the circuit. In the embodiment of FIG. 3, the P channel MO3F
ETQ3 (second MOSFET) and N-channel MO
CMO consisting of SFETQ8 (third MOSFET)
A parallel resistor R4 and N are connected between the S inverter circuit N3 (first CMOS inverter circuit) and the ground potential of the circuit.
Channel MOSFETQ9 (first MOSFET)
is provided, and the gate of MOSFETQ9 is connected to an external terminal V
A control voltage VC is supplied via C. The output terminal of the CMOS inverter circuit N3 is coupled to one electrode of the capacitor C2, and further coupled to the input terminal of a CMOS inverter circuit N4 (second inverter circuit) consisting of a P-channel MO3FET Q4 and an N-channel MO3FET QIG. A pull-down resistor R3 is provided between the external terminal VC and the ground potential of the circuit. When the external terminal VC is placed in a floating state, the MOSFET Q9 is turned off and its conductance is maximized, so that the delay time td of the delay circuit DL2 is set to the minimum value. When a control voltage VC is supplied to the external terminal VC, the conductance of the MOS FETQ9 is changed in accordance with this control voltage VC. The speed at which the charge accumulated in capacitor C2 is discharged is controlled according to the conductance of MOSFET Q9, and as a result, the delay time of delay circuit DL2 is continuously changed according to control voltage VC.

In the timing control circuit TC shown in FIG. 4, only the delay time of the delay circuit DL2 can be changed continuously.
A plurality of delay circuits that can continuously change the delay time as described above may be provided in the timing control circuit TC, or may be provided in a circuit block other than the timing control circuit. Although the control voltage VC is supplied through the delay circuit, the control voltage VC may be supplied through an internal terminal provided on the semiconductor substrate, such as a test pad. The basic configuration may be a bipolar transistor.

The delay circuit DL2 of FIG. 1 and FIG.
3) and the power supply voltage Vcc of the circuit. In this case, the delay time for a rising change in the delay circuit DL2 becomes almost negligibly small, and the delay time for a falling change continues continuously according to the control voltage VC. It will be subject to change.

Furthermore, the block configuration of the dynamic RAM shown in FIG. 5, and the delay circuit D shown in FIG. 181 and FIG.
Various embodiments can be adopted, including the specific circuit configuration of L2 and combinations of each control signal and address signal.

The above explanation will mainly focus on the dynamic type RA, which is the application field that is the background of the invention made by the present inventor.
Although the description has been made for the case where it is applicable to M, the present invention is not limited thereto and can be applied to, for example, static RAM and various read-only memories.
The present invention can be widely applied to semiconductor integrated circuit devices equipped with a timing control circuit (timing generation circuit) including at least a delay circuit.

(Effects of the Invention) A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows: In other words, a predetermined delay included in a timing control circuit such as a dynamic RAM, etc. A circuit whose conductance is changed according to a control voltage supplied externally M
By providing a capacitor that is charged or discharged via the OSFET and the above-mentioned MOS FET, the delay time of the delay circuit can be changed continuously according to the control voltage. It is possible to accurately and efficiently grasp the operating margin of dynamic RAM, etc. equipped with such a timing control circuit, and it is possible to shorten the product development period and improve the efficiency of timing adjustment work at the product inspection stage. .

[Brief explanation of drawings]

Figure 1 shows a dynamic RAM to which this invention is applied.
2 is a circuit diagram showing an example of the delay circuit included in the timing control circuit of FIG. FIG. 4 is a circuit diagram showing another embodiment of a delay circuit included in a timing control circuit of a dynamic RAM to which the invention is applied. FIG. Circuit Block Diagram Showing Embodiment FIG. 5 is a block diagram showing an embodiment of a dynamic RAM including the timing control circuit of FIG. TC...timing control circuit, DLI~DL3...
Delay circuit, N1 to N8...CMOS inverter circuit,
QINQ4...P channel O3FET, Q5~
QIO...N channel MO3FET%CI, C2.
...Capacitor, R1-R4...Resistance. M-ARY-- Memory array, PC... Precharge circuit, SA... Sense amplifier circuit, C8W... Column switch, RDCRI... Primary row address decoder, RDCR2... Secondary row address decoder, C
DCR: column address decoder, RADB: address buffer, AMX: address multiplexer,
REFC...Refresh address counter, CAD
B...Column address buffer, MA...Main amplifier, DOB...Data output cover sofa, DIB...Data person cover sofa. Fig. 1 Fig. 2-1◆VC Fig. 3riA Fig. 4-Fig. 5

Claims (1)

[Claims] 1. A first MOSF of a first conductivity type whose conductance is changed according to a predetermined control voltage supplied from the outside.
A semiconductor integrated circuit device comprising a delay circuit including a capacitor that forms a time constant circuit together with an ET and the first MOSFET, the delay time of which is continuously changed in accordance with the control voltage. 2. One electrode of the capacitor is connected to the ground potential of the circuit, and a predetermined input signal is received at the gate between the other electrode of the capacitor and the power supply voltage of the circuit, forming a charging circuit for the capacitor. A second MOSFET of a second conductivity type is provided between the other electrode of the capacitor and the ground potential of the circuit, and is connected in series with the first MOSFET, and together with the first MOSFET, a discharge circuit for the capacitor. and the second MO
A third MOSFET of the first conductivity type and a resistor are provided, which constitute the first CMOS inverter circuit together with the SFET, and a predetermined logic threshold level is provided between the other electrode of the capacitor and the output terminal of the delay circuit. 2. The semiconductor integrated circuit device according to claim 1, further comprising a second CMOS inverter circuit. 3. One electrode of the capacitor is connected to the ground potential of the circuit, and a predetermined input signal is received at the gate between the other electrode of the capacitor and the power supply voltage of the circuit, forming a charging circuit for the capacitor. A second MOSFET of a second conductivity type is provided, and a resistor connected in parallel with the first MOSFET, and a resistor connected to the first MOSFET and the resistor are connected between the other electrode of the capacitor and the ground potential of the circuit. The first CMOS transistor is connected in series with the first MOSFET and the resistor to form a discharge circuit for the capacitor, and together with the second MOSFET, the first CMOS
Third MOSF of the first conductivity type constituting the inverter circuit
ET, and a second CMOS inverter circuit is provided between the other electrode of the capacitor and the output terminal of the delay circuit to provide a predetermined logic threshold level. 2. The semiconductor integrated circuit device according to item 1. 4. The semiconductor integrated circuit device according to claim 1, 2, or 3, wherein the control voltage is supplied through a pad. 5. The semiconductor integrated circuit device is a dynamic RAM, and the delay circuit is included in a timing control circuit of the dynamic RAM. 4. The semiconductor integrated circuit device according to item 4.