JPS6325553B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an image enlargement/reduction method, and more particularly to a novel method in which an original image is read pixel by pixel, converted into a time-series binary electric signal, and electrically processed to perform enlargement/reduction. Hereinafter, the present invention will be explained in detail with reference to the drawings. Figure 1 shows that only the image information related to the extraction area is extracted from the first page memory, and the extracted image information is processed in order to enlarge or reduce the extraction area at a specified magnification (hereinafter simply referred to as enlargement). , the image information related to the copy area obtained through the processing is transferred to the second
FIG. 2 is a block diagram of one embodiment of the present invention. In Figure 1, an image related to a part or all area (extraction area) A specified on a document (or original image of the document) A is enlarged x times according to the specified magnification. This represents the operation of obtaining a desired copy image (or copy paper on which the copy image is recorded) by recording the image in a designated position or area (copy area) B of the copy paper. First, a method for enlarging/reducing image information used in the image processing means of the present invention will be described. Generally, the magnification is 0.05, 0.13, 1.05, 4.87,
There are an infinite number of 5.99 mags, and even if we limit the increments to 0.05,
0.05, 0.10,...5.25, 9.05...etc. There are infinite numbers. Also, even if the magnification is set to 4x or less, there will still be nearly 80 images in 0.05 increments. Therefore, it is necessary to consider a method to reduce this number. The basic equation is shown below. For a magnification x greater than 1, generally x=([x]+β)·α α=x/([x]+β). However, α is the correction coefficient, [x] is the integer part of x, that is, the maximum integer that does not exceed x, and β is a natural number.In order to make the enlarged image as faithful as possible to the original, the probability is that [x] + β is smaller. is advantageous, so if β=1, the above equation becomes as follows. x=([x]+1)・α α=x/[x]+1 For example, for x=3.33, since [x]=3, 3.33=4・α, α=0.8325. That is,
Multiplying by 3.33 means multiplying by 4 and adding 0.8325.
It is equivalent to multiplying. Here, since integer multiplication has been conventionally performed, the problem is to prepare a process for multiplying by α. The value of α is: (i) When 0<x<1, α=x and 0<α<1 (ii) When 1<x<2, α=x/2 and 1/2<α<1 n<x When <n+1, α=x/n+1 and n/n+1<α<1. FIG. 3 illustrates this situation. As you can see from the figure, if x is set at equal intervals, α must be finely chopped near 1, and if α is set at equal intervals, as the value of x increases, the magnification can only be selected coarsely. . Keeping this in mind, x and α
It is necessary to determine the value of In normal usage, the magnification x is naturally determined within a certain range, so
It is convenient to determine the correction coefficient α based on this. As an example, assuming that x is in a range of 4 or less and that the magnification should be changed at intervals of about 0.2, it is found that the minimum increment of the correction coefficient α is about 0.05. Therefore, 18 of α=0.05, 0.10, …, 0.90, 0.95
The following describes the case in which 2 pieces are prepared. The value of α used in the reduction process is 0.05 to 0.5, and α is used as a correction coefficient when expanding.
ranges from 0.5 to 0.95. As explained later, α
In the range of = 0.05 to 0.5, the process involves sampling and extracting a small number of data from a large amount of data, and α =
In the range of 0.5 to 0.95, the process involves thinning and removing a small number of data from a large amount of data.
Therefore, both processes have in common that a few are selected from a large number, and one method can be applied to the other. That is, for example, if it is possible to process α=0.05, it is also possible to process α=1−0.05=0.95. Therefore, in this specification, only processing for α=0.05 to 0.5 will be described. First, the selected α is expressed as an integer ratio A:B as follows.
It is expressed as 0.05→20:1 0.30→10:3 0.10→10:1 0.35→20:7 0.15→20:3 0.40→5:2 0.20→5:1 0.45→20:9 0.25→4:1 0.50→2:1 Each integer ratio means that B bits are selected from the one-dimensional array data of A bits, and in the case of sampling processing, only the selected data is extracted, and in the case of thinning processing, it is necessary to remove this data. ing. For example, in the case of (4:1), 1
Among the 4 bits a to d of the dimensional array, if it is a sampling process, one bit from a to d is selected and taken out, and if it is a thinning process, one bit is removed from abc, abd, acd, or bcd. This means to select and output the following. Next, patterns A and B as shown below are prepared for each value of α. Each pattern is α
If α is less than 0.5, it means that the data at the position "1" is sampled and extracted, and on the other hand, when α is more than 0.5, it means that the data at that position is thinned out and removed. Also, the Γ symbol is the number of "0"s intervening between adjacent "1"s when two patterns are arranged one-dimensionally - for example, Γ _AB is the pattern A
It represents the number of "0"s that exist between two "1"s when B is arranged next to "B". As is clear, the ratio of "0" to "1" that appears when the two patterns A and B are randomly arranged is equal to the correction coefficient. Arranging patterns A and B at random has the advantage of preventing the occurrence of moiré fringes. α = 0.25, 0.75 (4:1) A = 0100 Γ _AA = Γ _BB = 3 B = 0010 Γ _AB = 4, Γ _BA = 2 average Γ = 3 α = 0.20, 0.80 (5:1) A = 00100 Γ _AA = Γ _BB = 4 B = 01000 Γ _AB = 3, Γ _BA = 5 Average Γ = 4 α = 0.40, 0.60 (5:2) A = 01010 Γ _AA = Γ _BA = 2 B = 10010 Γ _AB = Γ _BB = 1 average Γ = 1.5 α = 0.10, 0.90 (10:1) A = 0000100000 Γ _AA = Γ _BB = 9 B = 0000010000 Γ _AB = 10, Γ _BA = 8 average Γ = 9 α = 0.30, 0.70 (10: 3) A = 0100100100 Γ _AA = Γ _AB = 3 B = 0100010010 Γ _BB = Γ _BA = 2 average Γ = 2.3 α = 0.05, 0.95 (20:1) A = 00000000010000000000 B = 00000000001000000000 0 Γ _AA = Γ _BB = 19 Γ _AB = 20, Γ _BA = 18 average 19 α = 0.15, 0.85 (20:3) A = 00010000001000000100 B = 00100000010000001000 Γ _AA = Γ _BB = 5 Γ _AB = 4, Γ _BA = 6 average 5.5 α = 0.35, 0.65 ( 20:7) A=01001001010010010010 B=01001001001010010010 Γ _AA = Γ _BB = 2 Γ _AB = Γ _BA = 2 average 1.875 α = 0.45, 0.55 (20:9) A = 01010101001010101010 B=01010101010010101010 Γ _AA = Γ _BB = Γ _AB = Γ _BA = 2 Average 1.3 α = 0.50 (2:1) A = 01 Γ _AA = Γ _BB = 1 B = 10 Γ _AB = 0, Γ _BA = 2 Average 1.0 Next, as an example, the procedure for multiplying by 2.22 shows. Since x=2.22=3×2.22/3=3×0.74, the correction coefficient α is 0.74. That is, you can first enlarge it by 3 times and then reduce it by 0.74 times. α=
Since it is approximated as 0.740.75 and α=0.75=15/20=3/4, it is sufficient to thin out 1 bit from 4 bits. Next, an example of processing in one direction will be shown. As mentioned above, each pattern is set to A=0100, B=0010, and the thinning command is
Suppose that AB is in the order ABAB... If the image data is...0011001110...

【table】 … … … …
… … …
Tripled data...000000111111000
000111111111000……
＊ ＊ ＊ ＊
＊ ＊ ＊
is obtained, and by thinning out the bits marked with * in the tripled data, the next 2.22 times the data is obtained.
2.22 times the data...00000111100001111111000...However, in this example, exactly 23 bits/10 bits = 2.3 times. As described above, two-dimensional non-integer enlargement processing can be performed also in other directions (there are methods of thinning out in line units and methods of thinning out in bit units). Hereinafter, each structure and operation will be explained with reference to the block diagram of FIG. In the figure, 1 and 2 represent a first page memory and a second page memory, respectively. It is assumed that the image information stored in the first and second page memories is stored from the first address in accordance with the order in which each pixel is scanned. Scanning is a main scanning process in which information on each pixel is sequentially input and output from left to right on a pixel row consisting of M' pixels lined up in the direction of arrow C in Figure 1 on the original image and the copied image. , and sub-scanning in which the pixel column on which the main scanning is performed is sequentially moved in the direction indicated by arrow D. Also, input/output of image information to page memory is k
This is done in units of bits, and information in units of k bits is hereinafter referred to as one word. Reference numerals 503 and 504 designate address designating circuits for addressing the first and second page memories, respectively. Address instruction circuit 5
03 is constructed as shown in the block diagram in FIG. In the figure 601, 602, 603, 604
is a register, 605 and 606 are counters, 60
7 and 608 are comparators, 609 is an adder, 610 is a multiplier, and 611 and 612 are OR circuits. The stored contents of registers 601, 602, 603, and 604 are ap, m, n', and M, respectively. ap is the address where the information related to the pixel P located at the upper left of the extraction area A shown in Figure 1, and a total of k pieces of information that are input and output to the page memory at the same time, m is the extraction area In A, n' is the number of addressing times required to input/output information about m' pixels lined up in the direction of arrow C in the page memory every k bits, and n' is the number of addressing times necessary for inputting/outputting information about m' pixels lined up in the direction of arrow C in extraction area A. where M represents the number of addressing operations required to input/output information about M' pixels lined up in the direction of arrow C in the original image to and from the page memory every k bits. Therefore, the address instruction circuit 50
3 performs operations as described below, and signals are supplied from the outside to perform such operations. In FIG. 4, when the start pulse signal a is supplied, counters 605 and 606 are initialized to display 0. Therefore, the operation result of the multiplier 610 is also 0, and the output g of the adder 609 is equal to that of the register 601, which is ap. Therefore, an address storing one word of information including information about pixel P in extraction area A is specified. Thereafter, by supplying the clock pulse b, the counter 60
5 counts and outputs the number of input pulses, so
The addresses specified by the output of the adder 609 are sequentially incremented by 1, such as ap+1, ap+2, . . . . When the mth clock pulse is input, the count value of counter 605 matches that of register 602, so comparator 607 generates a pulse signal. This pulse signal will hereinafter be referred to as an EOL signal (end of line), and information about m' pixels lined up in the main scanning direction (direction shown by arrow C in Figure 1) in extraction area A is extracted from page memory 1. This means that the addressing required for reading has been completed. This EOL signal is taken out to the outside as an output signal e, but at the same time, by supplying the EOL signal to one input of the OR circuit 611, the counter 605 is reset to 0 again. If signal C is not supplied when the EOL signal is generated, counter 606 and multiplier 610 do not change the display contents, so the address specified by output signal g is ap.
Therefore, the addresses specified by subsequent clock pulses b are exactly the same as those for the pixel column read out immediately before. In addition, when the input pulse signal C is supplied at the same time as the EOL signal is generated, the counter 606
increases the displayed value by 1, which causes the multiplier 61
0 causes the display content to change from 0 to M. That is, the multiplier 610 increases the displayed value by M each time the count value of the counter 606 increases by 1. Therefore, the address specified by the output signal g at this time is ap+M, and as is clear from FIG. This is nothing but an address that stores one word of information about a pixel. Thereafter, by supplying clock pulses to the counter 605, the designated address is
ap+M+1, ap+M+2, etc., and addresses are specified so that information about pixel columns adjacent in the sub-scanning direction to the previously read pixel column consisting of m' pixels is read out. . As is clear from the above explanation, if the pulse signal C is supplied when the EOL signal is generated from the comparator 607, the pixel column related to the information to be read from the page memory 1 from now on will be changed to the pixel column related to the information read immediately before that. The pixel row is one pixel advanced in the sub-scanning direction from the pixel row, and if no signal is supplied, the address storing the information of each pixel will be specified again for the pixel row that was read immediately before. Become. Thereafter, by repeating these operations, addresses storing image information regarding extraction area A are sequentially designated. Now, when the n'th pulse signal is supplied to the counter 606, the count value of the counter 606 matches the set value of the register 603, and the comparator 608 generates a pulse signal. This pulse signal is hereinafter referred to as an END signal, and indicates that all the image information related to the extraction area A has been read out from the page memory 1, and at the same time, after predetermined processing has been performed on the read image information, It is taken out to the outside as a signal f, which means that all data has been stored in the address related to the copy area of the second page memory 2. Address instruction circuit 504 is configured as shown in FIG. As can be seen, this circuit 50
4 are from the address instruction circuit 503 shown in FIG.
08 is removed, and accordingly, output signals e and f do not exist. 701,704
are shown in the registers as aq and M _1, respectively.
705 and 706 are counters, 709 is an adder, 7
10 is a multiplier, and 711 is an OR circuit, which operate as described below. When the start pulse signal a is supplied, the counters 705 and 706 are initialized to 0. Therefore, the calculation result of multiplier 710 is also 0, and adder 709
The display content of is equal to aq in register 701.
It is. aq contains the information of the image Q located at the upper left in the copy area B shown in FIG.
This value represents the address at which word image information is stored, and this value becomes the address designation signal g that is output first. Thereafter, as the counter 705 counts the number of clock pulses b supplied one after another, the output signal g becomes
It continues to increase in the order of aq+1, aq+2, etc. This is because the EOL signal e is supplied to the OR gate 711,
The EOL signal continues until the display value of the counter 705 shows 0 again. If the pulse signal c is supplied at the same time, the display content of the counter 706 will be 0.
to 1, and based on the change, the multiplier 71
The display content of 0 changes from 0 to _M1 . M ₁ is the number of address specifications required to input information about M ₁ ' pixels lined up in the main scanning direction to the second page memory 2 in units of k bits (in other words, units of words) in the copied image. , when the pixel arrangements constituting the original image and the copied image are the same, M=M ₁ . Therefore, the address specified by the output signal g is
aq+M ₁ , which is the total k of pixels lined up in the main scanning direction from the pixel located directly below pixel Q in Figure 1.
It is nothing but an address to which one word of information consisting of information about each pixel is to be written, and is specified sequentially depending on the arrival of clock pulse b.
The addresses Aq+M ₁ +1, aq+M ₁ +2, . . . relate to pixel columns that are advanced by one pixel in the sub-scanning direction from the pixel column related to the previous writing.
Thereafter, by repeating the above-described operations, addresses relating to all copy areas are specified. The image processing means shown in the block diagram in FIG.
Only the image information related to the extraction area is extracted from the first page memory, the image information is processed to enlarge the image related to the extraction area x times, and the resulting image information is transferred to the second page memory. In executing a series of operations to store the image in the address related to the copy area of the memory 2, the image related to the above-mentioned extraction area is first enlarged by x times, and then reduced by α times to x
It is configured to send an image signal to obtain an image that has been enlarged twice. The operation of the image signal means shown in FIG. 2 will be explained below. When the control circuit 523 sends out the start pulse signal 302 instructing the start of the series of operations described above, the address designating circuits 503 and 504 designate the addresses ap and aq, respectively, as described above. Also, by supplying the start signal, the frequency dividers 510, 511, 512, and 513 are set to 0.
is initialized to . Both of these frequency dividers are
Count the pulses to be input from now on and calculate X, k・
Simultaneously with the input of the X, X, and kth pulses, the initial state is restored, and the above operation is repeated for the pulses that are subsequently input. Note that at the same time as the first pulse is input to the frequency divider 511, the other frequency dividers 512, 513, and 514 are
It is configured to output a pulse signal simultaneously with the input of the X, X, and k-th pulses. Furthermore, the start signal 302 is an OR circuit 514,
One word of information, which is supplied to the shift register 505 and indicated to the data gate of the page memory 1 via the delay circuit 522, is input to the shift register 505. The shift register 505 is a parallel-in serial-out type k-bit shift register, and the information input at this time is sent to the address instruction circuit 5.
This is nothing but 1 word (k bits) of information stored at the address ap specified by 03. In this state, the control circuit 523
A clock pulse 301 is then sent out. The clock pulse 301 is input to a counter 510, and from the counter 510, a pulse train 305 whose frequency is divided by 1/x (hereinafter referred to as a shift signal) is supplied to a shift register 505 and a flip-flop 507. Each time the shift signal 305 is supplied, the shift register 505 sends the stored image information one bit at a time to the flip-flop 507, and the flip-flop 507 outputs the stored image information one bit at a time, and the flip-flop 507 outputs the stored image information one bit at a time.
The state of the output gate Q is changed and the state of the output gate Q is held until the next shift signal 305 is supplied. Output gate Q of flip-flop 507
The image information shown in is further transferred to the shift register 5.
Sent to 06. The shift register 506 is a k-bit serial-in-parallel-out type shift register, and each time a pulse signal (hereinafter referred to as a shift signal) 309 is supplied, the shift register 506 converts the state indicated at the output gate Q of the flip-flop 507 into information in units of bits. Enter as . The shift signal 309 is the clock pulse 301 delayed by a delay circuit 519 and gated by AND circuits 517 and 518. The other input of the AND circuit 517 is
The output of the shift register 508 is also input to the other input of the AND circuit 518.
9 outputs are supplied. shift register 50
8 and 509, reduction information corresponding to the correction coefficient α is stored in advance. Note that the contents of the two shift registers may be the same or different. These reduction information can be obtained by preparing an appropriate number of two or more different reduction patterns determined for the correction coefficient α for sampling or thinning, and arranging them irregularly (for example, the pattern described above). It consists of patterns A and B consecutively arranged in an appropriate order. In addition, these shift registers 508, 509
is configured such that the information output by supplying the pulse signal is sent again to the input of the shift register and stored. For this reason, the states of the output gates of the shift registers 508 and 509 will cycle, and the capacity of the shift register should be made large enough so that the regularity of sampling or thinning caused by this cycle can be ignored. good. The clock pulse 301 sent out from the control circuit 523 is input to the AND circuit 517 via the delay circuit 519 and is also supplied to the shift register 508.
The pulse train 308 output from 17 has a correction coefficient α
It is equal to the clock pulse 301 sampled or decimated according to . On the other hand, the shift register 509 is supplied with the EOL signal sent from the address instruction circuit 503, and each time the EOL signal 306 is supplied, the shift register 509
09 changes the output state according to reduction information stored in advance. Therefore, if the output state of the shift register 509 is L (Low), the pulse train 308 is not sent out from the AND circuit 518, and the pulse train 308 is not sent out from the flip-flop 50.
The image information shown at output gate Q 7 is not input to shift register 506 . Further, if the output state of the shift register 509 is H (High), the pulse train 308 passes through the AND circuit 518 and becomes the shift signal 309, and the output Q of the flip-flop 507 becomes the shift signal 309.
The shift register 506 uses the signal as image information.
will be required to be entered. The EOL signal supplied to the shift register 509 indicates that the addressing required to read out information about m' pixels lined up in the main scanning direction from the page memory 1 in the extraction area A shown in FIG. 1 has been completed. As described above, the output state of the shift register 509 does not change while the information regarding one pixel column in the extraction area is being processed. Therefore, when the output of the shift register 509 is in the H state, the number of pulses of the shift signal 309 supplied to the shift register 506 is
05 and the number of pulses of the shift signal 305 supplied to the flip-flop 507 is multiplied by X and then sampled or thinned out according to the reduction information corresponding to the correction coefficient α. Therefore,
The information input into the shift register 506 is
It represents an image obtained by multiplying the image related to the information read from the page memory 1 by X (=X·d) in the main scanning direction. The image information stored in the shift register 506 is transferred to the second page memory 2 in units of one word (in units of k bits), and is transferred to the second page memory 2 in the address instruction circuit 504.
is stored at the address specified in . This is the counter 5 that measures the number of pulses of the shift signal 309.
This is done by generating a pulse signal every time the counter 13 measures k pulses to put the page memory 2 in a writable state (write mode), and the pulse signal generated by the counter 513 is sent to the delay circuit 5.
20, it becomes the input signal b of the address designating circuit 504, and causes the address designating circuit 504 to designate the address to be written next. On the other hand, the address instruction circuit 503 uses the frequency divider 51
The pulse signal 304 sent from 1 is the input signal b
This indicates the address of the information to be read next. As already mentioned, the frequency divider 511 counts the clock pulses 301 and outputs the pulse signal 3 every time the k.X pulse is counted.
04. Therefore, the address instruction circuit 503 will change the address every time the k.X pulse is measured thereafter. The pulse signal 304 is also supplied to the shift register 505 via the OR circuit 514 and the delay circuit 522, and causes one word of information related to the address instructed by the address instruction circuit 503 to be input to the shift register 505. The shift register 50
Processing of the information stored in 5 is performed as described above. Now, according to the above-described procedure, when all the information about the first pixel column in the main scanning direction of the extraction area A shown in FIG. Applicable
The EOL signal is supplied to the OR circuit 611 and frequency divider 512 of the address instruction circuit 503, and the output of the frequency divider 512 is supplied to the counter 606 of the address instruction circuit 503 as a C signal. As a result, the address instruction circuit 50
3 reads out m' pixels arranged in the main scanning direction in the extraction area A shown in FIG. 1 X times (i.e.,
(the original image is multiplied by X in the main scanning direction). Therefore, if the EOL signal is not the Xth one, the pixel column related to the information read just before is the The pixel rows advanced in the sub-scanning direction will be read out thereafter. Further, the EOL signal initializes the frequency divider 513 via the OR circuit 515, and is also used as the input signal e of the address instruction circuit 504 via the delay circuit 521 and the AND circuit 516 as the input signal c.
It is supplied as. The output of the shift register 509 is supplied to the other input of the AND circuit 516. As described above, the shift register 509 changes the output state according to the stored correction coefficient α every time the EOL signal is supplied. Therefore, the shift register 509 of the EOL signal
If the output state of the shift register 509 is H at the same time as the EOL signal is supplied to the address instruction circuit 504, the EOL signal is supplied to the address instruction circuit 504 as an input signal c. Therefore, the address specified thereafter by the address designating circuit 504 will be related to a pixel column that is advanced by one pixel in the sub-scanning direction from the pixel column related to the previous writing. Also, the output state of the shift register 509 is L.
In this case, since the input signal c is not supplied, the address designating circuit 504 is set so that the pixel column related to the immediately previous writing is designated again. However, since the AND circuit 518 also stops sending out the shift signal 309, the information for one pixel column read from the page memory 1 will not be written to the page memory 2 from now on. That is, the information related to each pixel column arranged in the main scanning direction in the extraction area A is read out X times, and the lines corresponding to the correction coefficient α are sampled or thinned out, so that the information in the extraction area A is Such an image is multiplied by x (=X・α) in the sub-scanning direction, and each pixel column in the main scanning line that makes up this x-multiplied image is divided into pixels according to the reduction information corresponding to the correction coefficient α. Sampling or thinning is performed. By continuing to perform the above operations, information representing an image obtained by enlarging the image related to the extraction area on the original image by x times is stored in the second page memory 2.
It is clear that the data is stored at an address related to the copy area of . The end of the work is indicated by the END signal f sent from the address instruction circuit 503. The detailed explanation of the END signal f is as described above, and the END signal f
When the clock pulse 301 is sent to the control circuit 523, the control circuit stops sending out the clock pulse 301, and the series of operations described above are completed. In addition, in the above, the magnification is greater than 1 -
In other words, we have explained the case of enlargement, but in the case of reduction where the magnification is smaller than 1, [x] is 0, so if we directly apply the correction coefficient α to the original image signal in the first memory and perform the sampling or thinning operation, This is clearly a good thing, and no further explanation is necessary. In the above explanation regarding the configuration example of the image processing means, the position and size of the extraction area on the original image, the position of the copy area on the copied image, and the magnification if enlargement processing is involved. , these have all been treated as having been set in advance. However, these should not be fixed in each copying machine, but it is desirable that they can be set for each job according to the desired work content. The embodiment shown in FIG. 2 is a configuration example of an image processing means that enables transcription work accompanied by enlargement processing as described above. It is determined by the set values of three registers 601 to 603 provided in . This is because the position of the extraction area _A on the original image A shown in FIG. If expressed as _l2 , the corresponding quantities are the display contents ap, m, n' of the registers 601, 602, 603 in the block diagram of the address instruction circuit 503 shown in FIG. It is from. Furthermore, the position of the copy area B on the copy image B can also be represented by the pixel Q, and the pixel Q
The position of is determined by the value displayed in register 701 in the block diagram of address instruction circuit 504 related to the second page memory shown in FIG. Therefore, by providing a means for externally inputting a numerical value corresponding to the content of the desired work into the above-mentioned register, that is, an area specifying means, the position and size of the extraction area on the original image and copying can be determined for each work. The position of the copy area on the image can be set. The operator console shown schematically in FIG.
It constitutes a part of such area specifying means. The operator can enter a numerical value corresponding to the desired work content using a set of digital keys 851 provided on the console, and furthermore, the operator can input a numerical value corresponding to the desired work content, and further determines what the numerical value indicates in the above-mentioned area to be specified. By instructing this using the auxiliary key 852, numerical values corresponding to the work contents can be entered into each of the registers described above. FIG. 7 is a block diagram showing the configuration of the area specifying means. In the figure, 801 is an operator console, 802, 601, 602, 60
3,701,808-1,808-2,808-
3 is a register, 803 and 810 are selector control circuits, 804 and 811 are selectors, 807 and 809
are arithmetic circuits, 812-1 to 19,508,509
is a shift register. The operator inputs numerical information into the register 802 by hitting the digital key 851 on the operator console 801, and also uses the auxiliary key 852 to indicate what the numerical value represents. The selector control circuit 803 selects the register 802 according to the instruction.
The destination of the numerical information stored in is selected, and the selector 804 is controlled based on the result. Registers 601, 602, 603, and 701 are shown in FIGS. 4 and 5, respectively. Therefore, when any one of these registers 601, 602, 603, and 701 is designated, the numerical information of register 802 is input to the register related to the designation. FIG. 7 also shows the configuration of a magnification specifying means that allows specifying a magnification for each task when enlarging processing is involved. If the numerical information input into the register 802 via the digital keys on the operator console 801 is instructed to represent a magnification by a later pressed auxiliary key, the selector control circuit 803 inputs the numerical information into the register 802.
The selector 804 is controlled so that the numerical information of is transferred to the arithmetic circuit 809. The arithmetic circuit 809 calculates the numerical value X and α such that X=[x]+1 α=x/X for the numerical information x. The resulting X is transferred to registers 808-1, 808-2 and multiplication circuit 807. The multiplication circuit 807 calculates the product k×X of the transferred numerical value X and inputs this into the register 808-3.
The registers 808-1, 808-2, 808-
3 are frequency dividers 510, 511, 5 in FIG.
12. FIG. 8 is a block diagram of frequency divider 510, and FIG. 9 is a block diagram of frequency dividers 511 and 512. In these figures, parts having the same configuration and function are given the same reference numerals. 821 is a counter that measures the number of pulses for the supplied pulse train, 822 is a register, and 823 is a counter 821
This is a comparator that compares the measured value of and the display content of the register 822, and when the two match, generates a pulse signal to reinitialize the counter 821. Further, 824 is a register whose storage content is constant 1, and 825 is a comparator. Said 824, 82
5 is not provided in the frequency dividers 511 and 512. This means that only the frequency divider 510 is connected to the other frequency dividers 511 and 51.
Unlike 2, this is because a pulse signal is sent to the outside when the first pulse is input. Now, the other numerical information (correction coefficient) α calculated in the arithmetic circuit 809 is transferred to the selector control circuit 810. Here, the reduction magnification α ₁ prepared in advance for the calculated numerical information α,
..., α ₁₉ is selected, and the selector 811 is controlled according to the selection result. The shift registers 812-1 to 19 include
For example, reduction information representing 19 correction coefficients (reduction magnification) α ranging from 0.05 to 1.0 in 0.05 increments is stored in advance, and each shift register 812
The output is input to the selector 811. The selector 811 selects the output of the shift register storing reduced information α _k that is closest to the calculated numerical value α according to instructions from the selector control register 810 . Therefore, reduction information representing the reduction magnification α _k is input to shift registers 508 and 509 . The fact that the magnification specifying means described above makes it possible to select the magnification for each task is that among the components shown in the block diagram of FIG. , and shift registers 508 and 509. Now, by providing the area specifying means and magnification specifying means described so far, it is possible to specify the area for extraction or copying according to the content of each work.
When enlarging processing is involved, it is possible to specify the magnification, and the operator performs operations to specify these by hitting the digital keys and auxiliary keys on the operation desk according to the work content. When performing this operation, the operator can simultaneously observe the original image and the extraction area on the original image, and can immediately know (via the digital key) the numerical value to be entered based on the observation results. If possible, work efficiency can be further significantly improved. This also applies to the copy image and the copy area on the copy image. FIGS. 10 and 11 show the schematic configurations of original image display means and copy image display means, respectively, which enable the above-described observation. In FIG. 10, 831 is a document with the original image on the bottom surface, 832
is a platen glass on which the original is placed.
833 is a mirror, 834 is a lens, and 835 is an exposure lamp, and these constitute image projecting means. 835 is a screen on which the original image of the original is projected, and it is convenient to attach ruled lines and numerical values to the screen so that the position of any point on the projected image can be immediately read in coordinate format. be. Therefore, the operator reads the coordinates of the two points P and R shown in FIG. 1, which are necessary and sufficient points to specify the position and size of the extraction area on the original image projected on the screen, and All you have to do is type in the read value using the digital key and auxiliary key. However, the numbers entered at this time are
601, 602, 603, 701 in Figure 7
Since the value is not directly input into the register, a calculation circuit is required to calculate the value to be displayed in the register from the numerical value indicating the entered coordinates.
The calculation circuit can be placed at the location of register 802 in FIG. The calculation circuit is internally equipped with a plurality of registers, and numerical information based on a digital key is temporarily stored in a register designated by an auxiliary key within the calculation circuit. When all the numerical information necessary to start calculation is input into the register, the calculation circuit inputs the registers 601, 602, 60.
Calculate the numerical value to be input into 3, and input the calculation result into each register. In this manner, numerical values ap, m, n' representing the position and size of the extraction area are recorded in each register 601-603. The designation of the transfer area is also recorded in the corresponding register by a similar operation. That is, by inputting numerical information about the coordinates of point Q shown in FIG. However, in this case, the transcription position designating means on the copied image may be the one shown in FIG. This copy image display means inserts a copy paper sample (not shown) between a coordinate display board 841, which is a transparent plate with ruled lines and numerical values, and a mounting table 842, and transfers the copy paper onto the recording paper via the coordinate display board 841. The arrangement is such that the position of the area, that is, the coordinates of the point corresponding to point Q shown in FIG. 1, can be read from the ruled lines and numerical values attached to the coordinate display board 841. The calculation formulas executed in the calculation circuit described above differ depending on how the coordinates are selected. for example,
The point located at the upper left of the original image and the copied image shown in FIG.
When grading (integer) numerical values using the minimum (nominal) unit of length consisting of pixels, two sets of numerical values (x ₁ , y ₁ ) input as the coordinates of point P and point R,
For (x ₂ , y ₂ ), ap, m, and n' are calculated using the following formulas. ap=x ₁ +kMy ₁ m=x ₂ −x ₁ n'=k(y ₂ − y ₁ ) Also, for a set of numerical values (x ₃ , y ₃ ) input as the coordinates of point Q, aq is given by the formula aq=x ₃ +kMy ₃ . As is clear from the above description, according to the present invention, the following effects can be achieved. (1) Since the density of the pixels constituting the image after enlargement/reduction is kept almost constant, the image quality does not change or deteriorate due to enlargement/reduction. (2) Since the correction coefficients are set to integer ratios, enlargement/reduction of arbitrary magnification can be easily carried out by simply preparing a relatively small number of correction coefficients in advance. (3) By not imparting regularity to the correction coefficients, moiré fringes that tend to occur in enlarged/reduced images can be effectively reduced.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of the present invention, and FIG. 2 is a conceptual diagram of the present invention.
A block diagram of an embodiment, FIG. 3 is a diagram for explaining the principle of the present invention, FIGS. 4, 5, 8, and 9 are a partial detailed block diagram of FIG. 2, and FIG. 6 is a diagram for explaining the principle of the present invention. 7 is a block diagram showing its internal configuration, FIG. 10 is a schematic diagram of the original image display means, and FIG. 11 is a schematic diagram of the transcription position designation means on the copied image. be. A: Original image, B: Copied image, 1: First page memory, 2: Second page memory, A: Extraction area, B: Transcription area.

Claims (1)

[Scope of Claims] 1. A method for enlarging or reducing the original image by main scanning and sub-scanning the original image pixel by pixel, converting it into a time-series binary electric signal, and processing the electric signal, First, each pixel constituting the original image is multiplied in the main scanning and sub-scanning directions by a natural number equal to the sum of the integer part of the desired magnification and a preset natural number to form an intermediate enlarged image; On the other hand, a correction coefficient for specifying pixels to be sampled or thinned out of the pixels constituting the intermediate enlarged image is predetermined as an integer ratio A:B that approximates the ratio of the desired magnification to the natural number of the sum. , obtaining an image with a desired magnification by sampling or thinning out A to B pixels of the pixels constituting the intermediate enlarged image according to the correction coefficient to reduce the intermediate enlarged image; Featured image scaling method. 2. The image scaling method according to claim 1, wherein the preset natural number is 1.