JPS63228763A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the performance of a high electron-mobility FET by forming the hetero-junction of an InGaAs layer and an InGaP layer, to which an impurity is doped, and using the InGaAs layer as the channel of interface- quantized carriers. CONSTITUTION:An AlGaAs buffer layer 2, an InGaAs layer 3, an InGaP electron supply layer 4 and a GaAs layer 5 are shaped onto a semi-insulating GaAs substrate 1. Source-drain electrodes 8 are patterned onto the layer by employing AuGe/Au, etc., and alloy regions 8A are formed in depth reaching the layer 3 through heat treatment. A gate electrode 9 is shaped onto the layer 5. According to such constitution, the surface concentration of a two-dimensional electron gas is increased by the hetero-junction of the layer 3 and the layer 4. Since the electrode 9 is formed onto the layer 5, the large height of a Schottky barrier is acquired, thus improving performance.

Description

[Detailed Description of the Invention] [Summary] The present invention forms a heterojunction between an In, Ga+-, As semiconductor layer and an InXGa,-, P semiconductor layer in a semiconductor device using interfacial quantized carriers. , the InXGa1-XP
The semiconductor layer is a carrier supply layer, and the 1nxGa I -xA
By using the s semiconductor layer as a carrier channel, it is possible to increase carrier concentration and improve stability.

[Industrial application field]

The present invention relates to semiconductor devices, particularly high electron mobility field effect transistors (HEMTs) that utilize interfacial quantized carriers.
) and other compound semiconductor devices.

For example, in HEMT, the mobility of electrons is increased by spatial separation doping and quantization at the heterojunction interface, and there are strong expectations as a high-speed device, but improvements are still desired as described below.

[Conventional technology]

As an example of a semiconductor device that achieves high carrier mobility through carrier quantization and spatial separation doping at a heterojunction interface, a schematic cross-sectional view and an energy band diagram of an example of an IEMT are shown in Figure 4 (al and (bl). show.

The semiconductor substrate is formed on a semi-insulating gallium arsenide (GaAs) substrate 21, and includes a non-doped i-type aAs channel layer 23 that serves as both a buffer layer and a channel layer, and aluminum gallium arsenide (AI), which has a lower electron affinity than the undoped i-type aAs channel layer 23.

An n-type electron supply layer 24 made of Ga1-, As) is laminated, and from this AlGaAs electron supply layer 24 the GaAs layer 2
A two-dimensional electron gas 26 is formed near the heterojunction interface by the electrons that have transitioned to 3. This two-dimensional electron gas 26 has almost no reduction in mobility due to impurity scattering, and the highest mobility can be obtained at low temperatures, such as 77°C or lower, where lattice scattering is reduced.

Source and drain electrodes 28 and a main gate crosspiece 29 are provided on this semiconductor substrate, and the surface concentration of the two-dimensional electron gas 26 is controlled by the Schottky depletion layer formed by the gate electrode 29 to perform transistor operation.

AlxGat-xA, which is the electron supply layer of this IIEMT
The mixed crystal ratio X of AlAs and GaAs in the s-layer 24 is selected by comparing and examining the mobility μn and the surface concentration Ns of the two-dimensional electron gas 26, and the mobility μn is x=0.2 to 0.3. Also, from the surface concentration Ns, the i-type GaAs layer 23
It is preferable that the energy level difference in the conduction band between x and x is about 0.24 eV or more, and therefore x=0.30 or more.

On the other hand, however, if the mixed crystal ratio X of Ga, □As to Al is made larger than about 0.25, the doped St etc. will form a deep donor level called a DX center.

For this reason, even if the doping amount is increased, the amount of doping will be increased by 2
The surface concentration Ns of the dimensional electron gas 26 does not increase and further increases by 200
If infrared rays are incident below the level of
photo conductivity).

Therefore, the above-mentioned GaAs/AlGaAs HEMT
In this case, the drain current, the transfer conductance g1, etc. are restricted, and furthermore, these characteristics and the threshold voltage V, etc. have a large temperature dependence, which reduces the stability of operation.

GaAs/AlGaAs HE with such problems
In order to improve MT, the present applicant first filed a patent application in 1986-1.
No. 95579 provides the following structure whose energy band diagram is shown in FIG. 4(C).

In the semiconductor device according to the invention, the electron supply layer 24A is made of indium gallium phosphide (Ino, 4sGao, 5zP).
formed by Since InGaP does not form a DX center, it not only increases the surface concentration Ns of the two-dimensional electron gas 26 and improves operational instability, but also improves the stability of the organic The effect of improving chemical stability during and after the growth process such as metal pyrolysis vapor deposition (?1O-CVD) has also been achieved.

[Problem that the invention seeks to solve]

The invention of the prior application has the above-mentioned effects, but improvements such as further increasing the surface concentration Ns of the two-dimensional electron gas without sacrificing its advantages will improve the performance of HEMTs, etc., which have great expectations as high-speed devices. The purpose is to improve performance.

[Means for solving problems]

The problem is that indium gallium arsenide compounds (In,
Ga1□As) semiconductor layer and an impurity-doped indium gallium phosphide compound (I n XGa 1.-XP
) with a heterojunction with the semiconductor layer, in the Ga, J
This problem is solved by the semiconductor device according to the present invention in which the s-semiconductor layer serves as a channel for interfacially quantized carriers.

[For production]

InxGa+-xP/In) (Gal=
The xΔS heterojunction lattice matches the former to GaAs, for example [no. 48Gao, 5ZP and the latter is Ino
, +5Gao, esAs, ΔEC=0.
32eV, Ino, 4BGao, of the earlier invention,
A conduction band energy level difference larger than ΔEc=0.2 eV of the SAP/GaAs heterojunction is obtained, and an increase in the surface concentration Ns of the two-dimensional electron gas is achieved.

Note that using In, Ga, -, and As for the channel layer means that x=0.53 on an indium e (InP) substrate, for example.
The channel layer is made of InXGa1-XAs, and the InP
An example in which the electron supply layer is
No. 7, JP-A No. 59-5675), etc., but even in such a conventional example, ΔEC=0.2 eV.

However, InxGa and □As have different lattice constants from GaAs, which is often used as a substrate for semiconductor devices.
In order to realize this semiconductor device using a GaAs1 plate, for example, this InXGa1-xAs semiconductor layer is required as a channel for quantized carriers. To prevent this, or to grow In, Ga, □As semiconductor layers and InxGat-xr' semiconductor layers with mutual lattice matching through a buffer layer that alleviates the lattice constant difference on the GaAs semiconductor substrate. Use structure.

〔Example] The present invention will be specifically explained below using examples.

FIGS. 1 fa) and fb) are a schematic cross-sectional view and an energy band diagram showing a first embodiment of the present invention.

The semiconductor substrate of this example is on a semi-insulating GaAs substrate 1,
AlGaAs buffer layer 2, InGaAs channel layer 3
, the TnGaP electron supply layer 4, and the GaAs layer 5 are formed, for example, by the MO-CVD method as described below.

Code Composition Impurity Thickness 5
GaAs 5t-IXIO"cm-3#
lOnm4 InxGat-xP; x=0.48 5
i-1xlO"am-'#30nm3 rnXG
a+-x^s;x= Below Non-doped Below 2 A
1. Ga+-, AsHx = below non-doped "q
Is In this embodiment, the buffer layer 2 is x = 0.2 to 0.3
The reason for this is to obtain a high resistivity of, for example, about 10" Ωcm or more. Note that even if AlGaAs is used for this buffer layer 2, it is a non-doped high resistance layer, so the above-mentioned No problems arise.

Also, layer 2 of 77 is made of GaAs or Ino, naG.
It is also possible to use ao, szP, etc., and in this case, the energy band has the shape illustrated by the broken line in FIG.

In the configuration of this embodiment, taking into consideration the occurrence of crystal defects, Inx
For example, the mixed crystal ratio X of the Gat-XAs channel layer 3 is 0.1.
5 to 0.20 nm, and the thickness is selected to be, for example, about 10 to 15 nm.

If X is increased, the ΔEc between Ino, asGao, and 52P electron supply layer 4 will increase, but the difference in lattice constant from GaAs will also be large, and the thickness will be limited. In this embodiment, these are set to values shown in the following data example, for example.

Source and drain electrodes 8 are patterned using, for example, gold germanium/gold (AuGe/Au) on this semiconductor substrate, and heat treatment is performed to form an alloy region 8A at a depth that reaches the InXGap-xAs channel layer 3.

Further, a gate electrode 9 is provided on the GaAs layer 5 using, for example, AI. By providing the gate electrode 9 on the GaAs layer 5 in this manner, a greater height of the gate electrode can be obtained than when providing the gate electrode 9 on the Ino, asGao, or szP electron supply layer 4.

FIG. 2 is a diagram showing the average values of the surface concentration Ns and the mobility μn of the two-dimensional electron gas 6 at temperatures of 300 K and 77 K for the semiconductor substrates of this example and the prior invention, and
Ino, 'aa of each sample grown by O-CVD method
Gao, szP electron supply layer 4 has an impurity concentration of 1×101
e c m-:l, and the thickness is 37 nm.

In the embodiment of the present invention shown as △ and △, the mixed crystal ratio X of the InxGat-, As channel layer 3 is 0.15, and the thickness is 8. 'Inm
In the embodiment shown by . In addition, the samples of the prior invention are indicated by ・ and ○, and mu, ■, ・
indicates 300K, △ indicates mouth, and ○ indicates 77K.

It is clear from this data example that the surface concentration Ns of the two-dimensional electron gas 6 is significantly increased by the present invention, and Ino,
If the impurity concentration of the a8Gao, s□P electron supply layer 4 is made higher than the IXIO"cm-3 of this embodiment, the surface concentration N
s can be further increased.

Note that the mobility μn is considered to be the same at room temperature of 300K. At low temperatures, the mobility μn tends to decrease as the surface concentration Ns increases, similar to the previously known fact.
The selection is made depending on the thickness of the s-channel layer 3, etc.

Further, FIG. 3 is a schematic sectional view showing a second embodiment of the present invention.

The semiconductor substrate of this example is a semi-insulating GaAs substrate with a buffer layer 12 having a superlattice structure, an InGaAs layer 13 serving as a buffer layer and a channel layer, and an InGaP electron supply layer 14, for example, by MO-CVD as follows. A source electrode, a drain electrode 18, and a gate electrode 19 are provided.

Code Composition Impurity Thickness 14
InxGa1-xP; x=o, 75 5i-IXIO
"cm-"#30nm13 In, Ga1-xAs
;x=0.30 non-doped '=1μm12
Alternately stack 10 to 20 layers of the following 12a and 12b 12b
InAs non-doped -1.5nm
12a GaAs non-doped '=1
．． 5r+m In this example, the mixed crystal ratio of the In, Ga + '', As channel layer 13 is set to x=0.30, and In
, Ga+-xP electron supply J'i 14 is lattice-matched to this as X 0.75, these layers and the GaAs substrate 11
The lattice mismatch between the two is alleviated by the buffer layer 12 having a GaAs#nAs superlattice structure.

In this embodiment as well, a surface concentration Ns of the two-dimensional electron gas 16 that is equal to or higher than that in the first embodiment is obtained.

Note that the present invention is not limited to application to the HEMTs cited in the above explanation, but is applicable to, for example, velocity modulation transistors (helocity-modulation transistors).
nsistor.

H, 5akaki: Jpn, J, Appl, Phys.
, Vol. 21. No. 6. June 1982), or Quantum Well Transistor (Single Quantum Well Transistor)
m Well Transistor, C,llam
aguchi et al.: Jpn.

J, Appl, Phys, Vol, 23. No, 3.
It can be applied to all semiconductor devices that utilize high-mobility carriers by spatially separated doping and interface quantization, such as (March 1984).

〔Effect of the invention〕

As explained above, according to the present invention, in a semiconductor device in which carriers quantized at the interface by a heterojunction are used as channels, instability in operation can be further eliminated, carrier concentration can be increased, etc., and it is expected to be used as a high-speed device. H.E.
Great effects can be obtained on MT, etc.

[Brief explanation of the drawing]

Fig. 1 is a schematic cross-sectional view and energy band diagram of the first embodiment, Fig. 2 is a diagram showing an example of the areal concentration and mobility of a two-dimensional electron gas, and Fig. 3 is a schematic cross-section of the second embodiment. FIG. 4 is a schematic cross-sectional view and an energy band diagram of a conventional example. In the figure, 1 and 1 are semi-insulating GaAs substrates, 2 is a non-doped GaAs buffer layer, and 12 is a G
aAs/InAs superlattice structure buffer layer, 3.13 InxGa1-, As channel layer, 4.14 In, G
a+-, P electron supply layer, 5 is a non-doped GaAs layer, 6.16 is a two-dimensional electron gas, 8.18 is a source and drain electrode, and 9.19 is a gate electrode. +-', - ¥ 1 Diagram 3 Diagram 2D 7c Electrical signal power failure standard and movable property system 2 Diagram

Claims (1)

[Claims] 1) A heterojunction between an indium gallium arsenide compound semiconductor layer and an impurity-doped indium gallium phosphide compound semiconductor layer is provided, and the indium gallium arsenide compound semiconductor layer is used as a channel for interfacially quantized carriers. A semiconductor device characterized by: 2) A patent characterized in that the indium gallium arsenide compound semiconductor layer is provided between the third compound semiconductor layer and the indium gallium phosphide compound semiconductor layer, both of which are lattice matched to the gallium arsenide compound single crystal. A semiconductor device according to claim 1. 3) The indium gallium arsenide compound semiconductor layer and the indium gallium phosphorus compound semiconductor layer are formed on a gallium arsenide compound semiconductor substrate with a semiconductor layer that alleviates the difference in lattice constant interposed therebetween, and the indium gallium arsenide compound semiconductor layer and the indium gallium arsenide compound semiconductor layer Claim 1 characterized in that the gallium phosphide compound semiconductor layer and the gallium phosphate compound semiconductor layer are mutually lattice matched.
1. Semiconductor device described in Section 1.