JPS6320911A - Rotary channel selection system for syntehsizer receiver - Google Patents

Abstract

PURPOSE:To improve the operability by increasing/decreasing a time counting a pulse output depending on the count of the pulse output of a rotary encoder inputted to an interruption input of a microcomputer. CONSTITUTION:With a pulse from the rotary encoder 1-1 given, a counter counting a pulse output of a microcomputer 1-2 applies addition/subtraction. The preset time is measured in the step 2-5 of the main program and when the time elapses, the count subjected to addition/subtraction is read. When the count is not 0, the count is added to a present PLL data to check the frequency range and the result is outputted to a programmable frequency divider 1-3. Then the time T2 to be measured is set in the step 2-9. With the count zero given, after the time T1 to be set in the step 2-10 and the step goes to 2-5. The relation of T1<T2 exists and the time to update the PLL data is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a rotary tuning system for a synthesizer receiver in which the local oscillation circuit is a PLL synthesizer.

Conventional technology Conventionally, the rotary tuning method of a synthesizer receiver inputs the pulse output of a rotary encoder to the interrupt input of a microcomputer, counts and calculates the frequency division ratio of the programmable frequency divider that constitutes the PLL synthesizer. What to set is known.

Hereinafter, a rotary tuning system for a conventional synthesizer receiver will be described with reference to the drawings.

FIGS. 3 and 4 show the configuration of a rotary channel selection device of a conventional synthesizer receiver and a flowchart of a microcomputer program. In FIG. 3, 3-1 is a rotary encoder. 3-2 is a microcomputer, which includes a tally encoder 3.
It has the pulse output from -1 as an interrupt input, and has the normal rotation and inversion signal outputs of the rotary encoder 3-1 as input.

3-3 is a programmable frequency divider constituting the PLL synthesizer, and the frequency division ratio is set by the microcomputer 3-2. FIG. 4 is a flow chart showing the operation of the microcomputer.

The operation of the rotary tuning method of the synthesizer receiver configured as described above will be described below.

The pulse output from the rotary encoder 3-1 is input to the interrupt input of the microcomputer 3-2. In the microcomputer 3-2, as shown in the interrupt processing flow of FIG. 4A, the counter is incremented or subtracted based on the forward/reverse rotation signal inputted from the rotary encoder. On the other hand, in the main program, as shown in the main flow of FIG. 4B, time is measured, and after a predetermined time has elapsed, the value of the counter added or subtracted in the interrupt program is read, and the value of the counter is set to 0. Next, the read counter value is added to the current PLL data, a programmable frequency division ratio is set, and display data is output.

Problems to be Solved by the Invention However, in the above configuration, the time for reading the count value of the counter, setting the division ratio of the programmable frequency divider, and setting the frequency is determined by the PLL from the read count value. This is a fixed time interval that is longer than the time required to calculate the data, check the frequency range, and output the display data, so in actual use, the frequency is set after turning the rotary tuning knob. The problem was that there was a time delay until the process was completed, resulting in poor operability.

In view of the above problems, the present invention provides an a-tally tuning system for a synthesizer receiver that reduces the time delay between turning the rotary tuning knob and setting the frequency and improves operability. .

Means for Solving the Problems In order to solve the above problems, the rotary tuning system of the synthesizer receiver of the present invention uses the count value of the pulse output of the rotary encoder input to the interrupt input of the microcomputer to The present invention is characterized in that the time for counting the pulse output is increased or decreased.

According to the above-described system, if the pulse output from the rotary encoder inputted by the interrupt input of the microcomputer is not within a set fixed time interval, the counter that counts the output pulses of the rotary encoder next. By making the viewing time shorter than the time interval required by the microcomputer for calculating PLL data, checking the frequency range, and outputting display data, the frequency can be set after the rotary tuning knob is turned. This will shorten the time delay until the process is completed and improve operability.

Embodiment Hereinafter, a rotary tuning system of a synthesizer receiver according to an embodiment of the present invention will be explained with reference to the drawings. FIGS. 1 and 2 show the configuration of a rotary tuning system of a synthesizer receiver and a flowchart of a microcomputer in an embodiment of the present invention. In FIG. 1, 1-1 is a rotary encoder. 1-2
The microcomputer 1-1 has the pulse output of the rotary encoder 1-1 as an interrupt input, and has each of the normal rotation and 9 inversion signal outputs of the rotary encoder 1-1 as separate inputs. 1-3 is a programmable frequency divider constituting a PLL synthesizer, and the frequency division ratio is set by the microcomputer 1-2.

FIG. 2 is a flow chart showing the operation of the microcomputer.

The operation of the rotary tuning system of the synthesizer receiver configured as described above will be explained below with reference to FIGS. 1 and 2.

First, in FIG. 1, when a pulse is output from the rotary encoder 1-1, the microcomputer 1-2
input to the interrupt input. Microcomputer 1-2
Then, interrupt processing is performed as shown in FIG. 2A. In step 2-1, the normal rotation 9 inversion signals from the rotary encoder 1-1 are determined, and if the rotation is normal, step 2-2
A counter that counts the output pulses is incremented, and if it is reversed, the process goes to step 2-3, where the counter is decremented, and the interrupt processing is terminated and the process returns to the main program. On the other hand, in the main program, as shown in Figure 2B, steps 2-6
to measure the preset time. Step 2-
When time elapses in step 5, step 2-6 is reached;
0 to read the added/subtracted counter value in the interrupt routine
If the counter value is not 0, the process proceeds to step 2-7, where the counter value is added to the current PLL data, a frequency range check is performed, and the result is output to the programmable frequency divider.

Next, the process proceeds to step 2-8, where display data is calculated and output. Next, the process proceeds to step 2-9, and after setting the time T2 to be measured in step 2-5, the process proceeds to step 2-6. If the counter value is 0 in step 2-6, the process goes to step 2-10 and the time T to be measured in step 2-6
After setting 1, the process goes to step 2-5. Here, the time T2 in step 2-9 and the time T2 in step 2-10 have a relationship of T1<T2. In this way, when the rotary tuning knob is not turned, the counter value is read at short time intervals, and the time from turning the rotary tuning knob to changing the PLL data can be shortened. , it is possible to improve the operability in rotary channel selection. Furthermore, while the rotary tuning knob is being turned, there is time required for calculating PLL data, checking the frequency range, calculating and outputting display data, so the original operation is not affected. When you continue to turn the rotary tuning knob, the frequency changes at the same time intervals as before, but the delay between the actual operation of the rotary tuning knob and the frequency change can only be recognized at the beginning of the operation. This is not a problem.

Effects of the Invention As described above, the present invention reads out the counted value input from the rotary encoder to the interrupt input of the microcomputer and adjusts or subtracts the time interval for calculating the programmable frequency division ratio of the PLL synthesizer depending on the counted value. As a result, the time delay from when the rotary tuning knob is started to be operated until the frequency is changed can be shortened, and operability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synthesizer receiver showing an embodiment of the invention, FIG. 2 is a main and interrupt 70-chart showing the operation of a microcomputer, and FIG. 3 is a block diagram of a synthesizer receiver showing an embodiment of the invention. FIG. 4 is a block diagram showing a conventional synthesizer receiver. FIG. 4 is a main and interrupt flowchart showing the operation of a conventional microcomputer. 1-1...op relay encoder, 1-2.
...Microcomputer, 1-3...
Programmable frequency divider, 3-1... Rotary encoder, 3-2... Microcomputer, 3-3... Progerama Furire frequency divider. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 A B

Claims (1)

[Claims] The local oscillation circuit is composed of a PLL synthesizer, which has a rotary encoder and the output pulses of this rotary encoder as an interrupt input, and after counting the output pulses for a predetermined time, calculates the count value, and calculates the programmable frequency division ratio of the PLL synthesizer. The rotary selection of the synthesizer receiver is characterized in that the control means is configured to increase or decrease the time for counting output pulses from the rotary encoder according to the value of the count value. Bureau method.