JPS6318904B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention allows a plurality of stations to share one transmission path or repeater in a time-division manner, and performs burst transmission in synchronization with a time-division reference frame defined by a reference station. time division multiple access (TDMA)
That's what it means. ) communication system. For more information, see TDMA
This relates to time-division line setting technology for devices.

[Conventional technology and its problems]

One advantage of the TDMA communication system is that the time position and time length of the traffic bursts of each participating station allocated within the time division reference frame can be made variable. By providing flexibility and matching the time-division lines assigned to each station with the traffic volume of each station as much as possible, the overall transmission capacity unique to the TDMA communication system can be utilized most effectively. For this reason, variability is often required in the time division line setting function of TDMA devices.

In the case of the preassignment method, which predicts the traffic amount of participating stations and allocates each station's traffic burst within a time-division reference frame, static fluctuations in traffic are predicted and the allocation is performed periodically or temporarily. Static mutability is required to change. Conventionally, as a means for this purpose, a time-division reference frame is divided into a group of quantization unit time slots of an appropriate time length, a time slot number is assigned to each group, and a burst start or stop event within the reference frame is controlled. The occurrence time slot number is added to the control word for the event, and the event is arranged and stored in the order of occurrence. Rewritable burst-allocated memory was used. However, in a time-division communication system that accommodates a large number of stations with widely varying amounts of traffic, the reference frame time length must be set sufficiently long to allocate a large number of bursts with widely varying burst lengths. The drawback is that it requires a large memory capacity and its peripheral circuitry is complex.

In order to make the most of the overall transmission capacity of the TDMA communication system, it is desirable to dynamically allocate time division lines that match the dynamic traffic fluctuations of each participating station as much as possible. A promising method for this purpose is a demand assignment method in which a time division line is dynamically set only to the channel port where the call actually occurs. In this case, dynamic variability is required for the time-division line setup function to respond on a call-by-call basis.

Recently, with the progress of distributed processing in the field of information processing technology, the need for efficient communication networks connecting various computer terminals has increased. The data speeds of various computer terminals vary widely from slow to fast. When accommodating a group of channel ports that connect various types of terminal data with different data speeds in a TDMA communication system, time-sharing lines that match the traffic volume are allocated to each channel port in demand assignment mode. It is an important technical issue to increase the transmission efficiency of TDMA communication systems by setting this, and special measures are required to achieve this economically.

[Purpose of the invention]

The purpose of the present invention is to provide a TDMA communication system in which a large number of stations with widely varying amounts of traffic participate.
static variability required for pre-assignment methods;
Another object of the present invention is to provide a TDMA device having a time-division line setting function that economically provides the dynamic variability necessary for the demand assignment method.

Another object of the invention is to provide a group of channel ports for connecting various digital terminals having different data rates, each channel port having a time-sharing line matching its traffic in a demand assignment mode. An object of the present invention is to provide a TDMA device having a time division line setting function that can be allocated.

[Summary of the invention]

The present invention introduces a basic frame structure consisting of a plurality of time slots and a multi-frame structure consisting of a plurality of basic frames as a time division transmission format, fixes these fine structures, and simplifies the circuit. , the necessary number of time slots are selected from a group of time slots on the time slot matrix defined by the basic frame structure and the multi-frame structure according to a regular pattern to set up a time division line, and this selection pattern can be varied. This aims to provide flexibility in setting up time-division lines depending on the nature of the network.

The first feature of the present invention is that a reference station transmits a reference synchronized burst signal in order for a plurality of stations to share one transmission path or repeater in a time-division manner and communicate with each other in burst mode. In order to connect to the TDMA communication system, which defines a reference frame using this as a time reference, and further defines a super frame with multiple reference frames as a unit, the reference frame and super frame are received by receiving the reference synchronization burst signal. A TDMA synchronizer that establishes and maintains reception synchronization regarding the transmission and reception, further establishes and maintains transmission burst synchronization by correcting one-round transmission delay time between transmission and reception, and identifies reference frame and super frame start points. TDMA with multiple channel ports used in conjunction with
In the device, a reference frame is divided into a plurality of basic frames (time length T seconds), a plurality (N) of traffic time slots are provided within the basic frame, and time slot numbers 1, 2, ..., N are assigned. Transmission and reception time slot counters that identify this and are reset at the starting point of the reference frame, and a multiframe with multiple (M) basic frames as a unit are defined, and the basic frames within the multiframe are assigned frame numbers 0, 1, etc. 2,...,M-1 to identify it and reset it at the start of a superframe, and a D-bit burst data accommodating and receiving in the traffic time slot. A transmit traffic burst creation circuit for creating a transmit traffic burst by adding a preamble word for processing, and a receive traffic burst for processing the receive traffic burst and separating D-bit length burst data. and for each channel port, a transmit buffer for converting the channel port input data into burst data for accommodation in the designated transmit traffic time slot for each D bit; A receive buffer for converting the burst data of the received receive traffic time slot into channel port output data, a receive buffer that stores the line identification number specified for the channel port, and the time slot counter and multiframe counter described above. A transmission and reception time slot control circuit that specifies the traffic time slot to which the channel port should be connected by calculating and comparing the time slot number and frame number that develop on the time axis. The frame number indicated by the line identification number specified for each channel port is selected from M×N time slot groups on a time slot matrix that is a combination of a basic frame consisting of a basic frame consisting of a lot of frames and a multiframe consisting of M basic frames. Multiple (R) required according to time slot number
The purpose of this method is to select a time slot, set up a time division line, and accommodate a channel port with a transmission rate of RD/MT (bits/second).

The second feature of the present invention is that in the TDMA device having the first feature, a speed parameter P∈{divisor of M} and a frame number K∈{0, 1, 2 , . 0,1,2,...,M-1} and time slot number j∈{1,2,...,N} as the line identification number (p,
k, l) to specify the traffic time slot to which the channel port should be connected when i≡K (remainder system modulo p) and j=l. By providing it as a circuit, frame number i and time slot number j
M/p indicated by the line identification number (p, k, l) specified for the channel port from the M x N time slot group of the time slot matrix whose element is the time slot _{t i,j} identified by Select time slots {t _i,j | i≡k (coset modulo p)}, set up a time division line, and accommodate channel ports with a transmission rate of D/pT [bits/second]. It's about doing. This corresponds to the case where qM=pR in a TDMA device having the first characteristic.

A third feature of the present invention is that in a TDMA device having the first and second features, a first speed parameter p∈{divisor of M} specified as a line identification number for a channel port; q∈{1,2,...,N}, a register that stores frame number k∈{0,1,2,...,p-1} and time slot number l∈{1,2,...,N-q+1}; , the frame number i ∈ {0, 1, 2, ..., M-1} and the time slot number j ∈ {1, 2, ..., N} that the multi-frame counter and the timeslot counter expand on the time axis. The line identification number (p,
q, k, l) to specify the traffic time slot to which the channel port should be connected when i≡k (remainder system modulo p) and l≦j≦l+q−1. By providing a time slot control circuit with a time slot control circuit, frame number i and time slot number j
qM indicated by the line identification number (p, q, k, l) specified for the channel port from the M×N time slot group of the time slot matrix whose element is the time slot t _i,j identified by /p time slots {t _i,j | i≡k (coset modulo p) l≦j≦l+q−1}, set up a time division line, and set the transmission rate qD/pT to this. The purpose is to accommodate a [bit/second] channel port. This corresponds to the case where qM=pR in a TDMA device having the first characteristic.

〔Example〕

Next, the present invention will be explained in detail using the drawings.

A standard in which a reference station transmits a reference synchronized burst signal and uses this as the time reference in order for multiple stations to share one transmission path or repeater in a time-division manner and communicate with each other in burst mode. FIG. 1 shows an embodiment of a time-division transmission format of a TDMA device according to the present invention, which is applied to a TDMA communication system that defines a frame and further defines a super frame having a plurality of reference frames as units. The reference frame RF with the reference synchronization burst signal as the time standard,
Divide into multiple basic frames BF with the same structure.
Within the basic frame, there is a synchronization time slot S and N traffic time slots 1, 2,...,N.
, and the time length of the basic frame is T seconds. The reference synchronization burst signal occupies the synchronization time slot of the first basic frame within the reference frame. The traffic time slot accommodates a unit traffic burst in which a preamble word PW for reception processing is added to D-bit length data DT. Thus, a time division line using one traffic time slot per basic frame has a transmission rate of D/T (bits per second). For example, if D=1024 and T=2 [milliseconds], the transmission speed will be 512 kilobits/second.

Next, let M be an appropriate divisor of the total number of basic frames in a super frame period in which a plurality of reference frames defined by the reference synchronization burst signal are a unit, and a multi-frame MF in which M basic frames are a unit.
is introduced, and frame numbers 0, 1, 2, . . . , M-1 are assigned to the basic frames within this multiframe.

The starting point of the multiframe can be identified by setting the frame number of the basic frame containing the reference synchronization burst signal indicating the starting point of the superframe as "0."

FIG. 2 shows a time slot matrix obtained by arranging M basic frames containing N traffic time slots in order of frame number. This means that the time slot t i,j identified by the frame number i∈{0,1,2,...,M-1} and the time slot number j∈{1,2,...,N} is ( _i ,
j) Defined as a matrix with elements, M×
Contains N time slots.

Next, a selection pattern for selecting R time slots from M×N time slots in a time slot matrix and setting up a time division line with a transmission rate of RD/MT (bits/second) will be explained.

Let p be one of the divisors of the number M of basic frames included in a multi-frame. Specify the speed parameter p∈{divisor of M}, the frame number k∈{0, 1, ..., p-1} and the time slot number l∈{1, 2, ..., N} as the line identification number. M/p time slots, i.e. {t _i,j | i=k, k+p, k+2p, ..., k+
M-p} can be selected to set a time-division line with a transmission rate of D/pT (bits/second). This M/
The p time slots can also be expressed as {t _i,j | i≡k (remainder system modulo p)}, and are determined by specifying parameters k, p, and l. Therefore, this time division line is identified by a line identification number (k, p, l). For example, if M = 32, N = 16, D = 1024, T = 2 [milliseconds], then p∈{1, 2, 4, 8, 16, 32} k∈{0, 1, 2, ..., p- 1} l∈{1, 2,..., 16}. Since the transmission speed 512/p [kilobits/second] corresponds to the speed parameter p, a transmission speed series of 512, 256, 128, 64, 32, and 16 [kilobits/second] is obtained.

For example, the line identification number (8, k, l) can be used to identify either the 32 x 16 time slots included in the time slot matrix or the 4 time slots {t _i,j | i=k, k+8, k+16, k+24}. Compatible with 64 [kilobits/second] time-division lines that can be selected and used. In this case, since p=8, kε{0, 1, 2, .

Next, a double speed parameter q∈{1, 2, ..., N-q} is introduced. To distinguish from this, the speed parameter p will be referred to as the minute speed parameter. Mq/p by specifying speed parameters p and q as line identification numbers, frame number k∈{0,1,2,...,p-1}, and time slot number l∈{1,2,...,N-q+1} time slots, i.e. {t _i,j | i=k, k+p, k+2p, ..., k+M
-p;j=l,l+1,l+2,...,l+q-
1} can be selected to set up a time-division line with a transmission rate of qD/pT [bits/second]. This Mq/p
The number of time slots is {t _i,j | i≡k (coset modulo p), l≦j≦
l+q-1}, and is determined by specifying parameters p, q, k, and l. Therefore, this time division line is identified by a line identification number (p, q, k, l). For example, if M = 32, N = 16, D = 1024, T = 2 [milliseconds], then p∈{1, 2, 4, 8, 16, 32} q∈{1, 2,..., 16} k ∈{0,1,2,...,p-1} l∈{1,2,...,16-(q-1)}. Since the transmission rate 16×(32/p)q [kilobits/second] corresponds to the speed parameter ratio q/p, a transmission rate series of integral multiples of 16 [kilobits/second] is obtained. For example, p=8,q
=3, a time-division line with a transmission rate of 192 [kilobits/second] is obtained.

In this case, the line identification number (8, 3, k, l) selects 3 x 4 time slots {t _i,j | i=k, k+8, k+16, k+24; j=l, l+1, l+2}. Compatible with time-division lines used in However, k∈{0,1,2,...,7} l∈{1,2,3,...,14}. Next, by setting p=1 and q=3, a time division line with a transmission rate of 1536 [kilobits/second] is obtained. In this case, the line identification numbers (1, 3, 0, l) are used by selecting three time slots {t _i,j , t _i,j+1 , t _i,j+2 } for each basic frame. Compatible with time division lines.

As mentioned above, the essential elements for setting up a time-division line by selecting the number of time slots determined by the speed series for each channel port from the M x N time slots on the time slot matrix. 1. Means for dividing a reference frame into a plurality of basic frames, providing N traffic time slots in the basic frame, and identifying the time slot numbers; 2. Means for dividing M basic frames into a super frame as a unit. A means for providing a plurality of multi-frames and identifying the frame number of each basic frame within the multi-frame;・Means for identifying the time slot; 4. A transmission buffer that accumulates and stores the channel port input, reads the D bit data each time an online time slot occurs, and inserts it into the traffic time slot; and a means for identifying the time slot. To traffic
Channel buffer means includes a receiving buffer that accumulates and stores D-bit data of a time slot, continuously reads the data, and outputs the data to a channel port.

In a TDMA device equipped with a plurality of channel ports that is used in combination with the TDMA synchronization control device to connect to the TDMA communication system described above, time-division transmission is performed for each channel port according to the time-division transmission format described above. Embodiments of the present invention that are embodied by including the above-mentioned element means for setting up a line will be described with reference to the drawings.

The configuration of this embodiment is shown in FIG.

The transmission time slot counter 11 is
Symbol clock 10 from TDMA synchronizer
3 as the counting input and transmission reference frame starting point pulse 1
04 as a reset input, and has the following functions. That is, the reference frame is divided into a plurality of basic frames, N traffic time slots are provided in the basic frame, the time slot numbers j∈{1, 2, ..., N} are identified, and the starting point of the transmission basic frame is determined. A pulse 111 and a transmission traffic time slot start point pulse 112 are output, and a transmission time slot number identification code 113 is expanded on the time axis. The transmission multiframe counter 12 uses the transmission basic frame starting point pulse 111 as a counting input, and uses the TDMA
Transmission super frame start point pulse 1 from the synchronous controller
05 as a reset input, and has the following functions. That is, a plurality of multiframes each having M basic frames as units are provided in a superframe, and the frame number i∈{0, 1, 2, ..., M-1} of the basic frame in the multiframe is identified and transmitted. The frame number identification code 114 is developed on the time axis. The transmission time slot control circuit 13 decodes the line identification number stored in the register that stores the line identification number 102 designated for the transmission channel port 101, and reads the time slot number identification code 113 and the time slot number identification code 113 according to the regular pattern instructed by the line identification number. From the M×N time slots identified by the frame number identification code 114, the online
Equipped with an arithmetic comparator for selecting a time slot,
Online time slot gate signal 115
Output.

The transmission burst creation circuit 14
In response to the time slot start point pulse 112, a read clock 116 of D bit length is created. The transmission channel buffer 15 is connected to the channel port 10.
The input data from 1 to 1 is accumulated and stored, and is read out successively by a read clock 116 at a time slot specified by an online time slot gate signal 115 to output burst data 117.

The transmission burst creation circuit 14 creates a preamble word based on the traffic time slot start point pulse 112 at the time slot designated by the online time slot gate signal 115, and adds burst data read from the transmission channel buffer to this preamble word. 117 to create a transmit traffic burst 106.

Reception time slot counter 21 is TDMA
This counter uses the symbol clock 203 from the synchronizer as a counting input and the received reference frame starting point pulse 204 as a reset input. It has the same function as the transmitting time slot counter 11, and has the same function as the receiving basic frame starting point pulse 211 and the receiving traffic timestamp. It outputs the slot start point pulse 212 and also outputs the reception time slot number identification code 21.
3 on the time axis. Receive multi-frame
The counter 22 receives the received basic frame starting point pulse 2.
11 as the counting input and the received super frame start point pulse 205 from the TDMA synchronization control device as the reset input. It has the same function as the transmitting multiframe counter 12, and expands the received frame number identification code 214 on the time axis. do. Like the transmission time slot control circuit 13, the reception time slot control circuit 23 includes a register and an arithmetic comparator, stores the line identification number 202 specified in the reception channel port 201, and stores the reception time slot number identification code 213 and the reception frame. The online time slot to be connected to the channel port is selected from the M×N time slots identified by the number identification code 214, and a received online time slot gate signal 215 is output. The reception burst processing circuit 24 receives the traffic time slot start point pulse 212 and outputs D.
A bit-length write clock 216 is created and the received burst signal extracted from the received burst signal 206 is generated.
It is output to the reception channel buffer 25 along with the data 217. The receive channel buffer 25 receives the online time slot gate signal 215.
write clock 21 at the time slot specified by
6 is used to accumulate and store received burst data 217, which is continuously read out and output to the receive channel port 201 as received data.

A transmit and receive channel buffer and a transmit and receive time slot control circuit are provided for each channel port. Although a configuration accommodating one channel port is shown in FIG. 3, by providing a plurality of the above-mentioned means provided for each channel port and adding a simple combining or distributing means, it is possible to accommodate a plurality of channels. Easily expandable to accommodate ports.

Next, an embodiment of the time division line setting means according to the present invention, that is, the time slot control circuit shown in FIG. 3 will be described in more detail.

The first embodiment of the time slot control circuit is described in the fourth embodiment.
As shown in the figure. This is the identification number for the time division line.
Minute speed parameter p, frame number parameter k
This is for setting a time division line with a transmission rate of D/pT (bits/second) by specifying a line identification number (p, k, l) consisting of a time slot number parameter l and a time slot number parameter l. Line identification numbers (p, k,
l) in registers 41, 43 and 31. The register 41 is a minute speed register that stores the minute speed parameter p∈{divisor of M}, which is connected to the signal line 34.
Output to 1. The register 43 is a frame number register that stores frame number parameters k∈{0, 1, 2, . . . , p−1}, and outputs this to the signal line 343. The register 31 is a time slot number register that stores a time slot number lε{1, 2, . . . , N}, and outputs this to a signal line 331. The counter 42 is a modulo M counter with an initial value of 0 and an increment unit of p, and increments the output 342 by p every time the counter up input 345 becomes logic "1". Therefore, the counter output is expressed as np nε{0, 1, . . . , (M/p-1)}. The adder 44 outputs the frame number k stored in the frame number register 43 and the counter output.
np is added, and the result, ie, k+np, is output to the signal line 344.

The frame number comparator 45 inputs a frame number identification code input 314 between the frame number i∈{0,1,2,...,M−1} expanded on the time axis and the output k+np, n∈ of the adder 44. {0, 1, .
The time slot comparator 32 inputs the time slot number identification code input 313 by inputting the time slot number j∈{1,2,...,N} expanded on the time axis and the time slot number l stored in the time slot number register. are compared, and when they match, the output 332 is set to logic "1". and gate 46
ANDs the frame number comparator output 345 and the timeslot number comparator output 332 and outputs it as the online timeslot gate signal 315. Therefore, i=k+np; n=0, 1, 2,..., M/p-
1, that is, i≡k (coset modulo p) and i=l, the online timeslot gate is "on" and specifies the online timeslot to which the channel port is to be connected. Thus, by specifying the line identification numbers (k, p, l), M×N time slot matrices whose elements are the time slots t _i,j identified by the frame number i and the time slot number j. From the time slots of Can be set.

Next, a second embodiment of the time slot control circuit is shown in FIG. This is done by specifying the line identification number (p, q, k, l) consisting of the minute speed parameter p, double speed parameter q, frame number parameter k, and time slot number parameter l, and then setting the transmission speed qD/pT [bits/second]. It is used to set up a time-division line, and includes registers and arithmetic comparison means related to the minute speed parameter p and frame number parameter k shown in the first embodiment, and the double speed parameter q and time slot number l. It is a combination of registers and arithmetic comparison means. In FIG. 5, line identification numbers (p, q, k,
1), the minute speed parameter p and frame number k are stored in the first register and calculation comparison means 1.
, and the double speed parameter q and time slot number l are specified to the second register and the arithmetic comparison means 2. The first register and arithmetic comparison means 1 are the same as the registers and arithmetic comparison means related to the minute speed parameter p and frame number k in the first embodiment shown in FIG. Expanded frame number i∈{0,1,2,...,M-1}, minute rate parameter p∈{divisor of M} and frame number parameter k∈{0,1,2,...,p-1 } and when i≡k (remainder system modulo p), the output 345 is set to logic "1".

The second register and arithmetic comparison means 2 input the time slot number j∈{1,2,...,N} expanded to the time slot number identification code input 313 and the double speed parameter q∈{1,2,...,N } and the time slot number parameter l∈{1,2,...,N-q+1}, and when j=l, l+1, l+2,..., l+q-1, the output 354 is set to logic "1". It is something.

This second register and arithmetic comparison means 2 are
The line identification number (q,l) given to write input 302 is stored in registers 51 and 31.
Register 51 is a double speed register that stores double speed parameters q∈{1,2,...,N}, and register 31
is a time slot number register that stores time slot number parameters l∈{1, 2, ..., N-q+1},
The adder 52 adds the double speed parameter q and the time slot number parameter l, and the result is l+q
Output. Comparators 32 and 53 compare the time slot number jε{1, 2, . Comparator 32 outputs a logic ``1'' when j=l, setting flip-flop 54. Comparator 53 outputs a logic "1" when j=l+q and resets flip-flop 54.

As a result, j=l, l+1, l+2,..., l+q-1 When , the output 354 is set to logic "1".

The AND gate 46 calculates the logical product of the outputs of the first and second registers and the arithmetic comparison means and outputs the online time slot gate signal 315.
Output. Therefore, when i≡k (residue system modulo p) and l≦j≦l+q−1, the online time slot gate signal is “on” and the online time slot to which the channel port should be connected is It is specified. Thus, by specifying the line identification number (p, q, k, l), the time slot identified by the frame number identification code i and the time slot identification code j is
M of the time slot matrix whose elements are t _i,j
It is possible to select Mq/p online time slots satisfying the above relationship from ×N time slots and set up a time division line with a transmission rate of qD/pT (bits/second).

〔Effect of the invention〕

As is clear from the above explanation, by using the present invention, static variability required in the case of the pre-assignment method can be achieved in a TDMA communication system in which a large number of stations with widely varying traffic volumes participate. Alternatively, it is possible to realize a time-division line setting function that economically provides the dynamic variability required in the case of the demand assignment method. Furthermore, it is a time-division line that is equipped with a group of channel ports for connecting various types of terminal data with different information speeds, and can set up a time-division line that matches the traffic in demand assignment mode for each channel port. It is possible to provide a TDMA device with a setting function, making it possible to most effectively utilize the comprehensive transmission capacity of the TDMA communication system.

The concept of the invention is not limited to the embodiments described herein, but can be applied in various ways by those skilled in the art.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a time division transmission format of a TDMA device according to the present invention. FIG. 2 is a diagram showing a time slot matrix defined in the above embodiment. FIG. 3 is a diagram showing the configuration of an embodiment of a TDMA device according to the present invention. 4 and 5 are diagrams showing first and second embodiments of the time slot control circuit in FIG. 3, respectively.

Claims (1)

[Claims] 1. In order for a plurality of stations to share one transmission path in a time division manner and communicate with each other in burst mode,
A reference station among the stations transmits a reference synchronization burst signal, defines a reference frame using this as a time reference, defines a super frame with multiple reference frames as a unit, and the multiple stations transmit the reference synchronization burst signal. The burst signal is received to establish and maintain reception synchronization regarding the reference frame and super frame, and furthermore, the transmission burst synchronization is established by correcting the one-round transmission delay time between the transmitting station and the receiving station, and this is maintained. A time division multiple access communication system configured to maintain and identify a reference frame start point and a super frame start point, and having a plurality of channel ports used in conjunction with a time division multiple access synchronizer. In the device, a reference frame is divided into a plurality of basic frames each having a time length of T seconds, a plurality of (N) traffic time slots are provided in the basic frame, and time slot numbers 1, 2, ..., N are assigned. Transmission and reception time slot counters 11 and 21 that are reset at the starting point of the reference frame, and a multiframe with multiple (M) basic frames as units are defined, and basic frames within the multiframe are Transmit and receive multiframe counters 12, 22 are assigned frame numbers 0, 1, 2, ..., M-1 to identify them, and are reset at the start of a superframe, and a D bit length in the traffic time slot. a transmission traffic burst creation circuit 14 for accommodating the burst data and adding a preamble word for reception processing to create a transmission traffic burst, and processing the reception traffic burst to create a transmission traffic burst of D bit length. and a receive traffic burst processing circuit 24 for separating the burst data of each channel port, and further includes a receive traffic burst processing circuit 24 for separating the burst data of each channel port, and further includes a receive traffic burst processing circuit 24 for accommodating the channel port input data into a transmit traffic time slot designated for each D bit. A transmission buffer 15 for converting the burst data into burst data, a reception buffer 25 for converting the burst data of the specified reception traffic time slot into channel port output data, and a line identification number specified for the channel port. Transmission and reception that specifies the traffic time slot to which the channel port should be connected by calculating and comparing the memorized time slot number and frame number developed on the time axis by the time slot counter and multiframe counter. The transmission and reception time slot control circuits are equipped with time slot control circuits 13 and 23, and the transmission and reception time slot control circuits have a time slot control circuit that combines a basic frame consisting of N traffic time slots and a multiframe consisting of M basic frames. From a group of M×N time slots on the matrix,
According to the frame number and time slot number indicated by the line identification number specified for each channel port, select multiple (R) required time slots, set up a time division line, and set the transmission rate RD/ A time division multiple access device, characterized in that it includes means for controlling to accommodate a channel port of MT (bits per second). 2 Speed parameter specified as line identification number in channel port p∈{divisor of M} Frame number k∈{0,1,2,...,p-1} and time slot number l∈{1,2,... , N} and the multi-frame
The frame number i ∈ {0, 1, 2, ..., M-1} and the time slot number j ∈ {1, 2, ..., N} that the counter and time slot counter develop on the time axis are stored in the register. line identification number (p,
k, l), and specifies the traffic time slot to which the channel port should be connected when i≡k (remainder system modulo p) and j=l. The circuit is provided as a control circuit and identifies the line specified for the channel port from a group of M×N time slots in a time slot matrix whose elements are time slots t _i,j identified by frame number i and time slot number j. Number (p,
M/p time slots {t _i,j ｜ i≡k (coset modulo p)} are selected and a time-division line is set up, and the transmission rate D/pT is set on this. The time division multiple access device according to claim 1, characterized in that it is configured to accommodate a channel port of [bits/second]. 3 First speed parameter specified as a line identification number for the channel port p∈{Divisor of M} Second speed parameter q∈{1,2,...,N} Frame number k∈{0,1, 2,...,p-1} and a time slot number l∈{1,2,...,N-q+1}, and a frame number that the multi-frame counter and the time slot counter develop on the time axis. i∈{0,1,2,...,M-1} and time slot number j∈{1,2,...,N} are the line identification numbers (p,
q, k, l) to specify the traffic time slot to which the channel port should be connected when i≡k (remainder system modulo p) and l≦j≦l+q−1. A time slot controller is provided as a time slot control circuit, and a channel port is designated from a group of M×N time slots in a time slot matrix whose elements are time slots t _i,j identified by frame number i and time slot number j. The line identification number (p,
qM _/ p time slots indicated by 3. The time division multiple access device according to claim 1 or 2, characterized in that the time division multiple access device is configured to accommodate a channel port having a transmission rate of qD/pT (bits/second).