JPS63185015A - Forming method for semiconductor thin film - Google Patents
Forming method for semiconductor thin filmInfo
- Publication number
- JPS63185015A JPS63185015A JP1669687A JP1669687A JPS63185015A JP S63185015 A JPS63185015 A JP S63185015A JP 1669687 A JP1669687 A JP 1669687A JP 1669687 A JP1669687 A JP 1669687A JP S63185015 A JPS63185015 A JP S63185015A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- phosphorus
- semiconductor thin
- ions
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims description 13
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 34
- 239000011574 phosphorus Substances 0.000 claims abstract description 34
- -1 phosphorus ions Chemical class 0.000 claims abstract description 24
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims description 12
- 239000013078 crystal Substances 0.000 abstract description 18
- 239000010408 film Substances 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 description 24
- 239000010703 silicon Substances 0.000 description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は所謂再結晶法による半導体薄膜の形成方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a semiconductor thin film by a so-called recrystallization method.
本発明は所謂再結晶法による半導体薄膜の形成方法であ
って、絶縁物上に非晶質半導体i膜を形成した後、この
非晶質半導体薄膜の表面領域にリン又はリン・イオンを
導入し、続いて熱処理を行い、その後、リン又はリン・
イオン含有層を除去する様にしたことにより、絶縁物上
に、粒径の大、きい、且つ粒径にバラツキのない結晶粒
を有する結晶性の良好な半導体薄膜を形成できる様にし
たものである。The present invention is a method for forming a semiconductor thin film by a so-called recrystallization method, in which an amorphous semiconductor i-film is formed on an insulator, and then phosphorus or phosphorus ions are introduced into the surface region of this amorphous semiconductor thin film. , followed by heat treatment, and then phosphorus or phosphorus.
By removing the ion-containing layer, it is possible to form a semiconductor thin film with good crystallinity on the insulator, which has crystal grains that are large, large, and have uniform grain size. be.
従来、絶縁物上にシリコン薄膜を形成する場合、その一
方法として、絶縁物上に多結晶シリコン薄膜を形成した
後、この多結晶シリコン薄膜にシリコン・イオンSi+
をイオン注入し、この多結晶シリコン薄膜を非晶質シリ
コンM膜となし、続いて熱処理を行うという方法が採ら
れていた。Conventionally, when forming a silicon thin film on an insulator, one method is to form a polycrystalline silicon thin film on the insulator and then inject silicon ions and Si+ into this polycrystalline silicon thin film.
A method has been adopted in which ions are implanted, the polycrystalline silicon thin film is made into an amorphous silicon M film, and then heat treatment is performed.
しかしながら、斯る従来のシリコン薄膜の形成方法にお
いては、シリコン結晶粒の粒径を均一化できず、しかも
1μ!11〜5μm程度の大きさにしか成長させること
ができず、結晶性の良好なシリコン薄膜とすることがで
きないという不都合があった。However, in such conventional methods of forming silicon thin films, it is not possible to make the grain size of silicon crystal grains uniform, and moreover, it is not possible to make the grain size of silicon crystal grains uniform! There was a disadvantage that it could only be grown to a size of about 11 to 5 μm, and a silicon thin film with good crystallinity could not be obtained.
因みに、斯るシリコン薄膜においては、結晶粒が小さい
ため、大きい移動度を有するMOS FETを形成する
ことができないという不都合があると共に結晶粒の粒径
にバラツキがあるため、MOS FETを集積化した場
合には、各?IO5FETのチャンネル領域における結
晶粒界の数にバラツキが生じてしまい、このため、集積
化したMOS FfETの特性にバラツキが生じてしま
うという不都合があった。Incidentally, in such a silicon thin film, since the crystal grains are small, it is not possible to form a MOS FET with high mobility, and the grain size of the crystal grains varies, so it is difficult to integrate the MOS FET. In each case? There is a problem in that the number of grain boundaries in the channel region of the IO5FET varies, which causes variations in the characteristics of the integrated MOS FfET.
本発明は、斯る点に鑑み、粒径が大きく、且つ粒径にバ
ラツキのない結晶粒を有する結晶性の良好な半導体薄膜
を形成できる様にした半導体薄膜の形成方法を提供する
ことを目的とする。In view of the above, an object of the present invention is to provide a method for forming a semiconductor thin film that is capable of forming a semiconductor thin film with good crystallinity and having crystal grains having large grain sizes and uniform grain sizes. shall be.
本発明に依る半導体i膜の形成方法は、例えば第1図〜
第6図に示す様に、絶縁物(1)上に非晶質半導体′a
膜(2)を形成した後、この非晶質半導体薄膜(2)の
表面領域にリンP又はリン・イオンP+を導入し、続い
て熱処理を行い、その後、リンP又はリン・イオンP+
含有層(3)を除去する様にしたものである。The method for forming a semiconductor i-film according to the present invention is illustrated in, for example, FIGS.
As shown in Figure 6, an amorphous semiconductor 'a' is formed on the insulator (1).
After forming the film (2), phosphorus P or phosphorus ions P+ is introduced into the surface region of this amorphous semiconductor thin film (2), followed by heat treatment, and then phosphorus P or phosphorus ions P+ is introduced into the surface region of the amorphous semiconductor thin film (2).
The content layer (3) is removed.
斯る本発明においては、リンP又はリン・イオンP+を
中心とした核が先行して発生し、この核を中心として結
晶粒(4)・・・(4)が成長する。この場合、横方向
への成長が速く起こるが、深さ方向にも成長するので、
結果的に粒径の大きい結晶粒(4)・・・(4)が成長
し、結晶性の良好な半導体薄膜(5)が得られる。In the present invention, a nucleus centered on phosphorus P or phosphorus ion P+ is generated in advance, and crystal grains (4) (4) grow around this nucleus. In this case, growth occurs quickly in the lateral direction, but it also grows in the depth direction, so
As a result, crystal grains (4)...(4) with large grain sizes grow, and a semiconductor thin film (5) with good crystallinity is obtained.
以下、第1図〜第6図を参照して、本発明半導体薄膜の
形成方法の一実施例につき、シリコン薄膜を形成する場
合を例にして説明しよう。Hereinafter, with reference to FIGS. 1 to 6, one embodiment of the method for forming a semiconductor thin film of the present invention will be described, taking as an example the case of forming a silicon thin film.
本例においては、先ず第1図に示す様に、絶縁物である
石英ガラス基板(1)を用意し、この石英ガラス基板(
1)上に膜厚を800人とする多結晶シリコン薄膜(6
)を例えばCVDによって形成する。In this example, as shown in FIG. 1, first, a quartz glass substrate (1) which is an insulator is prepared,
1) Polycrystalline silicon thin film with a film thickness of 800 nm (6
) is formed, for example, by CVD.
次に第2図に示す様に、この多結晶シリコン薄115
(61にシリコン・イオンSt”を例えば5 X 10
151固/cd、4QKeVの条件の下に打ち込み、こ
の多結晶シリコン薄HfA(6)を非晶質シリコン薄膜
(2)となす様にする。Next, as shown in FIG.
(For example, add silicon ion St" to 61, 5 x 10
The polycrystalline silicon thin HfA (6) is formed into an amorphous silicon thin film (2) by implantation under the conditions of 151 solids/cd and 4QKeV.
次に第3図に示す様に、非晶質シリコン薄膜(2)にリ
ン・イオンP+を例えば5 X 10”個/cni、4
0KeVの条件の下に打ち込み、非晶質シリコン薄膜(
2)の表面側にリン・イオンP+を含有する領域(3)
を形成する。Next, as shown in FIG. 3, phosphorus ions P+ are added to the amorphous silicon thin film (2) at a rate of, for example, 5 x 10"/cni, 4
It was implanted under 0 KeV conditions to form an amorphous silicon thin film (
Region (3) containing phosphorus ions P+ on the surface side of 2)
form.
次にN2雰囲気中、600℃の下で熱処理を進行させる
。この様にすると、熱処理開始後4時間以内にリン・イ
オンP+を中心とする核が発生し、第4図に示す様に、
この核を中心としてシリコン結晶粒(4)・・・(4)
が成長する様になる。この場合、この核は第7図に実線
Xで示す様な速度で成長する。Next, heat treatment is performed at 600° C. in an N2 atmosphere. In this way, a nucleus centered on phosphorus ions P+ is generated within 4 hours after the start of heat treatment, and as shown in Fig. 4,
Silicon crystal grains (4)...(4) center around this core.
begins to grow. In this case, this nucleus grows at a rate as shown by the solid line X in FIG.
またこの場合、横方向への成長が速く起こるが、深さ方
向にも成長する。Also, in this case, growth occurs quickly in the lateral direction, but also in the depth direction.
そこで更に熱処理を進行させると、熱処理開始t&10
時間を過ぎる頃からシリコン・イオンSi+を中心とす
る核が発生し始めるが、この時には、リン・イオンP+
を中心とするシリコン結晶粒(4)・・・(4)はかな
りの大きさになっており、しかも、このす〉′・イオン
P+を中心とするシリコン結晶粒(4)・・・(4)の
成長速度は、シリコン・イオンSi+を中心とするシリ
コン結晶粒の成長速度(第7図に破線Yで示す。)より
も早いので、最終的には、即ち約20時間後には第5図
に示す様にリン・イオンP+を中心とする結晶粒(4)
・・・(4)をその粒径が約15μm含有層(3)をエ
ツチングにより除去する。Then, when the heat treatment is further progressed, the heat treatment starts at t&10.
As time passes, nuclei centered around silicon ions, Si+, begin to form, but at this time, phosphorus ions, P+
The silicon crystal grains (4)...(4) centered on the ions are quite large, and the silicon crystal grains (4)...(4) centered on the ions P+ are quite large. ) is faster than the growth rate of silicon crystal grains centered on silicon ions (Si+) (indicated by the broken line Y in FIG. 7). As shown in the figure, crystal grains centered on phosphorus ions P+ (4)
...The layer (3) containing (4) having a particle size of about 15 μm is removed by etching.
この様に本実施例に依れば、その粒径を従来例に依る場
合に比し大とする、例えば約15μmとする結晶粒(4
)・・・(4)を有する結晶性の良好なシリコンi 1
1Q +5>を形成することができる。従って、斯るシ
リコン薄膜(5)に例えばMOS FETを形成する場
合には、このMOS FITを高移動度のものとするこ
とができると共に、また本例のシリコン薄膜(5)は凹
凸が少ないので斯るシリコン薄膜(5)をゲート電極と
して用いる場合には、多結晶シリコンによりゲート電極
を形成する場合に比しゲート酸化膜を薄くすることがで
きるという利益がある。As described above, according to this embodiment, the crystal grain size is larger than that of the conventional example, for example, about 15 μm (4
)...(4) Silicon i 1 with good crystallinity
1Q +5> can be formed. Therefore, when forming, for example, a MOS FET on such a silicon thin film (5), this MOS FIT can be made to have high mobility, and the silicon thin film (5) of this example has few irregularities. When such a silicon thin film (5) is used as a gate electrode, there is an advantage that the gate oxide film can be made thinner than when the gate electrode is formed of polycrystalline silicon.
また本実施例に依れば、熱処理開始後4時間以内に成長
速度の早いリン・イオンP+を中心とする核を発生させ
ることができるので、熱処理時間を短縮することができ
るという利益がある。Furthermore, according to this embodiment, it is possible to generate nuclei centered on phosphorus ions P+, which grow rapidly, within 4 hours after the start of the heat treatment, so there is an advantage that the heat treatment time can be shortened.
尚、上述実施例においては、石英ガラス基板(1)上に
シリコン薄膜を形成する場合につき述べたが、本発明は
この上述実施例に限らず、s i(h ffi等種々の
絶縁物上にシリコン薄膜を形成する場合にも通用でき、
この場合にも、上述同様の作用効果を得ることができる
。In the above embodiment, a case was described in which a silicon thin film was formed on a quartz glass substrate (1), but the present invention is not limited to this embodiment. It can also be used to form silicon thin films.
In this case as well, the same effects as described above can be obtained.
また上述実施例においてはリン・イオンP+を非晶質シ
リコン薄III (21にイオン注入した場合につき述
べたが、この代わりに、リンPを拡散させる様にしても
良く、この場合にも上述同様の作用効果を得ることがで
きる。Furthermore, in the above embodiment, the case where phosphorus ions P+ were implanted into the amorphous silicon thin layer III (21) was described, but instead of this, phosphorus P may be diffused, and in this case, the same applies as above. It is possible to obtain the following effects.
また本発明は、上述実施例に限らず、本発明の要旨を逸
脱することなく、その他種々の構成が取り得ることは勿
論である。Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and can take various other configurations without departing from the gist of the present invention.
本発明に依れば、非晶質半導体薄膜の表面側にリン又は
リン・イオンを導入し、その後、熱処理を行う様にして
いるので、粒径の大きい結晶粒を有する結晶性の良好な
半導体薄膜を形成できるという利益がある。According to the present invention, phosphorus or phosphorus ions are introduced into the surface side of an amorphous semiconductor thin film, and then heat treatment is performed. It has the advantage of being able to form thin films.
また本発明に依れば、リン・イオンを中心とした核を発
生せしめ、これを成長させる様にしているので、従来例
に比し、熱処理時間を短縮できるという利益がある。Further, according to the present invention, since a nucleus mainly composed of phosphorus ions is generated and grown, there is an advantage that the heat treatment time can be shortened compared to the conventional example.
第1図、第2図、第3図、第4図、第5図及び第6図は
夫々本発明半導体薄膜の形成方法の一実施例を示す工程
図、第7図はシリコン結晶粒の成長速度を示す線図であ
る。
(1)は石英ガラス基板、(2)は非晶質シリコン薄膜
、(3)はリン・イオン含有層、(4)はシリコン結晶
粒、(5)はシリコン薄膜、(6)は多結晶シリコン薄
膜である。
第3図
第4図
一実)色イJIJめ工JLtJ
第5図
−賞 J4邑イJ1 の 工JLr5り第B図1, 2, 3, 4, 5, and 6 are process diagrams showing one embodiment of the method for forming a semiconductor thin film of the present invention, and FIG. 7 is a growth diagram of silicon crystal grains. It is a diagram showing speed. (1) is a quartz glass substrate, (2) is an amorphous silicon thin film, (3) is a phosphorus ion-containing layer, (4) is a silicon crystal grain, (5) is a silicon thin film, and (6) is polycrystalline silicon. It is a thin film. Fig. 3 Fig. 4 Ichiji) Color A JIJ Meko JLtJ Fig. 5 - Prize J4 Eup I J1's Work JLr5ri Fig. B
Claims (1)
導体薄膜の表面領域にリン又はリン・イオンを導入し、
続いて熱処理を行い、その後、リン又はリン・イオン含
有層を除去する様にしたことを特徴とする半導体薄膜の
形成方法。After forming an amorphous semiconductor thin film on an insulator, introducing phosphorus or phosphorus ions into the surface region of the amorphous semiconductor thin film,
A method for forming a semiconductor thin film, characterized in that a heat treatment is then performed, and then the phosphorus or phosphorus ion-containing layer is removed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1669687A JPS63185015A (en) | 1987-01-27 | 1987-01-27 | Forming method for semiconductor thin film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1669687A JPS63185015A (en) | 1987-01-27 | 1987-01-27 | Forming method for semiconductor thin film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63185015A true JPS63185015A (en) | 1988-07-30 |
Family
ID=11923458
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1669687A Pending JPS63185015A (en) | 1987-01-27 | 1987-01-27 | Forming method for semiconductor thin film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63185015A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0294625A (en) * | 1988-09-30 | 1990-04-05 | Sanyo Electric Co Ltd | Polycrystalline silicon film, formation of same film, and photovoltaic device using same film |
US5318919A (en) * | 1990-07-31 | 1994-06-07 | Sanyo Electric Co., Ltd. | Manufacturing method of thin film transistor |
-
1987
- 1987-01-27 JP JP1669687A patent/JPS63185015A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0294625A (en) * | 1988-09-30 | 1990-04-05 | Sanyo Electric Co Ltd | Polycrystalline silicon film, formation of same film, and photovoltaic device using same film |
US5318919A (en) * | 1990-07-31 | 1994-06-07 | Sanyo Electric Co., Ltd. | Manufacturing method of thin film transistor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR930000310B1 (en) | Manufacturing method of semiconductor device | |
JPS63185015A (en) | Forming method for semiconductor thin film | |
JPS58103124A (en) | Manufacture of semiconductor device | |
JPH0252419A (en) | Manufacture of semiconductor substrate | |
JPS63185016A (en) | Forming method for semiconductor thin film | |
JPS63142822A (en) | Manufacture of semiconductor device | |
JPS61127117A (en) | Method for forming polycrystalline semiconductor thin film | |
JPS5856408A (en) | Method of growing single crystal silicon film | |
JPS5982717A (en) | Manufacture of semiconductor device | |
JPH0254538A (en) | Manufacture of p-channel thin film transistor | |
JPH02143414A (en) | Formation of single crystal film | |
JPS60164316A (en) | Formation of semiconductor thin film | |
JPH03293718A (en) | Processing method for silicon single crystalline substrate | |
JPH04286111A (en) | Manufacture of polycrystal silicon thin film | |
JPS62273739A (en) | Manufacture of semiconductor substrate | |
JPS60176241A (en) | Manufacture of semiconductor substrate | |
JPH06236894A (en) | Manufacture of thin film transistor | |
JPH0547660A (en) | Solid growth method for semiconductor thin film | |
JPH0396223A (en) | Forming method for soi structure | |
JPS5856407A (en) | Method of growing single crystal silicon film | |
JP2833878B2 (en) | Method of forming semiconductor thin film | |
JPS62124731A (en) | Heat treatment method of semiconductor thin-film | |
JPH04196311A (en) | Manufacture of semiconductor device | |
JPS62166531A (en) | Manufacture of epitaxial wafer | |
JPH02208940A (en) | Manufacture of semiconductor device |