JPS63161678A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPS63161678A JPS63161678A JP31136586A JP31136586A JPS63161678A JP S63161678 A JPS63161678 A JP S63161678A JP 31136586 A JP31136586 A JP 31136586A JP 31136586 A JP31136586 A JP 31136586A JP S63161678 A JPS63161678 A JP S63161678A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- layers
- gaas
- type
- nondoped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 9
- 230000004888 barrier function Effects 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 230000002411 adverse Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
- H01L29/7785—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はへテロ接合を用いた電界効果トランジスタに関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a field effect transistor using a heterojunction.
従来の技術
ヘテロ接合を用いた電界効果トランジスタとして、従来
よシ、Ｎ型ＩＪＧａＡｓとノンドープＧａＡｓのヘテロ
接合界面にたまる高移動度の２次元電子ガスを用いた高
電子移動度トランジスタ（ＨｔｇｈＥｌｅｃｔｒｏｎ
Ｍｏｂｉｌｉｔｙ Ｔｒａｎｓｉｓｔｏｒ ； ）（Ｅ
ＭＴ ）がよく知られている。Conventional technology As a field effect transistor using a heterojunction, a high electron mobility transistor (HtghElectron
Mobility Transistor ; )(E
MT) is well known.
発明が解決しようとする問題点
ＨＥＭＴの欠点として、ヘテロ界面にたまる２次元電子
ガスの飽和濃度が低く（〜１×１０１しｄ）、チャンネ
ルの導電率が室温で通常のＧａＡｓのＭＥＳＦＥＴに比
べて同程度かそれ以下になること、Ｎ型ＡＩＧａＡａ中
のＤＸセンターと呼ばれる深い準位のため、光や温度に
対して素子特性の変化が大きくまた不安定であるという
点があげられる。Problems to be Solved by the Invention The disadvantages of HEMTs are that the saturation concentration of the two-dimensional electron gas that accumulates at the hetero interface is low (~1 x 101d), and the conductivity of the channel is lower than that of ordinary GaAs MESFETs at room temperature. Because of the deep level called the DX center in N-type AIGaAa, the device characteristics change greatly with respect to light and temperature and are unstable.
さらに、Ｎ型Ａｊｉ’ＧａＡｓ＋とＧａＡｓ のコンダ
クションバンドの不連続量、ΔＥｃが小さいため、高電
界での２次元電子ガスは、ＡｌＧａＡｓの障壁を越えて
、ＧａＡｓよりＡｌＧａＡｓ にあふれ出すという問題
もある０
問題点を解決するための手段
本発明は、以上のような従来例の問題点を解決する新し
い構造のへテロ接合電界効果トランジスタを提供するも
のである。電子濃度を高めるために、チャンネル層をＮ
型ＧａＡｓ＋層とノンドープのｌｎ２Ｇａ１−２Ａｌｌ
よりなる構成とし、さらに、チャンネル層を電子に対し
障壁となるＡｌＧａＡｓ層で挾んだ構造とするものであ
る。チャンネル層の両側のＡｌ１ＧａＡｓ層は、ノンド
ープでも、Ｎ型にしてもよいが、Ｎ型のＡｌＧａＡｓを
用いる場合には、ＡｌＧａＡｓ中のＡｌＡｓ組成を０．
２以下とすることにより、Ｄｘセンターの悪影響を除く
ことができる。Furthermore, because the amount of discontinuity, ΔEc, in the conduction band of N-type Aji'GaAs+ and GaAs is small, there is a problem that two-dimensional electron gas in a high electric field exceeds the barrier of AlGaAs and overflows from GaAs to AlGaAs. 0 Means for Solving the Problems The present invention provides a heterojunction field effect transistor with a new structure that solves the problems of the conventional example as described above. The channel layer is made of N to increase the electron concentration.
type GaAs+ layer and non-doped ln2Ga1-2All
Furthermore, the channel layer is sandwiched between AlGaAs layers that act as a barrier against electrons. The Al1GaAs layers on both sides of the channel layer may be non-doped or N-type, but if N-type AlGaAs is used, the AlAs composition in the AlGaAs should be 0.
By setting it to 2 or less, the negative influence of the Dx center can be removed.
作 用
本発明の構造を珀いることにより、電界効果トランジス
タの特性を向上させることができる。チャンネル層にた
まる電子の濃度をさらに増加するためには、チャンネル
層の両側、あるいは片側のＡｌＧａＡｓにＮ型不純物を
添加すればよい、この場合には、ＤＸセンターによる悪
影響を除くためにＡｌＧａＡｓのＡｌＡｓ組成比を０．
２以下とすることが必要となる。Function: By incorporating the structure of the present invention, the characteristics of a field effect transistor can be improved. In order to further increase the concentration of electrons accumulated in the channel layer, N-type impurities may be added to the AlGaAs on both sides or one side of the channel layer. Set the composition ratio to 0.
It is necessary to set it to 2 or less.
実施例
本発明の第１の実施例を第１図に示す。第１図（ａ）の
断面構造において、１は半絶縁性ＧａＡｓ基板、２は０
．１μｍの厚さのノンドープＧａＡｓ層、３は０．２μ
ｍの厚さのノンドープＡｌｏ、３Ｇａｏ、 ７Ａｓ層、
４及び６は、ドナー濃度４ Ｘ １０ ／ｌｙｌの膜厚
が６０人のＮ型ＧａＡｓ層、５はノンドープのＩ ｎ、
Ｇａ１−ｚＡｓ層、７は、膜厚２００人のノンドープの
＃ｏ、５Ｇａｏ、ｙ”層である。Ｉ ｒｘ ｚＧａ １
− ｚＡｓ層の厚さは１００人、２゜は０．２５とした
。Ｎ型ＧａＡｓ層（４及び６）と”０．２ｓＧａｏ、
７５Ａ１１層５にヨッテチャンネル層カ形成され、電子
濃度は最大４×１０／ｃＩｒＬと非常に高い値を示した
。Ｍｏ、３Ｇａ０．７ＡＢ層（３及び７）は、チャンネ
ル層に閉じ込めるための障壁層である。Embodiment A first embodiment of the present invention is shown in FIG. In the cross-sectional structure of FIG. 1(a), 1 is a semi-insulating GaAs substrate, 2 is 0
．． 1 μm thick non-doped GaAs layer, 3 is 0.2 μm
m-thick non-doped Alo, 3Gao, 7As layer,
4 and 6 are N-type GaAs layers with a donor concentration of 4 x 10 /lyl and a film thickness of 60 nm, 5 is a non-doped In,
The Ga1-zAs layer 7 is a non-doped #o, 5Gao,y'' layer with a thickness of 200.I rx zGa 1
- The thickness of the zAs layer was 100, and the 2° was 0.25. N-type GaAs layers (4 and 6) and 0.2s Gao,
A Yotte channel layer was formed on the 75A11 layer 5, and the electron concentration showed a very high value of 4×10/cIrL at maximum. The Mo, 3Ga0.7AB layers (3 and 7) are barrier layers for confinement in the channel layer.
８はソース電極、９はドレイン電極、１０はゲート電極
を示し’、 Ｍ Ｉ Ｓ （Ｍｅｔａｌ−ＩｎＢｕｌａ
ｔｏｒ −３部ｍｉｃｏｎｄｕｃｔｏｒ ）型の電界効
果トランジスタが構成される。第１図（ｂ）は、チャン
ネル層近傍のバンドダイアグラムを示す。8 is a source electrode, 9 is a drain electrode, and 10 is a gate electrode.
A field effect transistor of the tor-3-microconductor type is constructed. FIG. 1(b) shows a band diagram near the channel layer.
チャンネル層のＮ型ＧａＡｓは、それ自身導電層として
も働くが、ｌｎ２Ｇａ１−２Ａｓ層への電子供給層とし
ても作用する。すなわち第１図（ｂ）のバンドダイアグ
ラムに示すように、ｌｎ２Ｇａ１−ｚＡｓの量子井戸に
Ｎ型ＧａＡｓ層に電子が供給されＮ −ＡｌＧａＡｓ／
ＧａＡｓで構成されたＨＥＭＴにおけるＮ−ＡｌＧａＡ
ｓと同様な役目を果すことになる。Ｎ型ＧａＡｓを電子
供給層として用いる利点は、高いドナー濃度（６〜８ｘ
１０／７）を得ることができるため、所望の電子濃度を
Ｉｎ２Ｇａ１−ｚＡｓ層にためるためのＮ型ＧａＡｇ層
厚を薄くできること、Ｎ−ＡｌＧａＡｓ層のようにＤＸ
センターの悪影響がないことであり、高い相互コンダク
タンスをもつ、素子特性の安定な電界効果トランジスタ
を得るのに好適である。またチャンネル層をＡｌ１Ｇａ
Ａｇ層で挾んだ構造とすることにより、ＩｎｚＧａ１．
、−ｚＡｓにたまった電子から見て、障壁の高さを十分
に高くでき、高電界での熱い電子が、Ｉｎ２Ｇａ１−ｚ
Ａｓ量子井戸をあふれ出したとしても、ＡｌＧａＡｓ層
の障壁により、電子の、チャンネル層内にとどまる確率
が増える。チャンネル層はＧａＡｓと、Ｉ ｎ ｚＧａ
１−ｚＡｓ層で構成されているので、電子が、チャン
ネル層内にとどまる限シ、高い飽和速度が維持されるこ
とになる。また、チャンネル層内の電子の大部分は、ノ
ンドープＩ ｎ ２Ｇａ １□ｚＡｓ層にたまるため、
電子の移動度及び、飽和速度もＧａＡｓ単独のチャンネ
ル層に比べて高くなる。The N-type GaAs of the channel layer functions not only as a conductive layer itself, but also as an electron supply layer to the ln2Ga1-2As layer. That is, as shown in the band diagram of FIG. 1(b), electrons are supplied to the N-type GaAs layer in the quantum well of ln2Ga1-zAs, resulting in N -AlGaAs/
N-AlGaA in HEMT composed of GaAs
It will play the same role as s. The advantage of using N-type GaAs as the electron supply layer is the high donor concentration (6-8x
10/7), the thickness of the N-type GaAg layer for accumulating the desired electron concentration in the In2Ga1-zAs layer can be made thinner, and the DX
There is no adverse effect of the center, and it is suitable for obtaining a field effect transistor with high mutual conductance and stable device characteristics. In addition, the channel layer is made of Al1Ga
By forming a structure sandwiched between Ag layers, InzGa1.
, -zAs, the height of the barrier can be made sufficiently high, and the hot electrons in the high electric field
Even if the As quantum well is overflowed, the barrier of the AlGaAs layer increases the probability that electrons will remain in the channel layer. The channel layer is made of GaAs and InzGa.
Since it is composed of a 1-zAs layer, a high saturation velocity will be maintained as long as the electrons remain within the channel layer. In addition, most of the electrons in the channel layer accumulate in the non-doped In 2Ga 1□zAs layer, so
The electron mobility and saturation velocity are also higher than in a channel layer made of GaAs alone.
本発明の第２の実施例を第２図に示す。第２図は、第１
図（−）におけるチャンネル層の構成を、Ｎ型ＧａＡｓ
層４と、その上に形成した１００ＡのノンドープＩｎｏ
、 ２５Ｇａ０．７−ｙＡｓ としたもので、Ｎ型Ｇ
ａＡｓ の膜厚を１ｏＯＡ、ドナー濃度を４ Ｘｌ ０
１８／／ｃＩＩとした。この場合にも、チャンネルにた
まる電子濃度として４×１０１シｄ が得られた。A second embodiment of the invention is shown in FIG. Figure 2 shows the first
The structure of the channel layer in the figure (-) is made of N-type GaAs.
Layer 4 and a 100A non-doped Ino layer formed thereon.
, 25Ga0.7-yAs, N-type G
The aAs film thickness is 1oOA, the donor concentration is 4Xl 0
18//cII. In this case as well, 4×10 1 sid was obtained as the electron concentration accumulated in the channel.
第１の実施例および第２の実施例におけるノンドープの
Ａｔｅｏ、３Ｇａ０．７Ａｓ層をＡ１０．２Ｇａ０．８
部８層に置きかえ、かつ、Ａｌｏ、 ２Ｇａｏ、 ａＡ
ｓ層の１部にＮ型不純物を１×１０ ／ｃｒ／Ｉドープ
したところ、どちらの場合にも電子濃度として５〜６
Ｘ １０１２／Ｃ１／ｌという値を得た。The non-doped Ateo, 3Ga0.7As layer in the first and second embodiments was replaced with A10.2Ga0.8
8 layers, and Alo, 2Gao, aA
When part of the s-layer was doped with N-type impurities at 1×10 /cr/I, the electron concentration was 5 to 6 in both cases.
A value of X 1012/C1/l was obtained.
以上の実施例における電界効果トランジスタでは、温度
や光によるしきい値電圧の変化やＦＥＴ特性の大幅な変
化は見られず、従来のＮ −Ａｌ１ａＡｓ層／ ＧａＡ
ｓ系ＨＥＭＴに比べ特性が安定であった。In the field effect transistors in the above embodiments, no changes in threshold voltage or large changes in FET characteristics due to temperature or light were observed, and the conventional N-Al1aAs layer/GaA
The characteristics were more stable than s-based HEMTs.
発明の効果
以上述べたように、本発明のへテロ接合電界効果トラン
ジスタでは、従来のＨＥＭＴの様なＮ型ＭｘＧａ 、−
ｚＡｓ （” 〜０．３ ）中のＤｘセンターによる特
性の不安定さを無くすことができるばかりでなく、チャ
ンネル層に、高い電子濃度を供給するＮ型ＧａＡｓと電
子のたまるＩ ｎ ２Ｇａ １１Ａｓを用いているので
、チャンネル内に高移動度の高い電子濃度を実現できる
。また、Ｉ ｎ ｚＧａ １−ｚＡｓの量子井戸中を電
子は主として走行するので、チャンネル外部のｌ’ＪＩ
ＧａＡｓ障壁層のＭ組成比が０．２以下であっても、電
子に対して十分高い障壁となり、高電界において電子が
チャンネルよりあふれ出す確率を低下させられる。従っ
て本発明の構造を用いることにより、高い相互コンダク
タンスを有した、温度、光に対して特性の安定なヘテロ
接合電界効果トランジスタを実現できる。なお、Ｉ ｎ
ｚＧａ、−ＺＡｓ層の膜厚としては、５０人〜１５０Ａ
が適切であり、２の値としては０．２５以下が、膜内に
転位の入らない条件として適している。Effects of the Invention As described above, in the heterojunction field effect transistor of the present invention, N-type MxGa, -
Not only can the instability of characteristics caused by the Dx center in zAs (~0.3) be eliminated, but the channel layer is made of N-type GaAs, which supplies a high electron concentration, and I n 2Ga 11As, which accumulates electrons. Since the electrons mainly travel in the quantum well of I n zGa 1-zAs, it is possible to realize a high electron concentration with high mobility inside the channel.
Even if the M composition ratio of the GaAs barrier layer is 0.2 or less, it becomes a sufficiently high barrier to electrons, and the probability that electrons overflow from the channel in a high electric field can be reduced. Therefore, by using the structure of the present invention, a heterojunction field effect transistor having high mutual conductance and stable characteristics against temperature and light can be realized. In addition, I n
The thickness of the zGa, -ZAs layer is 50 to 150A.
is appropriate, and a value of 2 of 0.25 or less is suitable as a condition for preventing dislocations from entering the film.
第１図（ａ）および第２図は、本発明の第１．第２の実
施例としての電界効果トランジスタの素子構造を示す断
面図、第１図０））は同第１の実施例におけるチャンネ
ル層付近の伝導帯エネルギーバンドダイアグラムである
。
１・・・・・・半絶縁性ＧａＡｓ基板、２・・・・・ラ
ンドープＧａＡｓ層、３．７・・・・・ランドープＮｏ
。３０ａ０．７ＡＢ層、４，６・・・・・・Ｎ型ＧａＡ
ｓ層、６・・川・ノンドープＩｎｚＧａ１−ｚＡｓ層、
８・・・・・・ソース電甑、９・・・・・・ドレイン電
極、１０・山・・ゲート電極。FIG. 1(a) and FIG. 2 illustrate the first embodiment of the present invention. A cross-sectional view showing the element structure of a field effect transistor as a second embodiment, FIG. 10)) is a conduction band energy band diagram near the channel layer in the first embodiment. 1... Semi-insulating GaAs substrate, 2... Land-doped GaAs layer, 3.7... Land-doped No.
. 30a0.7AB layer, 4,6...N-type GaA
s layer, 6... river non-doped InzGa1-zAs layer,
8... Source electrode, 9... Drain electrode, 10. Mountain... Gate electrode.
Claims (1)
層とＡｌ＿ｙＧａ＿１＿−＿ｙＡｓ層が順次形成され、
前記チャンネル層として、ノンドープのＩｎ＿ｚＧａ＿
１＿−＿ｚＡｓ層とＮ型ＧａＡｓで構成されるヘテロ接
合構造を用いてなる電界効果トランジスタ。（２）Ａｌ
＿ｘＧａ＿１＿−＿ｘＡｓ層及び、Ａｌ＿ｙＧａ＿１＿
−＿ｙＡｓ層の一部にＮ型不純物がドープされ、ｘおよ
びｙの値が０．２以下である特許請求の範囲第１項に記
載の電界効果トランジスタ。(1) A channel layer and an Al_yGa_1_-_yAs layer are sequentially formed on the Al_xGa_1_-_xAs layer,
As the channel layer, non-doped In_zGa_
A field effect transistor using a heterojunction structure composed of a 1_-_zAs layer and N-type GaAs. (2) Al
_xGa_1_-_xAs layer and Al_yGa_1_
The field effect transistor according to claim 1, wherein a part of the −_yAs layer is doped with an N-type impurity, and the values of x and y are 0.2 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31136586A JPH0714057B2 (en) | 1986-12-25 | 1986-12-25 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31136586A JPH0714057B2 (en) | 1986-12-25 | 1986-12-25 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63161678A true JPS63161678A (en) | 1988-07-05 |
| JPH0714057B2 JPH0714057B2 (en) | 1995-02-15 |
Family
ID=18016289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31136586A Expired - Fee Related JPH0714057B2 (en) | 1986-12-25 | 1986-12-25 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0714057B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5223724A (en) * | 1990-07-31 | 1993-06-29 | At & T Bell Laboratories | Multiple channel high electron mobility transistor |
| US5266506A (en) * | 1990-07-31 | 1993-11-30 | At&T Bell Laboratories | Method of making substantially linear field-effect transistor |
| JPH0645366A (en) * | 1991-03-26 | 1994-02-18 | Mitsubishi Electric Corp | Field effect transistor |
| US5373168A (en) * | 1991-12-05 | 1994-12-13 | Nec Corporation | Two-dimensional electron gas field effect transistor including an improved InGaAs channel layer |
| US5486705A (en) * | 1993-06-15 | 1996-01-23 | Matsushita Electric Industrial Co., Ltd. | Heterojunction field effect transistor |
| US5488237A (en) * | 1992-02-14 | 1996-01-30 | Sumitomo Electric Industries, Ltd. | Semiconductor device with delta-doped layer in channel region |
-
1986
- 1986-12-25 JP JP31136586A patent/JPH0714057B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5223724A (en) * | 1990-07-31 | 1993-06-29 | At & T Bell Laboratories | Multiple channel high electron mobility transistor |
| US5266506A (en) * | 1990-07-31 | 1993-11-30 | At&T Bell Laboratories | Method of making substantially linear field-effect transistor |
| JPH0645366A (en) * | 1991-03-26 | 1994-02-18 | Mitsubishi Electric Corp | Field effect transistor |
| US5373168A (en) * | 1991-12-05 | 1994-12-13 | Nec Corporation | Two-dimensional electron gas field effect transistor including an improved InGaAs channel layer |
| US5488237A (en) * | 1992-02-14 | 1996-01-30 | Sumitomo Electric Industries, Ltd. | Semiconductor device with delta-doped layer in channel region |
| US5486705A (en) * | 1993-06-15 | 1996-01-23 | Matsushita Electric Industrial Co., Ltd. | Heterojunction field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0714057B2 (en) | 1995-02-15 |
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