JPS628028B2 - - Google Patents
Info
- Publication number
- JPS628028B2 JPS628028B2 JP15614280A JP15614280A JPS628028B2 JP S628028 B2 JPS628028 B2 JP S628028B2 JP 15614280 A JP15614280 A JP 15614280A JP 15614280 A JP15614280 A JP 15614280A JP S628028 B2 JPS628028 B2 JP S628028B2
- Authority
- JP
- Japan
- Prior art keywords
- oxidation
- substrate
- oxide film
- mask
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 66
- 230000003647 oxidation Effects 0.000 claims description 64
- 238000007254 oxidation reaction Methods 0.000 claims description 64
- 239000000463 material Substances 0.000 claims description 46
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 42
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 42
- 239000004065 semiconductor Substances 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000000992 sputter etching Methods 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に絶
縁物による素子分離技術を改良した半導体装置の
製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that improves element isolation technology using an insulator.
半導体集積回路における分離技術に関しては高
集積化、製造プロセスの容易化を図るものとして
一般に分離領域を選択酸化技術によつて形成した
酸化膜を使用するものが知られている。この方式
によれば、能動領域の周囲が酸化膜によつて取り
囲まれているため、ベース拡散等においてセルフ
アラインメントが可能で従来のようなマスク合せ
のための不要な部分が省略でき、高集積化が可能
となり、また側面が深い酸化膜により構成された
ことによつて接合容量は桁違いに減少する。しか
しながら、この方式ではシリコン基板中に熱酸化
膜を選択的に埋没させる構造のため、シリコン基
板に大きな歪が生じ、素子の電気的特性を劣化さ
せ、耐酸化性マスクの構造、構成、膜厚及び選択
酸化条件、時にはシリコン基板そのものの材料自
身の選択に著しい制限を与えている。これは、例
えば文献IEDM“High Pressure Oxidation for
Isolation of High Speed Bipolar Devices”
1979年PP340〜343に記載されている。 Regarding isolation technology in semiconductor integrated circuits, it is generally known to use an oxide film formed by selective oxidation technology as an isolation region in order to achieve high integration and ease of manufacturing process. According to this method, since the active region is surrounded by an oxide film, self-alignment is possible in base diffusion, etc., and unnecessary parts for mask alignment can be omitted as in conventional methods, allowing for high integration. Since the side surfaces are made of a deep oxide film, the junction capacitance is reduced by an order of magnitude. However, since this method has a structure in which the thermal oxide film is selectively buried in the silicon substrate, large strains occur in the silicon substrate, deteriorating the electrical characteristics of the device, and reducing the structure, composition, and film thickness of the oxidation-resistant mask. Also, selective oxidation conditions, and sometimes the selection of the material of the silicon substrate itself, are severely restricted. This can be seen, for example, in the literature IEDM “High Pressure Oxidation for
Isolation of High Speed Bipolar Devices”
Described in 1979 PP340-343.
また、窒化シリコン膜をマスクにして熱酸化を
行なうと、“ホワイトリボン”と称されるシリコ
ンナイトライドが窒化シリコン膜下のシリコン基
板中に形成され、これが素子の耐圧不良の原因と
なる。 Furthermore, when thermal oxidation is performed using a silicon nitride film as a mask, silicon nitride, called a "white ribbon", is formed in the silicon substrate under the silicon nitride film, which causes a breakdown voltage failure of the device.
このようなことから、本出願人は半導体基板上
に該基板より酸化速度の速い材料層を形成し、こ
の材料層上に耐酸化性マスクを選択的に形成した
後該材料層を選択酸化し、酸化膜を形成し、更に
前記マスクとその下の材料層の少なくとも一部を
除去することにより、半導体基板への熱影響によ
る欠陥発生を抑制し、かつホワイトリボンの発生
を防止し電気特性の良好な半導体装置の製造方法
を提案した（特願昭55−27310号）。しかしなが
ら、この方法では半導体基板上の材料層を選択酸
化する際、該材料層の酸化が終了すると、その下
の基板が酸化され始めるため、材料層の酸化終点
を厳格に制御する必要があつた。また、材料層と
して不純物ドープ多結晶シリコン層を用いた場
合、選択酸化時に多結晶シリコン層中の不純物が
半導体基板の素子領域に拡散する恐れがある。例
えば、多結晶シリコン層中に高濃度のリンを含む
場合、ｎチヤンネルトランジスタでは、選択酸化
時に素子領域にリンが拡散して所望の閾値を得る
ことが困難となる。 For this reason, the present applicant forms a material layer on a semiconductor substrate with a faster oxidation rate than the substrate, selectively forms an oxidation-resistant mask on this material layer, and then selectively oxidizes the material layer. , by forming an oxide film and removing at least a portion of the mask and the underlying material layer, the generation of defects due to thermal effects on the semiconductor substrate is suppressed, the generation of white ribbons is prevented, and the electrical characteristics are improved. He proposed a method for manufacturing good semiconductor devices (Japanese Patent Application No. 55-27310). However, in this method, when selectively oxidizing a material layer on a semiconductor substrate, once the oxidation of the material layer is completed, the underlying substrate begins to be oxidized, so it was necessary to strictly control the oxidation end point of the material layer. . Furthermore, when an impurity-doped polycrystalline silicon layer is used as the material layer, there is a risk that impurities in the polycrystalline silicon layer will diffuse into the element region of the semiconductor substrate during selective oxidation. For example, when a polycrystalline silicon layer contains a high concentration of phosphorus, in an n-channel transistor, phosphorus diffuses into the element region during selective oxidation, making it difficult to obtain a desired threshold value.
本発明は上記本出願人提案の方法を改良するた
めになされたもので、半導体基板上に酸化膜と窒
化シリコン膜を介して該基板より酸化速度の速い
材料層を形成し、これを耐酸化性マスクを用いて
選択酸化することにより、前記窒化シリコン膜の
酸化阻止作用によつて材料層の酸化終点を制御せ
ずに、半導体基板への酸化を招くことなく素子間
分離膜を形成でき、もつて半導体基板への熱影響
を抑制すると共にストレス発生を確実に防止で
き、欠陥発生の極めて少ない基板を有し電気特性
の良好な半導体装置を製造し得る方法を提供しよ
うとするものである。 The present invention was made in order to improve the method proposed by the present applicant, in which a layer of material having a faster oxidation rate than the substrate is formed on a semiconductor substrate via an oxide film and a silicon nitride film, and this is made resistant to oxidation. By performing selective oxidation using a chemical mask, it is possible to form an isolation film between elements without controlling the oxidation end point of the material layer and without causing oxidation to the semiconductor substrate due to the oxidation inhibiting effect of the silicon nitride film, It is an object of the present invention to provide a method that can suppress thermal effects on a semiconductor substrate, reliably prevent the occurrence of stress, and manufacture a semiconductor device having a substrate with extremely few defects and having good electrical characteristics.
すなわち、本発明は半導体基板上に酸化膜及び
窒化シリコン膜を順次形成する工程と、この窒化
シリコン膜上に前記基板より酸化速度の速い材料
層を形成する工程と、この材料層上に耐酸化マス
クを選択的に形成する工程と、この耐酸化性マス
クを用いて前記基板に該基板と同導電型の不純物
をドーピングする工程と、前記耐酸化性マスクを
用いて前記材料層を選択酸化して厚い酸化膜を形
成する工程と、前記耐酸化性マスクを除去した
後、露出した残存材料層を少なくとも一部除去す
る工程とを具備したことを特徴とするものであ
る。 That is, the present invention includes a step of sequentially forming an oxide film and a silicon nitride film on a semiconductor substrate, a step of forming a layer of a material having a faster oxidation rate than the substrate on this silicon nitride film, and a step of forming an oxidation-resistant layer on this material layer. selectively forming a mask; doping the substrate with an impurity of the same conductivity type as the substrate using the oxidation-resistant mask; and selectively oxidizing the material layer using the oxidation-resistant mask. and a step of removing at least a portion of the exposed remaining material layer after removing the oxidation-resistant mask.
本発明における半導体基板としては、ｐ型シリ
コン基板、ｎ型シリコン基板、或いはGaAsなど
の化合物半導体基板等を挙げることができる。 Examples of the semiconductor substrate in the present invention include a p-type silicon substrate, an n-type silicon substrate, and a compound semiconductor substrate such as GaAs.
本発明における基板上に形成される酸化膜及び
窒化シリコン膜は材料層の選択酸化時に該材料層
下の基板が酸化されるのを防ぐ酸化ストツパの作
用を有する。また、こうした酸化膜及び窒化シリ
コン膜を基板と材料層間に介在させることによつ
て、材料層として高濃度不純物ドープ多結晶シリ
コン層を用いた場合、選択酸化時に該多結晶シリ
コン層中の不純物が半導体基板に拡散するのを阻
止できる。かかる窒化シリコン膜は主に基板への
酸化防止作用を、酸化膜は窒化シリコン膜による
基板へのストレス発生を抑制する緩衝材等として
の作用する。酸化膜の厚膜については500〜3000
Å、窒化シリコン膜の膜厚については酸化の阻止
作用と基板へのストレスを小さくする観点から
500〜3000Åにすることが望ましい。 In the present invention, the oxide film and silicon nitride film formed on the substrate have the function of an oxidation stopper that prevents the substrate under the material layer from being oxidized during selective oxidation of the material layer. Furthermore, by interposing such an oxide film and a silicon nitride film between the substrate and the material layer, when a highly impurity-doped polycrystalline silicon layer is used as the material layer, impurities in the polycrystalline silicon layer are removed during selective oxidation. Diffusion into the semiconductor substrate can be prevented. Such a silicon nitride film mainly acts as an oxidation preventive effect on the substrate, and the oxide film acts as a buffer material that suppresses stress generation on the substrate due to the silicon nitride film. 500-3000 for thick oxide film
Å, The thickness of the silicon nitride film is determined from the viewpoint of preventing oxidation and reducing stress on the substrate.
It is desirable to set the thickness to 500 to 3000 Å.
本発明における半導体基板より酸化速度の速い
材料層は選択酸化により素子間分離膜としての酸
化膜を形成するために利用される。かかる材料と
しては、例えばリン、砒素、ボロンなどの不純物
が高濃度ドープされた多結晶シリコン、或いはモ
リブデンシリサイド、タングステンシリサイド、
タンタルシリサイドなどの金属硅化物等を挙げる
ことができる。 In the present invention, the material layer having a faster oxidation rate than the semiconductor substrate is used to form an oxide film as an isolation film between elements by selective oxidation. Examples of such materials include polycrystalline silicon heavily doped with impurities such as phosphorus, arsenic, and boron, molybdenum silicide, tungsten silicide,
Examples include metal silicides such as tantalum silicide.
本発明における耐酸化性マスクの形成手段とし
ては、例えば材料層上に直接窒化シリコン膜を堆
積し、光蝕刻法で作られたフオトレジストパター
ンをエツチングマスクとしてパターニングして窒
化シリコンパターンからなる耐酸化性マスクを形
成する方法、材料層上に酸化膜、窒化シリコン膜
を順次形成し、これらを光蝕刻法で作られたフオ
トレジストパターンをエツチングマスクとしてパ
ターニングして２層構造の耐酸化性マスクを形成
する方法等を挙げることができる。こうして形成
された耐酸化性マスクは半導体基板にチヤンネル
ストツパを形成するための不純物ドーピングのマ
スクとして用いる。なお、この耐酸化性マスクを
形成する際に用いたフオトレジストパターンを不
純物ドーピングのマスクとして使用してもよい。
また、前記耐酸化性マスクは材料層の選択酸化時
のマスクとして用いる。特に、材料層上に直接窒
化シリコンパターンからなる耐酸化性マスクを形
成し、これを用いて材料層を選択酸化すると、マ
スク下への酸化膜の喰い込み、いわゆるバーズビ
ークを著しく抑制できると共に、残存材料層表面
の一部にオキシナイトライド膜が生成されるのを
防止できる。なお、オキシナイトライド膜が生成
されないことによる効果は以下の如くである。即
ち、選択酸化により材料層の露出部付近に厚い酸
化膜を形成し、マスクを除去した後、残存材料層
を除去するが、この除去にあたつては形成すべき
素子間分離膜がオーバーハング構造となるのを避
けるために反応性スパツタイオンエツチングによ
り除去する。しかし、このエツチング時に残存し
た帯状のオキシナイトライド膜が生成されると、
これがエツチングマスクとして作用し、厚い酸化
膜に沿つて材料層が残る。こうした状態で残つた
材料層を熱酸化して酸化膜に変換すると、素子間
分離膜の面積が広くなる、つまり寸法変換差が大
きくなり、素子の微細化の妨げとなる。したがつ
て、選択酸化時に、耐酸化性マスク下の材料層表
面の一部にオキシナイトライド膜が生じないこと
は、素子の微細化の点から極めて有益である。 As a means for forming an oxidation-resistant mask in the present invention, for example, a silicon nitride film is deposited directly on a material layer, and a photoresist pattern made by a photolithography method is used as an etching mask to pattern the oxidation-resistant mask. A two-layer oxidation-resistant mask is formed by sequentially forming an oxide film and a silicon nitride film on a material layer, and patterning these using a photoresist pattern made by photolithography as an etching mask. Examples include a method of forming. The oxidation-resistant mask thus formed is used as an impurity doping mask for forming a channel stopper in a semiconductor substrate. Note that the photoresist pattern used in forming this oxidation-resistant mask may be used as a mask for impurity doping.
Further, the oxidation-resistant mask is used as a mask during selective oxidation of a material layer. In particular, by forming an oxidation-resistant mask consisting of a silicon nitride pattern directly on the material layer and using this to selectively oxidize the material layer, it is possible to significantly suppress the digging of the oxide film under the mask, so-called bird's beak, and to It is possible to prevent an oxynitride film from being formed on a part of the surface of the material layer. The effects of not producing an oxynitride film are as follows. That is, a thick oxide film is formed near the exposed part of the material layer by selective oxidation, and after removing the mask, the remaining material layer is removed, but during this removal, the isolation film to be formed is not overhanged. It is removed by reactive sputter ion etching to avoid structures. However, if a band-shaped oxynitride film remains during etching,
This acts as an etch mask, leaving a layer of material along the thick oxide layer. If the material layer remaining in such a state is thermally oxidized and converted into an oxide film, the area of the isolation film between elements becomes larger, that is, the difference in dimensional conversion becomes larger, which impedes miniaturization of the elements. Therefore, it is extremely beneficial from the viewpoint of device miniaturization that an oxynitride film is not formed on a part of the surface of the material layer under the oxidation-resistant mask during selective oxidation.
本発明における残存材料層の除去手段として
は、酸化膜端部下がオーバーハング構造となるの
を避けるために、基板に対して略垂直に残存材料
層をエツチングし得る反応性スパツタイオンエツ
チング法、イオンビームエツチング法などの異方
性エツチング法を採用することが望ましい。 The means for removing the remaining material layer in the present invention includes a reactive sputter ion etching method that can etch the remaining material layer approximately perpendicularly to the substrate in order to avoid an overhang structure under the edge of the oxide film; It is desirable to employ an anisotropic etching method such as ion beam etching.
次に、本発明をｎチヤンネルMOS Ｉ Ｃの製
造に適用した例について図面を参照して説明す
る。 Next, an example in which the present invention is applied to the manufacture of an n-channel MOS IC will be described with reference to the drawings.
実施例 １
〔〕 まず、ｐ型の単結晶シリコン基板１を熱
酸化処理して、その主面に厚さ1000Åの熱酸化
膜２を成長させ、更に厚さ1000Åの窒化シリコ
ン膜３を堆積した後、窒化シリコン膜３上に多
結晶シリコンをPOCl3雰囲気中で気相成長さ
せ、基板より酸化速度の速い材料層である厚さ
4000Åのリンドープ多結晶シリコン層４を堆積
した（第１図ａ図示）。つづいて、多結晶シリ
コン層４上に直接厚さ2000Åの窒化シリコン膜
を気相成長法により堆積し、反応性スパツタイ
オンエツチングを用いてフオトエツチングプロ
セスにより窒化シリコンパターン５を形成し
た。ひきつづき、窒化シリコンパターン５をマ
スクとしてボロンを出力180KeV、ドーズ量４
×1013／cm2の条件でイオン注入し、活性化して
基板１にp+型のチヤンネルストツパ６を形成
した（第１図ｂ図示）。なお、この場合窒化シ
リコンパターンの形成に使用したフオトレジス
トパターンをマスクとしてボロンのイオン注入
を行なつてもよい。Example 1 [] First, a p-type single crystal silicon substrate 1 was thermally oxidized to grow a thermal oxide film 2 with a thickness of 1000 Å on its main surface, and a silicon nitride film 3 with a thickness of 1000 Å was further deposited. After that, polycrystalline silicon is grown in a vapor phase on the silicon nitride film 3 in a POCl 3 atmosphere to form a layer of material with a faster oxidation rate than the substrate.
A 4000 Å thick phosphorus-doped polycrystalline silicon layer 4 was deposited (as shown in FIG. 1a). Subsequently, a silicon nitride film with a thickness of 2000 Å was deposited directly on the polycrystalline silicon layer 4 by vapor phase epitaxy, and a silicon nitride pattern 5 was formed by a photoetching process using reactive sputter ion etching. Continuing, using the silicon nitride pattern 5 as a mask, boron is output at 180 KeV and the dose is 4.
Ions were implanted under conditions of ×10 13 /cm 2 and activated to form a p + type channel stopper 6 on the substrate 1 (as shown in FIG. 1B). In this case, boron ions may be implanted using the photoresist pattern used to form the silicon nitride pattern as a mask.
〔〕 次いで、窒化シリコンパターン５を耐酸
化性マスクとして多結晶シリコン層４を選択酸
化した。この時、基板１は全く酸化されること
なく多結晶シリコン層４の露出部付近が酸化さ
れて寸法変換差が0.15μｍの素子間分離用の厚
さ8000Åの厚い酸化膜７が形成された（第１図
ｃ図示）。また、窒化シリコンパターン５下の
厚い酸化膜に沿う残存多結晶シリコン層４′の
表面部分にはオキシナイトライド膜は全く生じ
なかつた。更に、同選択酸化において、多結晶
シリコン層４′中のリンがシリコン基板１に拡
散するのを熱酸化膜２及び窒化シリコン膜３に
より阻止された。[] Next, polycrystalline silicon layer 4 was selectively oxidized using silicon nitride pattern 5 as an oxidation-resistant mask. At this time, the substrate 1 was not oxidized at all, and the vicinity of the exposed portion of the polycrystalline silicon layer 4 was oxidized, forming a thick oxide film 7 with a thickness of 8000 Å for device isolation with a dimensional conversion difference of 0.15 μm ( (Illustrated in Figure 1c). Further, no oxynitride film was formed on the surface portion of the remaining polycrystalline silicon layer 4' along the thick oxide film under the silicon nitride pattern 5. Furthermore, in the selective oxidation, diffusion of phosphorus in the polycrystalline silicon layer 4' into the silicon substrate 1 was prevented by the thermal oxide film 2 and the silicon nitride film 3.
〔〕 次いで、窒化シリコンパターン５をCF4
系のドライエツチングにより除去した後、残存
多結晶シリコン層４′をCCl4系の反応性スパツ
タイオンエツチングで除去した。この時、残存
多結晶シリコン層４′表面上にはオキシナイト
ライド膜が存在していないため厚い酸化膜７に
対してセルフアラインで該多結晶シリコン層
４′が略垂直にエツチングされ、第１図ｄに示
す如く厚い酸化膜７のオーバーハング部に多結
晶シリコン層４″が残つた。つづいて、露出し
た窒化シリコン膜３及び熱酸化膜２部分をCF4
プラズマ、フツ化アンモニウム液で順次除去し
て基板１表面の一部を露出させた（同第１図ｄ
図示）。[] Next, the silicon nitride pattern 5 is coated with CF 4
After removal by dry etching, the remaining polycrystalline silicon layer 4' was removed by reactive sputter ion etching using CCl 4 . At this time, since there is no oxynitride film on the surface of the remaining polycrystalline silicon layer 4', the polycrystalline silicon layer 4' is self-aligned and etched substantially perpendicularly to the thick oxide film 7. As shown in Figure d, a polycrystalline silicon layer 4'' remained on the overhang part of the thick oxide film 7.Subsequently, the exposed silicon nitride film 3 and thermal oxide film 2 were coated with CF4.
Part of the surface of the substrate 1 was exposed by sequentially removing it with plasma and ammonium fluoride solution (see Fig. 1d).
(Illustrated).
〔〕 次いで、熱酸化処理を施した。この時、
単結晶シリコン基板１の露出面に厚さ400Åの
ゲート酸化膜８が成長されると同時に、オーバ
ーハング部に残つた多結晶シリコン層４″が酸
化膜となり前記厚い酸化膜と共にオーバーハン
グのない素子間分離膜９が形成された（第１図
ｅ図示）。[] Next, thermal oxidation treatment was performed. At this time,
At the same time, a gate oxide film 8 with a thickness of 400 Å is grown on the exposed surface of the single crystal silicon substrate 1, and at the same time, the polycrystalline silicon layer 4'' remaining in the overhang portion becomes an oxide film, and together with the thick oxide film, a device without overhang is formed. A separation membrane 9 was formed (as shown in FIG. 1e).
〔〕 次いで、常法にしたがつてゲート酸化膜
８上に多結晶シリコンからなるゲート電極１０
を形成し、同ゲート電極１０をマスクとして砒
素のイオン注入、活性化を施してn+型のソー
ス、ドレイン（図示せず）を形成し、CVD−
SiO2膜、Al配線形成等を経た後、1000℃、60
分間の熱処理を施してｎチヤンネルMOS Ｉ
Ｃを製造した（第１図ｆ図示）。[] Next, a gate electrode 10 made of polycrystalline silicon is formed on the gate oxide film 8 according to a conventional method.
is formed, and using the same gate electrode 10 as a mask, arsenic ions are implanted and activated to form n + type sources and drains (not shown), and CVD-
After forming SiO 2 film, Al wiring, etc., 1000℃, 60℃
N-channel MOS I after heat treatment for 1 minute.
C was produced (as shown in FIG. 1 f).
しかして、本発明は単結晶シリコン基板１上に
設けられた該基板より酸化速度の速いリンドープ
多結晶シリコン層４を選択酸化することにより素
子間分離膜を形成するため、基板１への熱影響を
抑制でき、熱影響に伴なう基板１への欠陥発生、
不純物の再拡散を少なくできる。また、従来の選
択酸化法の如く基板１を直接酸化して素子間分離
膜を造るのではなく、基板１上のリンドープ多結
晶シリコン層４の選択酸化により該シリコン層４
下の基板１が酸化されるのを窒化シリコン膜３で
防止しつつ、素子間分離膜９を形成するため、基
板１への多大なストレス発生を防止できる。しか
も、窒化シリコンパターン５をマスクとした選択
酸化において、リンドープ多結晶シリコン層４中
のリンが基板１に拡散するのを窒化シリコン膜３
及び熱酸化膜２により阻止できる。更に、選択酸
化時に、オキシナイトライド膜が多結晶シリコン
層４上の一部に形成されないことは勿論、基板１
上にも全く形成されない。したがつて欠陥発生が
極めて少なく、かつチヤンネル領域へのリンの拡
散のないｐ型単結晶シリコン基板１を備えること
から、所望の閾値電圧を有し電気特性が良好な高
信頼性のｎチヤンネルMOS Ｉ Ｃを製造でき
る。 Therefore, in the present invention, since the device isolation film is formed by selectively oxidizing the phosphorus-doped polycrystalline silicon layer 4 provided on the single crystal silicon substrate 1, which has a faster oxidation rate than the substrate, the thermal influence on the substrate 1 is reduced. It is possible to suppress the occurrence of defects on the substrate 1 due to thermal effects,
Re-diffusion of impurities can be reduced. Furthermore, instead of directly oxidizing the substrate 1 to form an isolation film as in the conventional selective oxidation method, the silicon layer 4 is selectively oxidized by selectively oxidizing the phosphorus-doped polycrystalline silicon layer 4 on the substrate 1.
Since the inter-element isolation film 9 is formed while the silicon nitride film 3 prevents the underlying substrate 1 from being oxidized, the generation of great stress on the substrate 1 can be prevented. Furthermore, in selective oxidation using the silicon nitride pattern 5 as a mask, the silicon nitride film 3 prevents phosphorus in the phosphorus-doped polycrystalline silicon layer 4 from diffusing into the substrate 1.
This can be prevented by the thermal oxide film 2. Furthermore, during selective oxidation, it goes without saying that the oxynitride film is not formed on a portion of the polycrystalline silicon layer 4;
It does not form on the top at all. Therefore, since it has a p-type single crystal silicon substrate 1 with extremely few defects and no diffusion of phosphorus into the channel region, it is a highly reliable n-channel MOS with a desired threshold voltage and good electrical characteristics. IC can be manufactured.
また、リンドープ多結晶シリコン層４の選択酸
化時、窒化シリコンパターン５下の多結晶シリコ
ン層４部分への酸化膜の喰い込み、つまりバーズ
ビークは0.15μｍに抑えられること、並びに残存
多結晶シリコン層４′表面の一部にオキシナイト
ライド膜が生成せず、厚い酸化膜７に対してセル
フアラインで該多結晶シリコン層４′を略垂直に
エツチングできることにより、寸法変換差が少な
く微細な素子間分離膜９形成でき、その結果素子
の微細化が達成されたMOS Ｉ Ｃを得ることが
できる。 Further, during selective oxidation of the phosphorus-doped polycrystalline silicon layer 4, the penetration of the oxide film into the portion of the polycrystalline silicon layer 4 under the silicon nitride pattern 5, that is, the bird's beak, is suppressed to 0.15 μm, and the remaining polycrystalline silicon layer 4 'An oxynitride film is not formed on a part of the surface, and the polycrystalline silicon layer 4' can be etched almost perpendicularly in self-alignment with respect to the thick oxide film 7, resulting in fine separation between elements with little difference in dimensional conversion. The film 9 can be formed, and as a result, a MOS IC with miniaturized elements can be obtained.
実施例 ２
() まず、前記実施例１の工程に従つてｐ型単
結晶シリコン基板１上に厚さ1000Åの熱酸化膜
２及び厚さ1000Åの窒化シリコン膜３を形成
し、更に同窒化シリコン膜３上に厚さ4000Åの
リンドープ多結晶シリコン層４を堆積（第２図
ａ図示）した後、多結晶シリコン層４上に窒化
シリコンパターン５を形成し、これをマスクと
してボロンを基板１にドーピングしてp+型の
チヤンネルストツパ６を形成した（第２図ｂ図
示）。つづいて、窒化シリコンパターン５を耐
酸化性マスクとして選択酸化し、厚さ6000Åの
酸化膜７を形成すると共に該酸化膜７とその下
の窒化シリコン膜３との間に多結晶シリコン薄
層１１を残存させた（第２図ｃ図示）。Example 2 () First, a thermal oxide film 2 with a thickness of 1000 Å and a silicon nitride film 3 with a thickness of 1000 Å were formed on a p-type single crystal silicon substrate 1 according to the steps of Example 1, and After depositing a phosphorus-doped polycrystalline silicon layer 4 with a thickness of 4000 Å on the film 3 (as shown in FIG. 2a), a silicon nitride pattern 5 is formed on the polycrystalline silicon layer 4, and using this as a mask, boron is applied to the substrate 1. A p + type channel stopper 6 was formed by doping (as shown in FIG. 2b). Subsequently, selective oxidation is performed using the silicon nitride pattern 5 as an oxidation-resistant mask to form an oxide film 7 with a thickness of 6000 Å, and a polycrystalline silicon thin layer 11 is formed between the oxide film 7 and the silicon nitride film 3 below. was allowed to remain (as shown in Figure 2c).
() 次いで、窒化シリコンパターン５をCF4系
のドライエツチングにより除去した後、露出し
た残存多結晶シリコン層４′をCCl4系の反応性
スパツタイオンエツチングで除去した。この
時、残存多結晶シリコン層４′表面にはオキシ
ナイトライド膜が存在しないため、厚い酸化膜
７に対してセルフアラインで該多結晶シリコン
層４′が略垂直にエツチングされ、第２図ｄに
示す如く厚い酸化膜７のオーバーハング部に多
結晶シリコン層４″が残つた。ひきつづき、露
出した窒化シリコン膜３及び熱酸化膜２部分を
CF4系のプラズマ、フツ化アンモニウム液で順
次除去して基板１表面を露出させた（同第２図
ｄ図示）。() Next, the silicon nitride pattern 5 was removed by CF 4 -based dry etching, and then the exposed remaining polycrystalline silicon layer 4' was removed by CCl 4 -based reactive sputter ion etching. At this time, since there is no oxynitride film on the surface of the remaining polycrystalline silicon layer 4', the polycrystalline silicon layer 4' is self-aligned and etched substantially perpendicularly to the thick oxide film 7, as shown in FIG. As shown in the figure, the polycrystalline silicon layer 4'' remained on the overhang part of the thick oxide film 7.Continuing, the exposed silicon nitride film 3 and the thermal oxide film 2 were removed.
The surface of the substrate 1 was exposed by sequential removal using CF 4 -based plasma and ammonium fluoride solution (as shown in FIG. 2d).
() 次いで、熱酸化膜処理を施した。この時、
単結晶シリコン基板１の露出面に厚さ400Åの
ゲート酸化膜８が成長されると同時に、オーバ
ーハング部に残つた多結晶シリコン層４″が酸
化膜となり前記厚い酸化膜と共にオーバーハン
グのない素子間分離膜９が形成された（第２図
ｅ図示）。なお、この素子間分離膜９の中間付
近には多結晶シリコン薄層１１が存在してい
る。() Next, thermal oxidation film treatment was performed. At this time,
At the same time, a gate oxide film 8 with a thickness of 400 Å is grown on the exposed surface of the single crystal silicon substrate 1, and at the same time, the polycrystalline silicon layer 4'' remaining in the overhang portion becomes an oxide film, and together with the thick oxide film, a device without overhang is formed. An element isolation film 9 was formed (as shown in FIG. 2e).A polycrystalline silicon thin layer 11 is present near the middle of this element isolation film 9.
() 次いで常法にしたがつてゲート酸化膜８上
に多結晶シリコンからなるゲート電極１０を形
成し、同ゲート電極１０をマスクとして砒素の
イオン注入、活性化を施してn+型のソース、
ドレイン（図示せず）を形成し、CVD−SiO2
膜Al配線の形成等を経た後、1000℃、60分間
の熱処理を施してｎチヤンネルMOS Ｉ Ｃを
製造した（第２図ｆ図示）。() Next, a gate electrode 10 made of polycrystalline silicon is formed on the gate oxide film 8 according to a conventional method, and using the gate electrode 10 as a mask, arsenic ions are implanted and activated to form an n + type source.
Form a drain (not shown) and CVD-SiO 2
After forming the film Al wiring, etc., heat treatment was performed at 1000° C. for 60 minutes to produce an n-channel MOS IC (shown in FIG. 2f).
しかして、上記実施例２においては素子間分離
膜９の中間付近に比抵抗が小さいリンドープ多結
晶シリコン薄層１１が形成され、これに配線を接
続することによつて、シールド又は内部配線の一
部としての機能を果たすので高耐圧化が可能とな
り、更に外部からのNaイオン等の汚染にも強く
高信頼性のMOS Ｉ Ｃを得ることができる。 In the second embodiment described above, a phosphorus-doped polycrystalline silicon thin layer 11 having a low specific resistance is formed near the middle of the element isolation film 9, and by connecting wiring to this thin layer 11, it can be used as a shield or an internal wiring. Since it functions as a part, it is possible to achieve a high breakdown voltage, and it is also possible to obtain a highly reliable MOS IC that is resistant to external contamination such as Na ions.
なお、本発明は上記実施例の如きｎチヤンネル
MOS Ｉ Ｃの製造のみに限らず、ｐチヤンネル
MOS Ｉ Ｃ、バイポーラＩ Ｃ、I2L、CCD等
にも同様に適用できるものである。 Note that the present invention is applicable to n-channels such as those in the above embodiments.
Not limited to MOS IC manufacturing, but also p-channel
It can be similarly applied to MOS IC, bipolar IC, I 2 L, CCD, etc.
以上詳述した如く、本発明によれば半導体基板
上に酸化膜及び窒化シリコン膜を介して材料層を
形成し、この材料層を選択酸化することによつ
て、該材料層の酸化終点を制御せずに、基板への
酸化を招くことなく該基板上に素子間分離膜を形
成でき、もつて半導体基板への熱影響を抑制する
と共にストレス発生を確実に防止でき、穴陥発生
の極めて少ない基板を有し、電気特性の良好で素
子の微細化を達成した半導体装置を製造し得る方
法を提供できるものである。 As detailed above, according to the present invention, a material layer is formed on a semiconductor substrate via an oxide film and a silicon nitride film, and the oxidation end point of the material layer is controlled by selectively oxidizing the material layer. It is possible to form an isolation film on the substrate without causing oxidation of the substrate, suppressing the thermal influence on the semiconductor substrate, reliably preventing the occurrence of stress, and minimizing the occurrence of pitting. It is possible to provide a method for manufacturing a semiconductor device that has a substrate, has good electrical characteristics, and has miniaturized elements.
第１図ａ〜ｆは本発明の実施例１におけるｎチ
ヤンネルMOS Ｉ Ｃの製造工程を示す断面図、
第２図ａ〜ｆは本発明の実施例２におけるｎチヤ
ンネルMOS Ｉ Ｃの製造工程を示す断面図であ
る。
１……ｐ型単結晶シリコン基板、２……熱酸化
膜、３……窒化シリコン膜、４……リンドープ多
結晶シリコン層、４′……残存多結晶シリコン
層、５……窒化シリコンパターン、６……p+型
のチヤンネルストツパ、７……厚い酸化膜、８…
…ゲート酸化膜、９……素子間分離膜、１０……
ゲート電極、１１……リンドープ多結晶シリコン
薄層。
1A to 1F are cross-sectional views showing the manufacturing process of an n-channel MOS IC in Example 1 of the present invention,
FIGS. 2a to 2f are cross-sectional views showing the manufacturing process of an n-channel MOS IC in Example 2 of the present invention. DESCRIPTION OF SYMBOLS 1...P-type single crystal silicon substrate, 2...Thermal oxide film, 3...Silicon nitride film, 4...Phosphorus-doped polycrystalline silicon layer, 4'...Remaining polycrystalline silicon layer, 5...Silicon nitride pattern, 6...p + type channel stopper, 7... thick oxide film, 8...
... Gate oxide film, 9 ... Inter-element isolation film, 10 ...
Gate electrode, 11... phosphorus-doped polycrystalline silicon thin layer.
Claims (1)
順次形成する工程と、この窒化シリコン膜上に前
記基板より酸化速度の速い材料層を形成する工程
と、この材料層上に耐酸化性マスクを選択的に形
成する工程と、この耐酸化性マスクを用いて前記
基板に該基板と同導電型の不純物をドーピングす
る工程と、前記耐酸化性マスクを用いて前記材料
層を選択酸化して厚い酸化膜を形成する工程と、
前記耐酸化性マスクを除去した後、露出した残存
材料層を少なくとも一部除去する工程とを具備し
たことを特徴とする半導体装置の製造方法。 ２ 半導体基板より酸化速度の速い材料として、
高濃度不純物ドープ多結晶シリコン、モリブデン
シリサイド及びタングステンシリサイドのうちの
少なくとも１つの材料を用いることを特徴とする
特許請求の範囲第１項記載の半導体装置の製造方
法。 ３ 耐酸化性マスクが窒化シリコンからなること
を特徴とする特許請求の範囲第１項又は第２項記
載の半導体装置の製造方法。 ４ 耐酸化性マスクの形成に用いるフオトレジス
トを不純物のドーピングマスクとして使用するこ
とを特徴とする特許請求の範囲第１項ないし第３
項いずれか記載の半導体装置の製造方法。 ５ 耐酸化性マスクの形成に用いるフオトレジス
トを該マスクの面積より大きくすることを特徴と
する特許請求の範囲第１項ないし第３項のいずれ
か記載の半導体装置の製造方法。[Claims] 1. A step of sequentially forming an oxide film and a silicon nitride film on a semiconductor substrate, a step of forming a layer of material having a faster oxidation rate than the substrate on this silicon nitride film, and a step of forming a layer of material on this material layer at a faster oxidation rate than that of the substrate. selectively forming an oxidation-resistant mask; doping the substrate with an impurity of the same conductivity type as the substrate using the oxidation-resistant mask; and forming the material layer using the oxidation-resistant mask. A step of selectively oxidizing to form a thick oxide film;
A method for manufacturing a semiconductor device, comprising the step of removing at least a portion of the exposed remaining material layer after removing the oxidation-resistant mask. 2 As a material with a faster oxidation rate than a semiconductor substrate,
2. The method of manufacturing a semiconductor device according to claim 1, wherein at least one material selected from highly impurity-doped polycrystalline silicon, molybdenum silicide, and tungsten silicide is used. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the oxidation-resistant mask is made of silicon nitride. 4. Claims 1 to 3, characterized in that the photoresist used to form the oxidation-resistant mask is used as a doping mask for impurities.
A method for manufacturing a semiconductor device according to any one of paragraphs. 5. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that the area of the photoresist used to form the oxidation-resistant mask is larger than that of the mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15614280A JPS5779640A (en) | 1980-11-06 | 1980-11-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15614280A JPS5779640A (en) | 1980-11-06 | 1980-11-06 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5779640A JPS5779640A (en) | 1982-05-18 |
| JPS628028B2 true JPS628028B2 (en) | 1987-02-20 |
Family
ID=15621235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15614280A Granted JPS5779640A (en) | 1980-11-06 | 1980-11-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5779640A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6222452A (en) * | 1985-07-22 | 1987-01-30 | Mitsubishi Electric Corp | Semiconductor device |
| US4818235A (en) * | 1987-02-10 | 1989-04-04 | Industry Technology Research Institute | Isolation structures for integrated circuits |
| JP2628511B2 (en) * | 1987-08-19 | 1997-07-09 | 工業技術院長 | Pattern formation method |
-
1980
- 1980-11-06 JP JP15614280A patent/JPS5779640A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5779640A (en) | 1982-05-18 |
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